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1. 发明申请

US20070238284A1 Touch panel fabrication method 审中-公开
标题翻译：触摸屏制作方法
公开(公告)号：US20070238284A1
公开(公告)日：2007-10-11
申请号：US11392590
申请日：2006-03-30
申请人： Chun-Hao Wang , Chin-Pei Hwang , Wen-Tsung Wang , Sung-Hao Chu
发明人： Chun-Hao Wang , Chin-Pei Hwang , Wen-Tsung Wang , Sung-Hao Chu
IPC分类号： H01L21/4763
CPC分类号： G06F3/045
摘要： A touch panel fabrication method includes the steps of (a) preparing a first substrate and a second substrate, (b) disposing a seal frame having an opening on the first substrate, (c) coupling the first substrate and the second substrate together by the seal frame such that a vacancy is defined by the first substrate, the second substrate and the seal frame, and (d) filling up the vacancy with a dielectric material through the opening of the seal frame.
摘要翻译：一种触摸面板制造方法，包括以下步骤：（a）准备第一基板和第二基板，（b）在第一基板上设置具有开口的密封框架，（c）将第一基板和第二基板连接在一起，密封框架，使得空隙由第一基板，第二基板和密封框架限定，以及（d）通过密封框架的开口用介电材料填充空位。

2. 外观设计

USD421761S Camera 失效
公开(公告)号：USD421761S
公开(公告)日：2000-03-21
申请号：US107051
申请日：1999-06-29
申请人： Chih-Hung Chang , Wen-Tsung Wang
设计人： Chih-Hung Chang , Wen-Tsung Wang

3. 发明授权

US06713338B2 Method for fabricating source/drain devices 有权
标题翻译：源极/漏极器件的制造方法
公开(公告)号：US06713338B2
公开(公告)日：2004-03-30
申请号：US10315992
申请日：2002-12-11
申请人： Wen-Tsung Wang , Yi-Tsung Jan , Sung-Min Wei , Chih-Cherng Liao , Zhe-Xiong Wu , Mao-Tsung Chen , Yuan-Heng Li
发明人： Wen-Tsung Wang , Yi-Tsung Jan , Sung-Min Wei , Chih-Cherng Liao , Zhe-Xiong Wu , Mao-Tsung Chen , Yuan-Heng Li
IPC分类号： H01L218238
CPC分类号： H01L29/66659 , H01L29/7835
摘要： A method for fabricating source/drain devices. A semiconductor substrate is provided with a gate formed thereon, a first doped area is formed on a first side of the gate on the semiconductor substrate, and a second doped area is formed on a second side of the gate on the semiconductor substrate in a manner such that the second doped area is separated from the gate by a predetermined distance. A patterned photo resist layer is formed on the semiconductor substrate having an opening on the second side, the exposed gate less than half the width of the gate. The semiconductor substrate is implanted and annealed to form a dual diffusion area on the second side of the gate using the patterned photo resist layer as a mask.
摘要翻译：一种用于制造源极/漏极器件的方法。半导体衬底上形成有栅极，在半导体衬底上的栅极的第一侧上形成第一掺杂区域，并且以半导体衬底上的栅极的第二侧上形成第二掺杂区域使得第二掺杂区域与栅极分离预定距离。在半导体衬底上形成图案化的光致抗蚀剂层，该半导体衬底在第二侧具有开口，暴露的栅极小于栅极宽度的一半。使用图案化的光致抗蚀剂层作为掩模，将半导体衬底注入和退火以在栅极的第二侧上形成双重扩散区域。

4. 发明申请

US20090134455A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD 审中-公开
标题翻译：半导体器件和制造方法
公开(公告)号：US20090134455A1
公开(公告)日：2009-05-28
申请号：US11946016
申请日：2007-11-27
申请人： Shih-Fang Lin , Meng-Yen Hsieh , Yi-Tsung Jan , Sung-Min Wei , Chia-Yi Lee , Chun-Yao Li , Han-Lung Tsai , Zhe-Xiong Wu , Wen-Tsung Wang
发明人： Shih-Fang Lin , Meng-Yen Hsieh , Yi-Tsung Jan , Sung-Min Wei , Chia-Yi Lee , Chun-Yao Li , Han-Lung Tsai , Zhe-Xiong Wu , Wen-Tsung Wang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7836 , H01L29/1087 , H01L29/66575
摘要： A semiconductor device including a substrate, a first well, a second well, a gate, a first doped region, and a second doped region. The substrate includes a first conductive type. The first well includes a second conductive type and is formed in the substrate. The second well includes the second conductive type and is formed in the substrate. The gate is formed on the substrate and overlaps the first and the second wells. The first doped region includes the second conductive type. The first doped region is formed in the first well and self-aligned with the gate. The second doped region includes the second conductive type. The second doped region is formed in the second well and self-aligned with the gate. The gate, the first and the second doped regions constitute a transistor.
摘要翻译：一种半导体器件，包括衬底，第一阱，第二阱，栅极，第一掺杂区域和第二掺杂区域。基板包括第一导电类型。第一阱包括第二导电类型并且形成在衬底中。第二阱包括第二导电类型并形成在衬底中。栅极形成在衬底上并与第一和第二阱重叠。第一掺杂区域包括第二导电类型。第一掺杂区形成在第一阱中并与栅极自对准。第二掺杂区域包括第二导电类型。第二掺杂区形成在第二阱中并与栅极自对准。栅极，第一和第二掺杂区域构成晶体管。

5. 发明授权

US06835636B2 Method for fabricating source/drain devices 有权
标题翻译：源极/漏极器件的制造方法
公开(公告)号：US06835636B2
公开(公告)日：2004-12-28
申请号：US10315980
申请日：2002-12-11
申请人： Yi-Tsung Jan , Wen-Tsung Wang , Sung-Min Wei , Chih-Cherng Liao , Zhe-Xiong Wu , Mao-Tsang Chen , Yuan-Heng Li
发明人： Yi-Tsung Jan , Wen-Tsung Wang , Sung-Min Wei , Chih-Cherng Liao , Zhe-Xiong Wu , Mao-Tsang Chen , Yuan-Heng Li
IPC分类号： H01L213205
CPC分类号： H01L29/66659 , H01L29/7835
摘要： A method for fabricating source/drain devices. A semiconductor substrate is provided with a gate formed on the semiconductor substrate, and a hard mask layer formed on the gate. A first doped area is formed on a first side of the gate on the semiconductor substrate, and a second doped area is formed on a second side of the gate on the semiconductor substrate in a manner such that the second doped area is separated from the gate by a predetermined distance. A patterned photo resist layer is formed on the semiconductor substrate having an opening on the second side, the exposed gate equal to half the width of the gate. The semiconductor substrate is implanted and annealed to form a dual diffusion area on the second side of the gate using the patterned photo resist layer and the hard mask layer as masks.
摘要翻译：一种用于制造源极/漏极器件的方法。在半导体衬底上设置有形成在半导体衬底上的栅极和形成在栅极上的硬掩模层。第一掺杂区域形成在半导体衬底上的栅极的第一侧上，并且第二掺杂区域以这样的方式形成在半导体衬底上的栅极的第二侧上，使得第二掺杂区域与栅极分离预定距离。在具有在第二侧上具有开口的半导体衬底上形成图案化的光致抗蚀剂层，暴露的栅极等于栅极宽度的一半。使用图案化的光致抗蚀剂层和硬掩模层作为掩模，将半导体衬底注入和退火以在栅极的第二侧上形成双重扩散区域。

6. 发明授权

US06276973B1 Contact of electrical connector 失效
标题翻译：电气连接器的接触
公开(公告)号：US06276973B1
公开(公告)日：2001-08-21
申请号：US09516474
申请日：2000-03-01
申请人： Yu Hsu Lin , Wen-Tsung Wang , Yu Hung Huang
发明人： Yu Hsu Lin , Wen-Tsung Wang , Yu Hung Huang
IPC分类号： H01R448
CPC分类号： H01R13/193
摘要： A contact of an electrical connector includes an upper section for engaging a pin of a central processing unit module, a lower section retained in a bore defined in a housing of the connector with a tail section extending therefrom for being electrically connected to a circuit board and a plurality of spaced connecting sections, serving as signal transmission channels, arranged between the upper and lower sections and electrically connected thereto to serve as electrical current channels. By increasing the number of the connecting sections, the total cross-sectional area of the electrical channels is increased which effectively reduces the inductance thereof.
摘要翻译：电连接器的触点包括用于接合中央处理单元模块的销的上部，保持在连接器的壳体中限定的孔中的下部，其中从其延伸的尾部用于电连接到电路板，多个间隔开的连接部分，用作信号传输通道，布置在上部和下部之间并与其电连接以用作电流通道。通过增加连接部分的数量，电通道的总横截面面积增加，这有效地降低了其电感。

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