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1. 发明授权

US07161204B2 DRAM capacitor structure with increased electrode support for preventing process damage and exposed electrode surface for increasing capacitor area 有权
标题翻译： DRAM电容器结构具有增加的电极支持，用于防止工艺损坏和暴露的电极表面，以增加电容器面积
公开(公告)号：US07161204B2
公开(公告)日：2007-01-09
申请号：US11098112
申请日：2005-04-04
申请人： Chun-Chieh Lin , Lan-Lin Chao , Chia-Shiung Tsai , Fu-Liang Yang , Chia-Hui Lin , Chanming Hu
发明人： Chun-Chieh Lin , Lan-Lin Chao , Chia-Shiung Tsai , Fu-Liang Yang , Chia-Hui Lin , Chanming Hu
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10852 , H01L27/0207 , H01L27/10817 , H01L28/91
摘要： A method for fabricating a high-density array of crown capacitors with increased capacitance while reducing process damage to the bottom electrodes is achieved. The process is particularly useful for crown capacitors for future DRAM circuits with minimum feature sizes of 0.18 micrometer or less. A conformal conducting layer is deposited over trenches in an interlevel dielectric (ILD) layer, and is polished back to form capacitor bottom electrodes. A novel photoresist mask and etching are then used to pattern the ILD layer to provide a protective interlevel dielectric structure between capacitors. The protective structures prevent damage to the bottom electrodes during subsequent processing. The etching also exposes portions of the outer surface of bottom electrodes for increased capacitance (>50%). In a first embodiment the ILD structure is formed between pairs of adjacent bottom electrodes, and in a second embodiment the ILD structure is formed between four adjacent bottom electrodes.
摘要翻译：实现了一种用于制造具有增加的电容的高密度阵列的冠状电容器的方法，同时减少了对底部电极的工艺损伤。该过程对于具有最小特征尺寸为0.18微米或更小的未来DRAM电路的冠电容器特别有用。在层间电介质（ILD）层中的沟槽上沉积共形导电层，并将其抛光回形成电容器底部电极。然后使用新颖的光致抗蚀剂掩模和蚀刻来对ILD层进行图案化，以在电容器之间提供保护层间电介质结构。保护结构可防止在后续处理期间损坏底部电极。蚀刻还暴露了底部电极的外表面的部分以增加电容（> 50％）。在第一实施例中，ILD结构形成在成对的相邻底部电极之间，并且在第二实施例中，ILD结构形成在四个相邻的底部电极之间。

2. 发明申请

US20050179076A1 Method of forming DRAM capactiors with protected outside crown surface for more robust structures 有权
标题翻译：用于形成具有受保护的外表冠表面的DRAM盖板的方法用于更坚固的结构
公开(公告)号：US20050179076A1
公开(公告)日：2005-08-18
申请号：US11098112
申请日：2005-04-04
申请人： Chun-Chieh Lin , Lan-Lin Chao , Chia-Hui Lin , Fu-Liang Yang , Chia-Shiung Tsai , Chanming Hu
发明人： Chun-Chieh Lin , Lan-Lin Chao , Chia-Hui Lin , Fu-Liang Yang , Chia-Shiung Tsai , Chanming Hu
IPC分类号： H01L21/02 , H01L21/336 , H01L21/8242 , H01L27/02 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/0207 , H01L27/10817 , H01L28/91
摘要： A method for fabricating a high-density array of crown capacitors with increased capacitance while reducing process damage to the bottom electrodes is achieved. The process is particularly useful for crown capacitors for future DRAM circuits with minimum feature sizes of 0.18 micrometer or less. A conformal conducting layer is deposited over trenches in an interlevel dielectric (ILD) layer, and is polished back to form capacitor bottom electrodes. A novel photoresist mask and etching are then used to pattern the ILD layer to provide a protective interlevel dielectric structure between capacitors. The protective structures prevent damage to the bottom electrodes during subsequent processing. The etching also exposes portions of the outer surface of bottom electrodes for increased capacitance (>50%). In a first embodiment the ILD structure is formed between pairs of adjacent bottom electrodes, and in a second embodiment the ILD structure is formed between four adjacent bottom electrodes.
摘要翻译：实现了一种用于制造具有增加的电容的高密度阵列的冠状电容器的方法，同时减少了对底部电极的工艺损伤。该过程对于具有最小特征尺寸为0.18微米或更小的未来DRAM电路的冠电容器特别有用。在层间电介质（ILD）层中的沟槽上沉积共形导电层，并将其抛光回形成电容器底部电极。然后使用新颖的光致抗蚀剂掩模和蚀刻来对ILD层进行图案以在电容器之间提供保护性层间电介质结构。保护结构可防止在后续处理期间损坏底部电极。蚀刻还暴露了底部电极的外表面的部分以增加电容（> 50％）。在第一实施例中，ILD结构形成在成对的相邻底部电极之间，并且在第二实施例中，ILD结构形成在四个相邻的底部电极之间。

3. 发明授权

US06875655B2 Method of forming DRAM capacitors with protected outside crown surface for more robust structures 有权
标题翻译：形成具有受保护的外冠表面的DRAM电容器的方法用于更坚固的结构
公开(公告)号：US06875655B2
公开(公告)日：2005-04-05
申请号：US10802564
申请日：2004-03-17
申请人： Chun-Chieh Lin , Lan-Lin Chao , Chia-Hui Lin , Fu-Liang Yang , Chia-Shiung Tsai , Chanming Hu
发明人： Chun-Chieh Lin , Lan-Lin Chao , Chia-Hui Lin , Fu-Liang Yang , Chia-Shiung Tsai , Chanming Hu
IPC分类号： H01L21/02 , H01L21/336 , H01L21/8242 , H01L27/02 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/0207 , H01L27/10817 , H01L28/91
摘要： A method for fabricating a high-density array of crown capacitors with increased capacitance while reducing process damage to the bottom electrodes is achieved. The process is particularly useful for crown capacitors for future DRAM circuits with minimum feature sizes of 0.18 micrometer or less. A conformal conducting layer is deposited over trenches in an interlevel dielectric (ILD) layer, and is polished back to form capacitor bottom electrodes. A novel photoresist mask and etching are then used to pattern the ILD layer to provide a protective interlevel dielectric structure between capacitors. The protective structures prevent damage to the bottom electrodes during subsequent processing. The etching also exposes portions of the outer surface of bottom electrodes for increased capacitance (>50%). In a first embodiment the ILD structure is formed between pairs of adjacent bottom electrodes, and in a second embodiment the ILD structure is formed between four adjacent bottom electrodes.
摘要翻译：实现了一种用于制造具有增加的电容的高密度阵列的冠状电容器的方法，同时减少了对底部电极的工艺损伤。该过程对于具有最小特征尺寸为0.18微米或更小的未来DRAM电路的冠电容器特别有用。在层间电介质（ILD）层中的沟槽上沉积共形导电层，并将其抛光回形成电容器底部电极。然后使用新颖的光致抗蚀剂掩模和蚀刻来对ILD层进行图案以在电容器之间提供保护性层间电介质结构。保护结构可防止在后续处理期间损坏底部电极。蚀刻还暴露了底部电极的外表面的部分以增加电容（> 50％）。在第一实施例中，ILD结构形成在成对的相邻底部电极之间，并且在第二实施例中，ILD结构形成在四个相邻的底部电极之间。

4. 发明授权

US09054121B2 MEMS structures and methods for forming the same 有权
标题翻译： MEMS结构及其形成方法
公开(公告)号：US09054121B2
公开(公告)日：2015-06-09
申请号：US13280075
申请日：2011-10-24
申请人： Ping-Yin Liu , Xin-Hua Huang , Hsin-Ting Huang , Yuan-Chih Hsieh , Jung-Huei Peng , Lan-Lin Chao , Chia-Shiung Tsai , Chun-Wen Cheng
发明人： Ping-Yin Liu , Xin-Hua Huang , Hsin-Ting Huang , Yuan-Chih Hsieh , Jung-Huei Peng , Lan-Lin Chao , Chia-Shiung Tsai , Chun-Wen Cheng
IPC分类号： H01L21/31 , H01L49/02 , B81C1/00 , H01G5/16
CPC分类号： B81B7/0058 , B81B3/0005 , B81B3/0021 , B81C1/00269 , B81C1/00793 , B81C2201/053 , B81C2203/0109 , H01G5/16 , H01L28/60
摘要： A method includes forming a MEMS device, forming a bond layer adjacent the MEMS device, and forming a protection layer over the bond layer. The steps of forming the bond layer and the protection layer include in-situ deposition of the bond layer and the protection layer.
摘要翻译：一种方法包括形成MEMS器件，形成与MEMS器件相邻的接合层，并在接合层上形成保护层。形成接合层和保护层的步骤包括接合层和保护层的原位沉积。

5. 发明授权

US08945344B2 Systems and methods of separating bonded wafers 有权
标题翻译：分离粘结晶片的系统和方法
公开(公告)号：US08945344B2
公开(公告)日：2015-02-03
申请号：US13554751
申请日：2012-07-20
申请人： Xin-Hua Huang , Ping-Yin Liu , Hung-Hua Lin , Yuan-Chih Hsieh , Lan-Lin Chao , Chia-Shiung Tsai
发明人： Xin-Hua Huang , Ping-Yin Liu , Hung-Hua Lin , Yuan-Chih Hsieh , Lan-Lin Chao , Chia-Shiung Tsai
IPC分类号： B32B38/10
CPC分类号： H01L21/67092 , Y10T156/11 , Y10T156/1132 , Y10T156/1153 , Y10T156/1189 , Y10T156/1911 , Y10T156/1944 , Y10T156/1972
摘要： Systems and methods of separating bonded wafers are disclosed. In one embodiment, a system for separating bonded wafers includes a support for the bonded wafers and means for applying a sheer force to the bonded wafers. The system also includes means for applying a vacuum to the bonded wafers.
摘要翻译：公开了分离键合晶片的系统和方法。在一个实施例中，用于分离接合的晶片的系统包括用于接合的晶片的支撑件和用于向结合的晶片施加纯粹的力的装置。该系统还包括用于向接合晶片施加真空的装置。

6. 发明授权

US08846129B2 Biological sensing structures and methods of forming the same 有权
标题翻译：生物传感结构及其形成方法
公开(公告)号：US08846129B2
公开(公告)日：2014-09-30
申请号：US13372141
申请日：2012-02-13
申请人： Hung-Hua Lin , Li-Cheng Chu , Ming-Tung Wu , Yuan-Chih Hsieh , Lan-Lin Chao , Chia-Shiung Tsai
发明人： Hung-Hua Lin , Li-Cheng Chu , Ming-Tung Wu , Yuan-Chih Hsieh , Lan-Lin Chao , Chia-Shiung Tsai
IPC分类号： B05D3/10 , C12Q1/68 , H01L21/311
CPC分类号： G01N21/55 , G01N21/01 , G01N21/253 , G01N27/327 , G01N33/483 , G01N2021/0106 , G01N2201/0636
摘要： A method of forming of biological sensing structures including a portion of a substrate is recessed to form a plurality of mesas in the substrate. Each of the plurality of mesas has a top surface and a sidewall surface. A first light reflecting layer is deposited over the top surface and the sidewall surface of each mesa. A filling material is formed over a first portion of the first light reflecting layer. A stop layer is deposited over the filling material and a second portion of the first light reflecting layer. A sacrificial layer is formed over the stop layer and is planarized exposing the stop layer. A first opening is formed in the stop layer and the first light reflecting layer. A second light reflecting layer is deposited over the first opening. A second opening is formed in the second light reflecting layer.
摘要翻译：形成包括衬底的一部分的生物感测结构的方法被凹进以在衬底中形成多个台面。多个台面中的每一个具有顶表面和侧壁表面。第一光反射层沉积在每个台面的顶表面和侧壁表面上。在第一光反射层的第一部分上形成填充材料。沉积在填充材料上的停止层和第一光反射层的第二部分。牺牲层形成在停止层上并且被平坦化地暴露停止层。在停止层和第一光反射层中形成第一开口。第二光反射层沉积在第一开口上。在第二光反射层中形成第二开口。

7. 发明授权

US08809123B2 Three dimensional integrated circuit structures and hybrid bonding methods for semiconductor wafers 有权
标题翻译：半导体晶圆的三维集成电路结构和混合键合方法
公开(公告)号：US08809123B2
公开(公告)日：2014-08-19
申请号：US13488745
申请日：2012-06-05
申请人： Ping-Yin Liu , Xin-Hua Huang , Lan-Lin Chao , Chia-Shiung Tsai
发明人： Ping-Yin Liu , Xin-Hua Huang , Lan-Lin Chao , Chia-Shiung Tsai
IPC分类号： H01L21/00
CPC分类号： H01L25/0657 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/80 , H01L24/92 , H01L24/94 , H01L25/50 , H01L2224/03845 , H01L2224/05026 , H01L2224/05147 , H01L2224/05571 , H01L2224/056 , H01L2224/05611 , H01L2224/08147 , H01L2224/08502 , H01L2224/80097 , H01L2224/80203 , H01L2224/80204 , H01L2224/80345 , H01L2224/80805 , H01L2224/80896 , H01L2224/80986 , H01L2224/92 , H01L2224/9202 , H01L2224/94 , H01L2924/00014 , H01L2924/01322 , H01L2924/1461 , H01L2224/80 , H01L2224/83 , H01L2924/00012 , H01L2924/01032 , H01L2924/00 , H01L2224/05552
摘要： Three dimensional integrated circuit (3DIC) structures and hybrid bonding methods for semiconductor wafers are disclosed. A 3DIC structure includes a first semiconductor device having first conductive pads disposed within a first insulating material on a top surface thereof, the first conductive pads having a first recess on a top surface thereof. The 3DIC structure includes a second semiconductor device having second conductive pads disposed within a second insulating material on a top surface thereof coupled to the first semiconductor device, the second conductive pads having a second recess on a top surface thereof. A sealing layer is disposed between the first conductive pads and the second conductive pads in the first recess and the second recess. The sealing layer bonds the first conductive pads to the second conductive pads. The first insulating material is bonded to the second insulating material.
摘要翻译：公开了用于半导体晶片的三维集成电路（3DIC）结构和混合键合方法。 3DIC结构包括第一半导体器件，其第一导电焊盘设置在其顶表面上的第一绝缘材料内，第一导电焊盘在其顶表面上具有第一凹部。 3DIC结构包括第二半导体器件，其第二导电焊盘设置在耦合到第一半导体器件的顶表面上的第二绝缘材料内，第二导电焊盘在其顶表面上具有第二凹槽。密封层设置在第一导电垫和第一凹槽和第二凹槽中的第二导电垫之间。密封层将第一导电焊盘连接到第二导电焊盘。第一绝缘材料结合到第二绝缘材料上。

8. 发明申请

US20140020818A1 Systems and Methods of Separating Bonded Wafers 有权
标题翻译：分离粘结晶片的系统和方法
公开(公告)号：US20140020818A1
公开(公告)日：2014-01-23
申请号：US13554751
申请日：2012-07-20
申请人： Xin-Hua Huang , Ping-Yin Liu , Hung-Hua Lin , Yuan-Chih Hsieh , Lan-Lin Chao , Chia-Shiung Tsai
发明人： Xin-Hua Huang , Ping-Yin Liu , Hung-Hua Lin , Yuan-Chih Hsieh , Lan-Lin Chao , Chia-Shiung Tsai
IPC分类号： B32B38/10 , B32B37/02
CPC分类号： H01L21/67092 , Y10T156/11 , Y10T156/1132 , Y10T156/1153 , Y10T156/1189 , Y10T156/1911 , Y10T156/1944 , Y10T156/1972
摘要： Systems and methods of separating bonded wafers are disclosed. In one embodiment, a system for separating bonded wafers includes a support for the bonded wafers and means for applying a sheer force to the bonded wafers. The system also includes means for applying a vacuum to the bonded wafers.
摘要翻译：公开了分离键合晶片的系统和方法。在一个实施例中，用于分离接合的晶片的系统包括用于接合的晶片的支撑件和用于向结合的晶片施加纯粹的力的装置。该系统还包括用于向接合晶片施加真空的装置。

9. 发明申请

US20140011324A1 Hybrid Bonding Systems and Methods for Semiconductor Wafers 有权
标题翻译：半导体晶片的混合键合系统和方法
公开(公告)号：US20140011324A1
公开(公告)日：2014-01-09
申请号：US13542507
申请日：2012-07-05
申请人： Ping-Yin Liu , Shih-Wei Lin , Xin-Hua Huang , Lan-Lin Chao , Chia-Shiung Tsai
发明人： Ping-Yin Liu , Shih-Wei Lin , Xin-Hua Huang , Lan-Lin Chao , Chia-Shiung Tsai
IPC分类号： H01L21/50
CPC分类号： H01L24/80 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/27 , H01L24/74 , H01L24/94 , H01L2224/02215 , H01L2224/0361 , H01L2224/03616 , H01L2224/0381 , H01L2224/05647 , H01L2224/05687 , H01L2224/08145 , H01L2224/74 , H01L2224/7501 , H01L2224/75101 , H01L2224/7565 , H01L2224/75753 , H01L2224/75824 , H01L2224/80004 , H01L2224/80007 , H01L2224/8001 , H01L2224/80011 , H01L2224/80013 , H01L2224/80014 , H01L2224/80065 , H01L2224/80075 , H01L2224/80097 , H01L2224/80121 , H01L2224/80136 , H01L2224/80203 , H01L2224/80895 , H01L2224/80896 , H01L2224/83889 , H01L2224/94 , H01L2924/00014 , H01L2924/1461 , H01L2924/351 , Y10T156/15 , Y10T156/1744 , H01L2924/00012 , H01L2224/80 , H01L2924/05442 , H01L2924/00
摘要： Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.
摘要翻译：公开了用于半导体晶片的混合键合系统和方法。在一个实施例中，用于半导体晶片的混合键合系统包括腔室和设置在腔室内的多个子腔室。机器人处理器设置在腔室内，其适于移动多个子室内的室内的多个半导体晶片。多个子室包括适于从多个半导体晶片去除保护层的第一子室，以及适于在混合结合多个半导体之前激活多个半导体晶片的顶表面的第二子室晶圆在一起多个子室还包括适于对准多个半导体晶片并将多个半导体晶片混合地结合在一起的第三子室。

10. 发明授权

US08598687B2 Semiconductor having a high aspect ratio via 有权
公开(公告)号：US08598687B2
公开(公告)日：2013-12-03
申请号：US13481574
申请日：2012-05-25
申请人： Yuan-Chih Hsieh , Richard Chu , Ming-Tung Wu , Martin Liu , Lan-Lin Chao , Chia-Shiung Tsai
发明人： Yuan-Chih Hsieh , Richard Chu , Ming-Tung Wu , Martin Liu , Lan-Lin Chao , Chia-Shiung Tsai
IPC分类号： H01L29/40
CPC分类号： H01L23/5384 , H01L21/76802 , H01L21/76831 , H01L21/7684 , H01L21/7685 , H01L21/76877 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2225/06541 , H01L2225/06548 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having via sidewall surfaces defined by a semiconductor substrate. The via sidewall surfaces have a first portion and a second portion. A conductive layer is disposed in the via on the first portion of the via sidewall surfaces, and a dielectric layer is disposed on the second portion of the via sidewall surfaces. The dielectric layer is disposed between the second portion of the via sidewall surfaces and the conductive layer. In an example, the dielectric layer is an oxide layer.

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