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1. 发明授权

US06875655B2 Method of forming DRAM capacitors with protected outside crown surface for more robust structures 有权
标题翻译：形成具有受保护的外冠表面的DRAM电容器的方法用于更坚固的结构
公开(公告)号：US06875655B2
公开(公告)日：2005-04-05
申请号：US10802564
申请日：2004-03-17
申请人： Chun-Chieh Lin , Lan-Lin Chao , Chia-Hui Lin , Fu-Liang Yang , Chia-Shiung Tsai , Chanming Hu
发明人： Chun-Chieh Lin , Lan-Lin Chao , Chia-Hui Lin , Fu-Liang Yang , Chia-Shiung Tsai , Chanming Hu
IPC分类号： H01L21/02 , H01L21/336 , H01L21/8242 , H01L27/02 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/0207 , H01L27/10817 , H01L28/91
摘要： A method for fabricating a high-density array of crown capacitors with increased capacitance while reducing process damage to the bottom electrodes is achieved. The process is particularly useful for crown capacitors for future DRAM circuits with minimum feature sizes of 0.18 micrometer or less. A conformal conducting layer is deposited over trenches in an interlevel dielectric (ILD) layer, and is polished back to form capacitor bottom electrodes. A novel photoresist mask and etching are then used to pattern the ILD layer to provide a protective interlevel dielectric structure between capacitors. The protective structures prevent damage to the bottom electrodes during subsequent processing. The etching also exposes portions of the outer surface of bottom electrodes for increased capacitance (>50%). In a first embodiment the ILD structure is formed between pairs of adjacent bottom electrodes, and in a second embodiment the ILD structure is formed between four adjacent bottom electrodes.
摘要翻译：实现了一种用于制造具有增加的电容的高密度阵列的冠状电容器的方法，同时减少了对底部电极的工艺损伤。该过程对于具有最小特征尺寸为0.18微米或更小的未来DRAM电路的冠电容器特别有用。在层间电介质（ILD）层中的沟槽上沉积共形导电层，并将其抛光回形成电容器底部电极。然后使用新颖的光致抗蚀剂掩模和蚀刻来对ILD层进行图案以在电容器之间提供保护性层间电介质结构。保护结构可防止在后续处理期间损坏底部电极。蚀刻还暴露了底部电极的外表面的部分以增加电容（> 50％）。在第一实施例中，ILD结构形成在成对的相邻底部电极之间，并且在第二实施例中，ILD结构形成在四个相邻的底部电极之间。

2. 发明申请

US20050179076A1 Method of forming DRAM capactiors with protected outside crown surface for more robust structures 有权
标题翻译：用于形成具有受保护的外表冠表面的DRAM盖板的方法用于更坚固的结构
公开(公告)号：US20050179076A1
公开(公告)日：2005-08-18
申请号：US11098112
申请日：2005-04-04
申请人： Chun-Chieh Lin , Lan-Lin Chao , Chia-Hui Lin , Fu-Liang Yang , Chia-Shiung Tsai , Chanming Hu
发明人： Chun-Chieh Lin , Lan-Lin Chao , Chia-Hui Lin , Fu-Liang Yang , Chia-Shiung Tsai , Chanming Hu
IPC分类号： H01L21/02 , H01L21/336 , H01L21/8242 , H01L27/02 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/0207 , H01L27/10817 , H01L28/91
摘要： A method for fabricating a high-density array of crown capacitors with increased capacitance while reducing process damage to the bottom electrodes is achieved. The process is particularly useful for crown capacitors for future DRAM circuits with minimum feature sizes of 0.18 micrometer or less. A conformal conducting layer is deposited over trenches in an interlevel dielectric (ILD) layer, and is polished back to form capacitor bottom electrodes. A novel photoresist mask and etching are then used to pattern the ILD layer to provide a protective interlevel dielectric structure between capacitors. The protective structures prevent damage to the bottom electrodes during subsequent processing. The etching also exposes portions of the outer surface of bottom electrodes for increased capacitance (>50%). In a first embodiment the ILD structure is formed between pairs of adjacent bottom electrodes, and in a second embodiment the ILD structure is formed between four adjacent bottom electrodes.
摘要翻译：实现了一种用于制造具有增加的电容的高密度阵列的冠状电容器的方法，同时减少了对底部电极的工艺损伤。该过程对于具有最小特征尺寸为0.18微米或更小的未来DRAM电路的冠电容器特别有用。在层间电介质（ILD）层中的沟槽上沉积共形导电层，并将其抛光回形成电容器底部电极。然后使用新颖的光致抗蚀剂掩模和蚀刻来对ILD层进行图案以在电容器之间提供保护性层间电介质结构。保护结构可防止在后续处理期间损坏底部电极。蚀刻还暴露了底部电极的外表面的部分以增加电容（> 50％）。在第一实施例中，ILD结构形成在成对的相邻底部电极之间，并且在第二实施例中，ILD结构形成在四个相邻的底部电极之间。

3. 发明授权

US07161204B2 DRAM capacitor structure with increased electrode support for preventing process damage and exposed electrode surface for increasing capacitor area 有权
标题翻译： DRAM电容器结构具有增加的电极支持，用于防止工艺损坏和暴露的电极表面，以增加电容器面积
公开(公告)号：US07161204B2
公开(公告)日：2007-01-09
申请号：US11098112
申请日：2005-04-04
申请人： Chun-Chieh Lin , Lan-Lin Chao , Chia-Shiung Tsai , Fu-Liang Yang , Chia-Hui Lin , Chanming Hu
发明人： Chun-Chieh Lin , Lan-Lin Chao , Chia-Shiung Tsai , Fu-Liang Yang , Chia-Hui Lin , Chanming Hu
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10852 , H01L27/0207 , H01L27/10817 , H01L28/91
摘要： A method for fabricating a high-density array of crown capacitors with increased capacitance while reducing process damage to the bottom electrodes is achieved. The process is particularly useful for crown capacitors for future DRAM circuits with minimum feature sizes of 0.18 micrometer or less. A conformal conducting layer is deposited over trenches in an interlevel dielectric (ILD) layer, and is polished back to form capacitor bottom electrodes. A novel photoresist mask and etching are then used to pattern the ILD layer to provide a protective interlevel dielectric structure between capacitors. The protective structures prevent damage to the bottom electrodes during subsequent processing. The etching also exposes portions of the outer surface of bottom electrodes for increased capacitance (>50%). In a first embodiment the ILD structure is formed between pairs of adjacent bottom electrodes, and in a second embodiment the ILD structure is formed between four adjacent bottom electrodes.
摘要翻译：实现了一种用于制造具有增加的电容的高密度阵列的冠状电容器的方法，同时减少了对底部电极的工艺损伤。该过程对于具有最小特征尺寸为0.18微米或更小的未来DRAM电路的冠电容器特别有用。在层间电介质（ILD）层中的沟槽上沉积共形导电层，并将其抛光回形成电容器底部电极。然后使用新颖的光致抗蚀剂掩模和蚀刻来对ILD层进行图案化，以在电容器之间提供保护层间电介质结构。保护结构可防止在后续处理期间损坏底部电极。蚀刻还暴露了底部电极的外表面的部分以增加电容（> 50％）。在第一实施例中，ILD结构形成在成对的相邻底部电极之间，并且在第二实施例中，ILD结构形成在四个相邻的底部电极之间。

4. 发明申请

US20060113616A1 Selective spacer layer deposition method for forming spacers with different widths 审中-公开
标题翻译：用于形成具有不同宽度的间隔物的选择性间隔层沉积方法
公开(公告)号：US20060113616A1
公开(公告)日：2006-06-01
申请号：US11206613
申请日：2005-08-18
申请人： Ai-Sen Liu , Baw-Ching Perng , Ming-Ta Lei , Yih-Shung Lin , Cheng-Chung Lin , Chia-Hui Lin
发明人： Ai-Sen Liu , Baw-Ching Perng , Ming-Ta Lei , Yih-Shung Lin , Cheng-Chung Lin , Chia-Hui Lin
IPC分类号： H01L29/94
CPC分类号： H01L21/823468 , H01L21/3105 , H01L21/3144 , H01L21/823456 , H01L29/6656
摘要： A method of forming spacers with different widths on a semiconductor substrate, includes the steps of disposing a first spacer layer over the substrate, defining the first spacer layer into a plurality of spacers of a first width, and disposing a second spacer layer selectively over the first spacer layer of a number of the spacers preselected for the second spacer layer, the predetermined number of the spacers with the second spacer layer each having a second width which is different from the first width.
摘要翻译：一种在半导体衬底上形成具有不同宽度的间隔物的方法，包括以下步骤：在衬底上设置第一间隔层，将第一间隔层限定为多个第一宽度的间隔物，并且在第为第二间隔层预选的多个间隔物的第一间隔层，具有第二间隔层的预定数量的间隔物各自具有与第一宽度不同的第二宽度。

5. 发明授权

US07011929B2 Method for forming multiple spacer widths 失效
标题翻译：形成多个间隔物宽度的方法
公开(公告)号：US07011929B2
公开(公告)日：2006-03-14
申请号：US10340245
申请日：2003-01-09
申请人： Ming-Ta Lei , Yih-Shung Lin , Ai-Sen Liu , Cheng-Chung Lin , Baw-Ching Perng , Chia-Hui Lin
发明人： Ming-Ta Lei , Yih-Shung Lin , Ai-Sen Liu , Cheng-Chung Lin , Baw-Ching Perng , Chia-Hui Lin
IPC分类号： H01L21/302
CPC分类号： H01L21/823468
摘要： A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a plurality of gate structures formed overlying a substrate and a plurality of dielectric layers formed substantially conformally overlying the gate structures; exposing a first selected portion of the plurality followed by anisotropically etching through a thickness portion comprising at least the uppermost dielectric layer to form a first sidewall spacer width; exposing a first subsequent selected portion of the plurality followed by etching through at least a thickness portion of the uppermost dielectric layer; and, exposing a second subsequent selected portion of the plurality followed by anisotropically etching through at least a thickness portion of the uppermost dielectric layer to form a subsequent sidewall spacer width.
摘要翻译：一种形成多个栅极侧壁间隔物的方法，每个栅极侧壁间隔件包括不同的相关栅极侧壁间隔物宽度，包括提供形成在衬底上的多个栅极结构和基本上共形地覆盖栅极结构的多个电介质层; 暴露多个的第一选定部分，然后通过各向异性蚀刻穿过包括至少最上面的介电层的厚度部分以形成第一侧壁间隔物宽度; 暴露多个的第一后续选定部分，然后蚀刻通过至少最上层介电层的厚度部分; 并且暴露多个随后的第二部分，然后通过各向异性蚀刻穿过至少最上面的介电层的厚度部分以形成随后的侧壁间隔物宽度。

6. 发明授权

US06982135B2 Pattern compensation for stitching 失效
标题翻译：拼接图案补偿
公开(公告)号：US06982135B2
公开(公告)日：2006-01-03
申请号：US10402590
申请日：2003-03-28
申请人： Chung-Hsing Chang , Chien-Hung Lin , Burn J. Lin , Chia-Hui Lin , Chih-Cheng Chin , Chin-Hsiang Lin , Fu-Jye Liang , Jeng-Horng Chen , Bang-Ching Ho
发明人： Chung-Hsing Chang , Chien-Hung Lin , Burn J. Lin , Chia-Hui Lin , Chih-Cheng Chin , Chin-Hsiang Lin , Fu-Jye Liang , Jeng-Horng Chen , Bang-Ching Ho
IPC分类号： G03F9/00 , G03F7/20
CPC分类号： G03F1/20 , G03B27/42 , G03F1/00 , G03F7/70475
摘要： A method for transferring a pattern from a mask to a substrate (or wafer), comprises dividing a mask generation data file into a plurality of segments. The segments include a main pattern area and a stitching area. Each stitching area contains a respective common pattern. An image of an illuminated portion of the main pattern area is formed. Connection ends of the segments in a substrate area (or wafer area) are illuminated with an illumination beam. An image of the illuminated portion of the main pattern area is formed, and a halftone gray level dosage distribution is produced in the substrate area (or wafer area) corresponding to the common pattern. The common patterns of adjacent segments substantially overlap in the substrate area (or wafer area).
摘要翻译：将图案从掩模转印到基板（或晶片）的方法包括将掩模生成数据文件分割成多个段。片段包括主图案区域和缝合区域。每个缝合区域包含各自的共同图案。形成主图案区域的照明部分的图像。衬底区域（或晶片区域）中的段的连接端用照明光束照射。形成主图案区域的照明部分的图像，并且在对应于共同图案的基板区域（或晶片区域）中产生半色调灰度级剂量分布。相邻段的共同图案在衬底区域（或晶片区域）中基本上重叠。

7. 发明授权

US6051347A Application of e-beam proximity over-correction to compensate optical proximity effect in optical lithography process 有权
标题翻译：电子束接近过校正的应用来补偿光学光刻工艺中的光学邻近效应
公开(公告)号：US6051347A
公开(公告)日：2000-04-18
申请号：US270595
申请日：1999-03-18
申请人： San-De Tzu , Chia-Hui Lin
发明人： San-De Tzu , Chia-Hui Lin
IPC分类号： G03F7/20 , G03C5/00
CPC分类号： G03F7/70441 , Y10S430/143
摘要： A method of correcting, or compensating for errors encountered in the transfer of patterns is disclosed for use with high resolution e-beam lithography. In a first embodiment, optical proximity effects are incorporated into the e-beam proximity effects by superimposing the two effects to arrive at a compensated dosage level database to produce the desired patterns. In a second embodiment, etching effects are also superimposed on the previous driving database by compensating the e-beam proximity data twice, that is, by over correcting it, to further improve the transfer of patterns without the undesirable effects. It is shown that corrections for a number of other process steps can also be incorporated into the database that drives the e-beam lithography machine in order to achieve high resolution patterns of about one-quarter-micron technology.
摘要翻译：公开了一种校正或补偿在图案传送中遇到的错误的方法，用于高分辨率电子束光刻。在第一实施例中，通过叠加两个效应来将光学邻近效应并入到电子束邻近效应中，以得到补偿剂量水平数据库以产生期望的图案。在第二实施例中，通过补偿电子束邻近数据两次，即通过对其进行过度校正，也可以对先前的驱动数据库叠加蚀刻效果，以进一步改善图案的传送而不产生不良影响。显示出许多其他工艺步骤的校正也可以并入驱动电子束光刻机的数据库中，以实现约四分之一微米技术的高分辨率图案。

8. 发明授权

US07176137B2 Method for multiple spacer width control 有权
标题翻译：多间隔宽度控制方法
公开(公告)号：US07176137B2
公开(公告)日：2007-02-13
申请号：US10435009
申请日：2003-05-09
申请人： Baw-Ching Perng , Yih-Shung Lin , Ming-Ta Lei , Ai-Sen Liu , Chia-Hui Lin , Cheng-Chung Lin
发明人： Baw-Ching Perng , Yih-Shung Lin , Ming-Ta Lei , Ai-Sen Liu , Chia-Hui Lin , Cheng-Chung Lin
IPC分类号： H01L21/302
CPC分类号： H01L29/6656 , H01L21/823468
摘要： A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a first plurality of gate structures; blanket depositing a first dielectric layer over the first plurality of gate structures; blanket depositing a second dielectric layer over the first dielectric layer; etching back through a thickness of the first and second dielectric layers; blanket depositing a first photoresist layer to cover the first plurality and patterning to selectively expose at least a second plurality of gate structures; isotropically etching the at least a second plurality of gate structures for a predetermined time period to selectively etch away a predetermined portion of the first dielectric layer; and, selectively etching away the second dielectric layer to leave gate structures comprising a plurality of associated sidewall spacer widths.
摘要翻译：形成多个栅极侧壁间隔物的方法，每个栅极侧壁间隔件包括不同的相关栅极侧壁间隔物宽度，包括提供第一多个栅极结构; 在第一多个栅极结构上覆盖沉积第一介电层; 在第一介电层上铺设第二介电层; 通过第一和第二介电层的厚度回蚀; 覆盖沉积第一光致抗蚀剂层以覆盖第一多个并且图案化以选择性地暴露至少第二多个栅极结构; 对所述至少第二多个栅极结构进行各向同性蚀刻预定的时间段以选择性地蚀刻掉所述第一介电层的预定部分; 并且选择性地蚀刻掉第二介电层以留下包括多个相关联的侧壁间隔物宽度的栅极结构。

9. 发明申请

US20050004806A1 Automatic patent claim reader and computer-aided claim reading method 审中-公开
标题翻译：自动专利权利要求阅读器和计算机辅助索赔阅读方法
公开(公告)号：US20050004806A1
公开(公告)日：2005-01-06
申请号：US10601164
申请日：2003-06-20
申请人： Dah-Chih Lin , Jeffrey Liou , Joseph Du , Chia-Hui Lin , Shih-Wen Tu , Hsien_Ying Tseng , Chun Chen , Yueh-Ching Lee
发明人： Dah-Chih Lin , Jeffrey Liou , Joseph Du , Chia-Hui Lin , Shih-Wen Tu , Hsien_Ying Tseng , Chun Chen , Yueh-Ching Lee
IPC分类号： G06F17/27 , G06Q10/00 , G06F17/60
CPC分类号： G06F17/2785 , G06F17/2775 , G06Q10/10 , G06Q50/184
摘要： A method of analyzing a claim in a patent or patent application is disclosed, comprising retrieving a patent claim which has been rendered into a format parsable by a computer program into a computer memory; parsing the claim into a set of discrete elements; categorizing each element in the set of elements according to a predetermined rule; and storing a set of categorized elements in a data store. A parsing program executable in a computer may be used to parse the patent claim and, optionally, to identify one or more keyword sets in the parsed claim. A rating program may also be used to assign a rating weight to each categorized element. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：公开了一种分析专利或专利申请中的权利要求的方法，包括将已经呈现为可由计算机程序解析的格式的专利权利要求检索到计算机存储器中; 将声明解析成一组离散元素; 根据预定规则对元素集合中的每个元素进行分类; 并将一组分类元素存储在数据存储中。可以使用计算机中可执行的解析程序来解析专利权利要求，并且可选地，用于识别解析的权利要求中的一个或多个关键字集合。评级程序也可用于为每个分类元素分配评级权重。要强调的是，该摘要被提供以符合要求摘要的规则，这将允许搜索者或其他读者快速确定技术公开的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

10. 发明授权

US06746900B1 Method for forming a semiconductor device having high-K gate dielectric material 失效
标题翻译：用于形成具有高K栅介电材料的半导体器件的方法
公开(公告)号：US06746900B1
公开(公告)日：2004-06-08
申请号：US10369992
申请日：2003-02-19
申请人： Ai-Sen Liu , Baw-Ching Perng , Ming-Ta Lei , Wen-Kai Wan , Cheng-Chung Lin , Kuei-Wu Huang , Yih-Shung Lin , Chia-Hui Lin
发明人： Ai-Sen Liu , Baw-Ching Perng , Ming-Ta Lei , Wen-Kai Wan , Cheng-Chung Lin , Kuei-Wu Huang , Yih-Shung Lin , Chia-Hui Lin
IPC分类号： H01L21335
CPC分类号： H01L21/28185 , H01L21/28194 , H01L29/517 , H01L29/66583
摘要： In a method of forming an integrated circuit, a sacrificial layer is formed over a substrate. The sacrificial layer has a gate trench formed therein and a first layer of a first material formed over the substrate in the gate trench. A second layer of a second material is formed over the first layer in the gate trench. The first and second layers are processed to form a layer of a high-K dielectric material.
摘要翻译：在形成集成电路的方法中，在衬底上形成牺牲层。牺牲层具有形成在其中的栅极沟槽和形成在栅极沟槽中的衬底上的第一材料的第一层。第二材料的第二层形成在栅极沟槽中的第一层上。处理第一层和第二层以形成高K电介质材料层。

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