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1. 发明授权

US06943077B2 Selective spacer layer deposition method for forming spacers with different widths 失效
标题翻译：用于形成具有不同宽度的间隔物的选择性间隔层沉积方法
公开(公告)号：US06943077B2
公开(公告)日：2005-09-13
申请号：US10408689
申请日：2003-04-07
申请人： Ai-Sen Liu , Baw-Ching Perng , Ming-Ta Lei , Yih-Shung Lin , Cheng-Chung Lin , Chia-Hui Lin
发明人： Ai-Sen Liu , Baw-Ching Perng , Ming-Ta Lei , Yih-Shung Lin , Cheng-Chung Lin , Chia-Hui Lin
IPC分类号： H01L21/02 , H01L21/302 , H01L21/3105 , H01L21/314 , H01L21/336 , H01L21/8234 , H01L21/8238
CPC分类号： H01L21/823468 , H01L21/3105 , H01L21/3144 , H01L21/823456 , H01L29/6656
摘要： A method of forming spacers with different widths on a semiconductor substrate, includes the steps of disposing a first spacer layer over the substrate, defining the first spacer layer into a plurality of spacers of a first width, and disposing a second spacer layer selectively over the first spacer layer of a number of the spacers preselected for the second spacer layer, the predetermined number of the spacers with the second spacer layer each having a second width which is different from the first width.
摘要翻译：一种在半导体衬底上形成具有不同宽度的间隔物的方法，包括以下步骤：在衬底上设置第一间隔层，将第一间隔层限定为多个第一宽度的间隔物，并且在第为第二间隔层预选的多个间隔物的第一间隔层，具有第二间隔层的预定数量的间隔物各自具有与第一宽度不同的第二宽度。

2. 发明授权

US07271103B2 Surface treated low-k dielectric as diffusion barrier for copper metallization 有权
标题翻译：表面处理的低k电介质作为铜金属化的扩散阻挡层
公开(公告)号：US07271103B2
公开(公告)日：2007-09-18
申请号：US10687713
申请日：2003-10-17
申请人： Kuei-Wu Huang , Ai-Sen Liu , Baw-Ching Perng , Ming-Ta Lei , Wen-Kai Wan , Cheng-Chung Lin , Yih-Shung Lin , Chia-Hui Lin
发明人： Kuei-Wu Huang , Ai-Sen Liu , Baw-Ching Perng , Ming-Ta Lei , Wen-Kai Wan , Cheng-Chung Lin , Yih-Shung Lin , Chia-Hui Lin
IPC分类号： H01L21/302
CPC分类号： H01L21/02137 , H01L21/02332 , H01L21/0234 , H01L21/02351 , H01L21/02362 , H01L21/31058 , H01L21/3122 , H01L21/3124 , H01L21/3148 , H01L21/3185 , H01L21/76825 , H01L21/76826 , H01L21/76829
摘要： A Cu damascene structure is formed where Cu diffusion barrier is formed by treating the top surface of the surrounding low-k interlayer dielectric with nitrogen or carbon containing medium to form a silicon nitride or silicon carbide diffusion barrier rather than capping the top surface of the Cu with metal diffusion barrier as is conventionally done.
摘要翻译：形成Cu镶嵌结构，其中通过用含氮或碳的介质处理周围的低k层间电介质的顶表面形成Cu扩散阻挡层，以形成氮化硅或碳化硅扩散阻挡层，而不是封盖Cu的顶表面具有如以往所做的金属扩散阻挡层。

3. 发明申请

US20050085083A1 Surface treated low-k dielectric as diffusion barrier for copper metallization 有权
标题翻译：表面处理的低k电介质作为铜金属化的扩散阻挡层
公开(公告)号：US20050085083A1
公开(公告)日：2005-04-21
申请号：US10687713
申请日：2003-10-17
申请人： Kuei-Wu Huang , Ai-Sen Liu , Baw-Ching Perng , Ming-Ta Lei , Wen-Kai Wan , Cheng-Chung Lin , Yih-Shung Lin , Chia-Hui Lin
发明人： Kuei-Wu Huang , Ai-Sen Liu , Baw-Ching Perng , Ming-Ta Lei , Wen-Kai Wan , Cheng-Chung Lin , Yih-Shung Lin , Chia-Hui Lin
IPC分类号： H01L21/3105 , H01L21/312 , H01L21/314 , H01L21/318 , H01L21/768 , H01L21/302 , H01L21/461
CPC分类号： H01L21/02137 , H01L21/02332 , H01L21/0234 , H01L21/02351 , H01L21/02362 , H01L21/31058 , H01L21/3122 , H01L21/3124 , H01L21/3148 , H01L21/3185 , H01L21/76825 , H01L21/76826 , H01L21/76829
摘要： A Cu damascene structure is formed where Cu diffusion barrier is formed by treating the top surface of the surrounding low-k interlayer dielectric with nitrogen or carbon containing medium to form a silicon nitride or silicon carbide diffusion barrier rather than capping the top surface of the Cu with metal diffusion barrier as is conventionally done.
摘要翻译：形成Cu镶嵌结构，其中通过用含氮或碳的介质处理周围的低k层间电介质的顶表面形成Cu扩散阻挡层，以形成氮化硅或碳化硅扩散阻挡层，而不是封盖Cu的顶表面具有如以往所做的金属扩散阻挡层。

4. 发明授权

US07176137B2 Method for multiple spacer width control 有权
标题翻译：多间隔宽度控制方法
公开(公告)号：US07176137B2
公开(公告)日：2007-02-13
申请号：US10435009
申请日：2003-05-09
申请人： Baw-Ching Perng , Yih-Shung Lin , Ming-Ta Lei , Ai-Sen Liu , Chia-Hui Lin , Cheng-Chung Lin
发明人： Baw-Ching Perng , Yih-Shung Lin , Ming-Ta Lei , Ai-Sen Liu , Chia-Hui Lin , Cheng-Chung Lin
IPC分类号： H01L21/302
CPC分类号： H01L29/6656 , H01L21/823468
摘要： A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a first plurality of gate structures; blanket depositing a first dielectric layer over the first plurality of gate structures; blanket depositing a second dielectric layer over the first dielectric layer; etching back through a thickness of the first and second dielectric layers; blanket depositing a first photoresist layer to cover the first plurality and patterning to selectively expose at least a second plurality of gate structures; isotropically etching the at least a second plurality of gate structures for a predetermined time period to selectively etch away a predetermined portion of the first dielectric layer; and, selectively etching away the second dielectric layer to leave gate structures comprising a plurality of associated sidewall spacer widths.
摘要翻译：形成多个栅极侧壁间隔物的方法，每个栅极侧壁间隔件包括不同的相关栅极侧壁间隔物宽度，包括提供第一多个栅极结构; 在第一多个栅极结构上覆盖沉积第一介电层; 在第一介电层上铺设第二介电层; 通过第一和第二介电层的厚度回蚀; 覆盖沉积第一光致抗蚀剂层以覆盖第一多个并且图案化以选择性地暴露至少第二多个栅极结构; 对所述至少第二多个栅极结构进行各向同性蚀刻预定的时间段以选择性地蚀刻掉所述第一介电层的预定部分; 并且选择性地蚀刻掉第二介电层以留下包括多个相关联的侧壁间隔物宽度的栅极结构。

5. 发明授权

US06746900B1 Method for forming a semiconductor device having high-K gate dielectric material 失效
标题翻译：用于形成具有高K栅介电材料的半导体器件的方法
公开(公告)号：US06746900B1
公开(公告)日：2004-06-08
申请号：US10369992
申请日：2003-02-19
申请人： Ai-Sen Liu , Baw-Ching Perng , Ming-Ta Lei , Wen-Kai Wan , Cheng-Chung Lin , Kuei-Wu Huang , Yih-Shung Lin , Chia-Hui Lin
发明人： Ai-Sen Liu , Baw-Ching Perng , Ming-Ta Lei , Wen-Kai Wan , Cheng-Chung Lin , Kuei-Wu Huang , Yih-Shung Lin , Chia-Hui Lin
IPC分类号： H01L21335
CPC分类号： H01L21/28185 , H01L21/28194 , H01L29/517 , H01L29/66583
摘要： In a method of forming an integrated circuit, a sacrificial layer is formed over a substrate. The sacrificial layer has a gate trench formed therein and a first layer of a first material formed over the substrate in the gate trench. A second layer of a second material is formed over the first layer in the gate trench. The first and second layers are processed to form a layer of a high-K dielectric material.
摘要翻译：在形成集成电路的方法中，在衬底上形成牺牲层。牺牲层具有形成在其中的栅极沟槽和形成在栅极沟槽中的衬底上的第一材料的第一层。第二材料的第二层形成在栅极沟槽中的第一层上。处理第一层和第二层以形成高K电介质材料层。

6. 发明申请

US20060113616A1 Selective spacer layer deposition method for forming spacers with different widths 审中-公开
标题翻译：用于形成具有不同宽度的间隔物的选择性间隔层沉积方法
公开(公告)号：US20060113616A1
公开(公告)日：2006-06-01
申请号：US11206613
申请日：2005-08-18
申请人： Ai-Sen Liu , Baw-Ching Perng , Ming-Ta Lei , Yih-Shung Lin , Cheng-Chung Lin , Chia-Hui Lin
发明人： Ai-Sen Liu , Baw-Ching Perng , Ming-Ta Lei , Yih-Shung Lin , Cheng-Chung Lin , Chia-Hui Lin
IPC分类号： H01L29/94
CPC分类号： H01L21/823468 , H01L21/3105 , H01L21/3144 , H01L21/823456 , H01L29/6656
摘要： A method of forming spacers with different widths on a semiconductor substrate, includes the steps of disposing a first spacer layer over the substrate, defining the first spacer layer into a plurality of spacers of a first width, and disposing a second spacer layer selectively over the first spacer layer of a number of the spacers preselected for the second spacer layer, the predetermined number of the spacers with the second spacer layer each having a second width which is different from the first width.
摘要翻译：一种在半导体衬底上形成具有不同宽度的间隔物的方法，包括以下步骤：在衬底上设置第一间隔层，将第一间隔层限定为多个第一宽度的间隔物，并且在第为第二间隔层预选的多个间隔物的第一间隔层，具有第二间隔层的预定数量的间隔物各自具有与第一宽度不同的第二宽度。

7. 发明授权

US07011929B2 Method for forming multiple spacer widths 失效
标题翻译：形成多个间隔物宽度的方法
公开(公告)号：US07011929B2
公开(公告)日：2006-03-14
申请号：US10340245
申请日：2003-01-09
申请人： Ming-Ta Lei , Yih-Shung Lin , Ai-Sen Liu , Cheng-Chung Lin , Baw-Ching Perng , Chia-Hui Lin
发明人： Ming-Ta Lei , Yih-Shung Lin , Ai-Sen Liu , Cheng-Chung Lin , Baw-Ching Perng , Chia-Hui Lin
IPC分类号： H01L21/302
CPC分类号： H01L21/823468
摘要： A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a plurality of gate structures formed overlying a substrate and a plurality of dielectric layers formed substantially conformally overlying the gate structures; exposing a first selected portion of the plurality followed by anisotropically etching through a thickness portion comprising at least the uppermost dielectric layer to form a first sidewall spacer width; exposing a first subsequent selected portion of the plurality followed by etching through at least a thickness portion of the uppermost dielectric layer; and, exposing a second subsequent selected portion of the plurality followed by anisotropically etching through at least a thickness portion of the uppermost dielectric layer to form a subsequent sidewall spacer width.
摘要翻译：一种形成多个栅极侧壁间隔物的方法，每个栅极侧壁间隔件包括不同的相关栅极侧壁间隔物宽度，包括提供形成在衬底上的多个栅极结构和基本上共形地覆盖栅极结构的多个电介质层; 暴露多个的第一选定部分，然后通过各向异性蚀刻穿过包括至少最上面的介电层的厚度部分以形成第一侧壁间隔物宽度; 暴露多个的第一后续选定部分，然后蚀刻通过至少最上层介电层的厚度部分; 并且暴露多个随后的第二部分，然后通过各向异性蚀刻穿过至少最上面的介电层的厚度部分以形成随后的侧壁间隔物宽度。

8. 发明授权

US08053894B2 Surface treatment of metal interconnect lines 有权
标题翻译：金属互连线的表面处理
公开(公告)号：US08053894B2
公开(公告)日：2011-11-08
申请号：US11213238
申请日：2005-08-26
申请人： Wen-Kai Wan , Yih-Hsiung Lin , Ming-Ta Lei , Baw-Ching Perng , Cheng-Chung Lin , Chia-Hui Lin , Ai-Sen Liu
发明人： Wen-Kai Wan , Yih-Hsiung Lin , Ming-Ta Lei , Baw-Ching Perng , Cheng-Chung Lin , Chia-Hui Lin , Ai-Sen Liu
IPC分类号： H01L23/48
CPC分类号： H01L21/76843 , H01L21/288 , H01L21/76849 , H01L21/76858 , H01L21/76886
摘要： Apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.
摘要翻译：用于形成半导体结构的装置，其包括在衬底的顶部上的第一层，其中第一层限定诸如铜互连线和非导电区域（例如介电材料）的导电区域。导电区域被不同于第一层的材料的第二层（例如镍）覆盖，然后对该结构进行热处理，使得互连线和第二金属（例如铜互连线和镍第二层）相互作用形成合金层。合金层具有优异的粘附于铜互连线和随后沉积的电介质材料的品质。

9. 发明申请

US20060001160A1 Surface treatment of metal interconnect lines 有权
标题翻译：金属互连线的表面处理
公开(公告)号：US20060001160A1
公开(公告)日：2006-01-05
申请号：US11213238
申请日：2005-08-26
申请人： Wen-Kai Wan , Yih-Hsiung Lin , Ming-Ta Lei , Baw-Ching Perng , Cheng-Chung Lin , Chia-Hui Lin , Ai-Sen Liu
发明人： Wen-Kai Wan , Yih-Hsiung Lin , Ming-Ta Lei , Baw-Ching Perng , Cheng-Chung Lin , Chia-Hui Lin , Ai-Sen Liu
IPC分类号： H01L29/40 , H01L23/52 , H01L23/48 , B32B15/00 , B32B17/06
CPC分类号： H01L21/76843 , H01L21/288 , H01L21/76849 , H01L21/76858 , H01L21/76886
摘要： Apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.
摘要翻译：用于形成半导体结构的装置，其包括在衬底的顶部上的第一层，其中第一层限定诸如铜互连线和非导电区域（例如介电材料）的导电区域。导电区域被不同于第一层的材料的第二层（例如镍）覆盖，然后对该结构进行热处理，使得互连线和第二金属（例如铜互连线和镍第二层）相互作用形成合金层。合金层具有优异的粘附于铜互连线和随后沉积的电介质材料的品质。

10. 发明授权

US09252019B2 Semiconductor device and method for forming the same 有权
标题翻译：半导体装置及其形成方法
公开(公告)号：US09252019B2
公开(公告)日：2016-02-02
申请号：US13222502
申请日：2011-08-31
申请人： Wen-Chi Tsai , Chia-Han Lai , Yung-Chung Chen , Mei-Yun Wang , Chii-Ming Wu , Fang-Cheng Chen , Huang-Ming Chen , Ming-Ta Lei
发明人： Wen-Chi Tsai , Chia-Han Lai , Yung-Chung Chen , Mei-Yun Wang , Chii-Ming Wu , Fang-Cheng Chen , Huang-Ming Chen , Ming-Ta Lei
IPC分类号： H01L21/768 , H01L21/285 , H01L29/417 , H01L21/02 , H01L29/66
CPC分类号： H01L29/78 , H01L21/02063 , H01L21/28512 , H01L21/28518 , H01L21/76802 , H01L21/76805 , H01L21/76814 , H01L21/76825 , H01L21/76831 , H01L21/76844 , H01L21/76855 , H01L23/485 , H01L23/535 , H01L29/41775 , H01L29/45 , H01L29/6659 , H01L2924/0002 , H01L2924/00
摘要： A system and method for forming and using a liner is provided. An embodiment comprises forming an opening in an inter-layer dielectric over a substrate and forming the liner along the sidewalls of the opening. A portion of the liner is removed from a bottom of the opening, and a cleaning process may be performed through the liner. By using the liner, damage to the sidewalls of the opening from the cleaning process may be reduced or eliminated. Additionally, the liner may be used to help implantation of ions within the substrate.
摘要翻译：提供了一种用于形成和使用衬套的系统和方法。一个实施例包括在衬底之上的层间电介质中形成开口，并沿着开口的侧壁形成衬垫。衬套的一部分从开口的底部移除，并且可以通过衬套执行清洁过程。通过使用衬垫，可以减少或消除从清洁过程对开口侧壁的损坏。另外，衬垫可用于帮助衬底内的离子注入。

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