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1. 发明授权

US06855597B2 DRAM cell 失效
标题翻译： DRAM单元
公开(公告)号：US06855597B2
公开(公告)日：2005-02-15
申请号：US10413372
申请日：2003-04-15
申请人： Chul-Ho Shin , Kyeong-Koo Chi
发明人： Chul-Ho Shin , Kyeong-Koo Chi
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10855 , H01L27/10885 , H01L28/91
摘要： A method of manufacturing a DRAM cell includes forming an isolation layer on a given region of a substrate to define an active region having a plurality of line shaped sub-regions; forming at least a pair of cell transistors in each line shaped sub-region, each cell transistor of a pair having a common drain region and respective source regions; forming a bit line pad on each common drain region and a storage node pad on each source region; forming a bit line pad protecting layer pattern having portions parallel to the word line, that covers the bit line pad; and forming storage nodes on storage node pads. The storage nodes of the DRAM cell contact with the storage node pads and are insulated electrically from the bit line pad by the bit pad protecting layer pattern.
摘要翻译：制造DRAM单元的方法包括在衬底的给定区域上形成隔离层以限定具有多个线状子区域的有源区域; 在每个线状子区域中形成至少一对单元晶体管，每对单元晶体管具有公共漏极区域和相应的源极区域; 在每个公共漏极区域上形成位线焊盘和在每个源极区域上形成存储节点焊盘; 形成具有与字线平行的部分的位线保护层图案，覆盖位线焊盘; 并在存储节点垫上形成存储节点。 DRAM单元的存储节点与存储节点焊盘接触，并通过位焊盘保护层图案与位线焊盘电绝缘。

2. 发明授权

US06570205B2 DRAM cell 失效
标题翻译： DRAM单元
公开(公告)号：US06570205B2
公开(公告)日：2003-05-27
申请号：US10038911
申请日：2002-01-08
申请人： Chul-Ho Shin , Kyeong-Koo Chi
发明人： Chul-Ho Shin , Kyeong-Koo Chi
IPC分类号： H01L27108
CPC分类号： H01L27/10855 , H01L27/10885 , H01L28/91
摘要： A method of manufacturing a DRAM cell includes forming an isolation layer on a given region of a substrate to define an active region having a plurality of line shaped sub-regions; forming at least a pair of cell transistors in each line shaped sub-region, each cell transistor of a pair having a common drain region and respective source regions; forming a bit line pad on each common drain region and a storage node pad on each source region; forming a bit line pad protecting layer pattern having portions parallel to the word line, that covers the bit line pad; and forming storage nodes on storage node pads. The storage nodes of the DRAM cell contact with the storage node pads and are insulated electrically from the bit line pad by the bit line pad protecting layer pattern.
摘要翻译：制造DRAM单元的方法包括在衬底的给定区域上形成隔离层以限定具有多个线状子区域的有源区域; 在每个线状子区域中形成至少一对单元晶体管，每对单元晶体管具有公共漏极区域和相应的源极区域; 在每个公共漏极区域上形成位线焊盘和在每个源极区域上形成存储节点焊盘; 形成具有与字线平行的部分的位线保护层图案，覆盖位线焊盘; 并在存储节点垫上形成存储节点。 DRAM单元的存储节点与存储节点焊盘接触，并通过位线焊盘保护层图案与位线焊盘电绝缘。

3. 发明授权

US07682986B2 Ultra-high aspect ratio dielectric etch 有权
标题翻译：超高纵横比电介质蚀刻
公开(公告)号：US07682986B2
公开(公告)日：2010-03-23
申请号：US11671340
申请日：2007-02-05
申请人： Kyeong-Koo Chi , Erik A. Edelberg
发明人： Kyeong-Koo Chi , Erik A. Edelberg
IPC分类号： H01L21/302
CPC分类号： H01L21/31144 , H01L21/31116 , H01L21/31138 , H01L21/76816
摘要： A method for etching an ultra high aspect ratio feature in a dielectric layer through a carbon based mask is provided. The dielectric layer is selectively etched with respect to the carbon based mask, wherein the selective etching provides a net deposition of a fluorocarbon based polymer on the carbon based mask. The selective etch is stopped. The fluorocarbon polymer is selectively removed with respect to the carbon based mask, so that the carbon based mask remains, using a trimming. The selectively removing the fluorocarbon polymer is stopped. The dielectric layer is again selectively etched with respect to the carbon based mask, wherein the second selectively etching provides a net deposition of a fluorocarbon based polymer on the carbon based mask.
摘要翻译：提供了一种通过碳基掩模蚀刻介电层中的超高宽比特征的方法。相对于碳基掩模选择性地蚀刻电介质层，其中选择性蚀刻提供基于碳基掩模的基于碳氟化合物的聚合物的净沉积。选择性蚀刻停止。相对于碳基掩模选择性地除去氟碳聚合物，使得使用修整保留碳基掩模。停止选择性除去氟碳聚合物。相对于碳基掩模再次选择性地蚀刻介电层，其中第二选择性蚀刻提供基于碳基掩模的碳氟基聚合物的净沉积。

4. 发明授权

US07491344B2 Method for etching an object using a plasma and an object etched by a plasma 有权
标题翻译：使用等离子体蚀刻物体的方法和由等离子体蚀刻的物体
公开(公告)号：US07491344B2
公开(公告)日：2009-02-17
申请号：US10703947
申请日：2003-11-04
申请人： Heung-Sik Park , Chang-Jin Kang , Tae-Hyuk Ahn , Kyeong-Koo Chi , Sang-Hun Seo
发明人： Heung-Sik Park , Chang-Jin Kang , Tae-Hyuk Ahn , Kyeong-Koo Chi , Sang-Hun Seo
IPC分类号： C23F1/00
CPC分类号： H01J37/32055 , H01L21/3065 , H01L21/78 , H05H1/44
摘要： Disclosed herein is a method for etching a face of an object and more particularly a method for etching a rear face of a silicon substrate. The object having a silicon face is positioned so as to be spaced apart from a plasma-generating member by a predetermined interval distance. The plasma-generating member generates arc plasmas to form a plasma region. A reaction gas is allowed to pass through the plasma region to generate radicals having high energies and high densities. The radicals react with the object to etch the face of the object. The face of the object can be rapidly and uniformly etched.
摘要翻译：本文公开了一种用于蚀刻物体的表面的方法，更具体地，蚀刻硅衬底的背面的方法。具有硅面的物体被定位成与等离子体产生构件间隔预定间隔距离。等离子体产生部件产生电弧等离子体以形成等离子体区域。允许反应气体通过等离子体区域以产生具有高能量和高密度的自由基。自由基与物体反应以蚀刻物体的表面。物体的表面可以快速均匀地蚀刻。

5. 发明申请

US20080188082A1 PULSED ULTRA-HIGH ASPECT RATIO DIELECTRIC ETCH 有权
标题翻译：脉冲超高比例电介质蚀刻
公开(公告)号：US20080188082A1
公开(公告)日：2008-08-07
申请号：US11671342
申请日：2007-02-05
申请人： Kyeong-Koo Chi , Erik A. Edelberg
发明人： Kyeong-Koo Chi , Erik A. Edelberg
IPC分类号： H01L21/311 , H01L21/461
CPC分类号： H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/76816
摘要： A method for selectively etching an ultra high aspect ratio feature dielectric layer through a carbon based mask in an etch chamber is provided. A flow of an etch gas is provided, comprising a fluorocarbon containing molecule and an oxygen containing molecule to the etch chamber. A pulsed bias RF signal is provided. An energizing RF signal is provided to transform the etch gas to a plasma.
摘要翻译：提供了一种通过蚀刻室中的基于碳的掩模来选择性地蚀刻超高宽比特征介电层的方法。提供蚀刻气体的流动，其包括含氟碳分子和含氧分子到蚀刻室。提供脉冲偏置RF信号。提供激励RF信号以将蚀刻气体转换成等离子体。

6. 发明申请

US20050158948A1 Semiconductor device having self-aligned contact plug and method for fabricating the same 有权
公开(公告)号：US20050158948A1
公开(公告)日：2005-07-21
申请号：US11058670
申请日：2005-02-15
申请人： Myeong-Cheol Kim , Chang-Jin Kang , Kyeong-Koo Chi , Seung-Young Son
发明人： Myeong-Cheol Kim , Chang-Jin Kang , Kyeong-Koo Chi , Seung-Young Son
IPC分类号： H01L21/28 , H01L21/60 , H01L21/8242 , H01L23/522 , H01L27/108
CPC分类号： H01L21/76831 , H01L21/76897 , H01L23/5226 , H01L27/10814 , H01L27/10855 , H01L2924/0002 , H01L2924/00
摘要： Provided are a semiconductor device having a self-aligned contact plug and a method of fabricating the semiconductor device. The semiconductor device includes conductive patterns, a first interlayer insulating layer, a first spacer, a second interlayer insulating layer, and a contact plug. In each conductive pattern, a conductive layer and a capping layer are sequentially deposited on an insulating layer over a semiconductor substrate. The first interlayer insulating layer fills spaces between the conductive patterns and has a height such that when the first interlayer insulating layer is placed on the insulating layer, the first interlayer insulating layer is lower than a top surface of the capping layer but higher than a top surface of the conductive layer. The first spacer surrounds the outer surface of the capping layer on the first interlayer insulating layer. The second interlayer insulating layer covers the first interlayer insulating layer, the capping layer, and the first spacer and has a planarized top surface. The contact plug passes through the second interlayer insulating layer, the first interlayer insulating layer, and the insulating layer between the conductive patterns, is electrically connected to the semiconductor substrate, has an outerwall surrounded by a second spacer, and is self-aligned with the capping layer.

7. 发明申请

US20050130371A1 Method of fabricating semiconductor device having capacitor 有权
公开(公告)号：US20050130371A1
公开(公告)日：2005-06-16
申请号：US11048995
申请日：2005-02-02
申请人： Sung-Il Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
发明人： Sung-Il Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
IPC分类号： H01L21/8242 , H01L21/02 , H01L21/314 , H01L21/316 , H01L21/3213
CPC分类号： H01L28/91 , H01L21/3142 , H01L21/31616 , H01L21/31645 , H01L21/32136 , H01L27/10855
摘要： Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.

8. 发明授权

US06867096B2 Method of fabricating semiconductor device having capacitor 有权
标题翻译：制造具有电容器的半导体器件的方法
公开(公告)号：US06867096B2
公开(公告)日：2005-03-15
申请号：US10855165
申请日：2004-05-27
申请人： Sung-IL Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
发明人： Sung-IL Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
IPC分类号： H01L21/8242 , H01L21/02 , H01L21/314 , H01L21/316 , H01L21/3213
CPC分类号： H01L28/91 , H01L21/3142 , H01L21/31616 , H01L21/31645 , H01L21/32136 , H01L27/10855
摘要： Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.
摘要翻译：提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中，接触插塞的上表面，在着陆焊盘和第二绝缘层上形成蚀刻停止层，在蚀刻停止层上形成第三绝缘层; 通过第三绝缘层和蚀刻停止层形成第三孔以暴露着陆焊盘，选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的焊盘上形成下电极，然后通过形成电介质层和上层电极在下电极上。

9. 发明授权

US08941165B2 Methods of fabricating integrated circuit capacitors having u-shaped lower capacitor electrodes 有权
标题翻译：制造具有u形下电容器电极的集成电路电容器的方法
公开(公告)号：US08941165B2
公开(公告)日：2015-01-27
申请号：US12779300
申请日：2010-05-13
申请人： Sung-Il Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
发明人： Sung-Il Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
IPC分类号： H01L27/108 , H01L49/02 , H01L21/3213 , H01L21/314 , H01L21/316
CPC分类号： H01L28/91 , H01L21/3142 , H01L21/31616 , H01L21/31645 , H01L21/32136 , H01L27/10855
摘要： Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.
摘要翻译：提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中，接触插塞的上表面，在着陆焊盘和第二绝缘层上形成蚀刻停止层，在蚀刻停止层上形成第三绝缘层; 通过第三绝缘层和蚀刻停止层形成第三孔以暴露着陆焊盘，选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的焊盘上形成下电极，然后通过形成电介质层和上层电极在下电极上。

10. 发明授权

US08470715B2 CD bias loading control with ARC layer open 有权
标题翻译： CD偏压加载控制与ARC层打开
公开(公告)号：US08470715B2
公开(公告)日：2013-06-25
申请号：US12809021
申请日：2008-12-09
申请人： Kyeong-Koo Chi , Jonathan Kim
发明人： Kyeong-Koo Chi , Jonathan Kim
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/31144 , H01L21/0276
摘要： A method for etching a line pattern in an etch layer disposed below an antireflective coating (ARC) layer below a patterned mask is provided. The method includes opening the ARC layer, in which an ARC opening gas comprising CF3I, a fluorocarbon (including hydrofluorocarbon) containing gas, and an oxygen containing gas are provided, a plasma is formed from the ARC opening gas to open the ARC layer, and providing the ARC opening gas is stopped. Line pattern features are etched into the etch layer through the opened ARC layer.
摘要翻译：提供了一种用于蚀刻设置在图案化掩模下面的抗反射涂层（ARC）层下方的蚀刻层中的线图案的方法。该方法包括：在其中设置包括CF 3I的ARC开口气体，含有气体的碳氟化合物（包括氢氟烃）和含氧气体的ARC层，从ARC开口气体形成等离子体以打开ARC层，并且提供ARC打开气体停止。线图案特征通过打开的ARC层蚀刻到蚀刻层中。

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