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1. 发明授权

US5541131A Peeling free metal silicide films using ion implantation 失效
标题翻译：使用离子注入剥离游离金属硅化物膜
公开(公告)号：US5541131A
公开(公告)日：1996-07-30
申请号：US649549
申请日：1991-02-01
申请人： Chue-San Yoo , Ting-Hwang Lin
发明人： Chue-San Yoo , Ting-Hwang Lin
IPC分类号： H01L21/285 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/28518 , Y10S148/147
摘要： A method is described for fabricating a lightly doped drain MOSFET integrated circuit device which overcomes the polycide peeling problems. A pattern of gate electrode structures is formed upon a semiconductor substrate which each includes a gate oxide, a polysilicon layer and an amorphous refractory metal silicide. The resulting structure may be annealed in oxygen at this time to change the refractory metal silicide from it deposited amorphous phase into its crystalline phase. This causes the formation of a thin layer of silicon dioxide upon the exposed silicon substrate, the exposed polysilicon layer and the exposed metal silicide layer. A pattern of lightly doped regions in the substrate is formed by ion implantation using the polycide gate structures as the mask. A dielectric layer is blanket deposited over the surfaces and spacer structures formed by anisotropic etching. A pattern of heavily doped regions in the substrate is formed by ion implantation using the polycide structures with spacer structures as the mask to produce the lightly doped drain source/drain structures of an MOSFET device. The silicon oxide layer on the top surface of the metal silicate layer was removed by etching. Silicon ions are now implanted into the metal silicide layer to supply an excess of silicon ions at the surface of the metal silicide layer. The integrated circuit device is completed by forming a passivation layer over the structures described and appropriate electrical connecting structures thereover.
摘要翻译：描述了一种制造轻掺杂漏极MOSFET集成电路器件的方法，其克服了多晶硅剥离问题。栅电极结构的图案形成在半导体衬底上，每个半导体衬底包括栅极氧化物，多晶硅层和非晶难熔金属硅化物。此时可以在氧气中对所得结构进行退火，以将难熔金属硅化物从其沉积的非晶相变为其结晶相。这导致在暴露的硅衬底，暴露的多晶硅层和暴露的金属硅化物层上形成薄的二氧化硅层。通过使用多晶硅栅极结构作为掩模的离子注入形成衬底中的轻掺杂区域的图案。介电层被覆盖在各个表面上，并通过各向异性蚀刻形成间隔结构。通过使用具有间隔结构的聚硅氧烷结构作为掩模的离子注入形成衬底中的重掺杂区域的图案，以产生MOSFET器件的轻掺杂漏极/漏极结构。通过蚀刻去除金属硅酸盐层的顶表面上的氧化硅层。硅离子现在被注入到金属硅化物层中，以在金属硅化物层的表面处提供过量的硅离子。通过在所描述的结构上形成钝化层并在其上形成适当的电连接结构来完成集成电路器件。

2. 发明授权

US5203957A Contact sidewall tapering with argon sputtering 失效
标题翻译：氩气溅射接触侧壁逐渐变细
公开(公告)号：US5203957A
公开(公告)日：1993-04-20
申请号：US713508
申请日：1991-06-12
申请人： Chue-San Yoo , Ting-Hwang Lin , Sui-Hei Kuo
发明人： Chue-San Yoo , Ting-Hwang Lin , Sui-Hei Kuo
IPC分类号： H01L21/311 , H01L21/768
CPC分类号： H01L21/76826 , H01L21/31116 , H01L21/76804
摘要： The method for making a contact opening for an integrated circuit having a feature size of about one micrometer or less is accomplished by first providing an integrated circuit structure having device elements within a semiconductor substate and multilayer insulating layers thereover. A resist masking layer is formed over the multilayer insulating layer having openings therein in the areas where the contact openings are desired. Isotropic etching is done through a desired thickness portion of multilayer insulating layer. Anisotropic etching is now done through the remaining thickness of multilayer insulating layer to the semiconductor substrate to form the desired contact opening. The resist layer is removed. The structure is subjected to an Argon sputter etching ambient to smooth the sharp corners at the upper surface of multilayer layer and the point where the isotropic etching ended and the anisotropic etching began. It is preferred that soft reactive ion etching be done for a period of less than about 30 seconds after said Argon sputter etching to reduce the increased contact resistance caused by this Argon sputter etching.
摘要翻译：通过首先提供具有在半导体子状态内的器件元件和其上的多层绝缘层的集成电路结构，来实现具有约1微米或更小特征尺寸的集成电路的接触开口的方法。在需要接触开口的区域中，在其上具有开口的多层绝缘层上形成抗蚀剂掩模层。通过多层绝缘层的所需厚度部分进行各向同性蚀刻。现在通过多层绝缘层的剩余厚度到半导体衬底来形成各向异性蚀刻以形成所需的接触开口。去除抗蚀剂层。该结构经受氩溅射蚀刻环境以平滑多层层的上表面处的尖角以及各向同性蚀刻结束的点和各向异性蚀刻开始。优选的是，在所述氩溅射蚀刻之后，软反应离子蚀刻进行时间小于约30秒，以减少由该氩溅射蚀刻引起的增加的接触电阻。

3. 发明授权

US5393685A Peeling free metal silicide films using rapid thermal anneal 失效
标题翻译：使用快速热退火剥离游离金属硅化物膜
公开(公告)号：US5393685A
公开(公告)日：1995-02-28
申请号：US926299
申请日：1992-08-10
申请人： Chue-San Yoo , Ting-Hwang Lin
发明人： Chue-San Yoo , Ting-Hwang Lin
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L21/265
CPC分类号： H01L29/6659 , H01L21/28061 , H01L21/28518
摘要： A method is described for fabricating a lightly doped drain MOSFET integrated circuit device which provides a peeling-free metal silicide gate electrode devices. The process uses annealing of the gate oxide, the polysilicon layer and the metal silicide layer using a rapid thermal annealing process at a temperature more than about 1000.degree. C. and for a time of between about 30 to 60 seconds. A pattern of lightly doped regions is formed in the substrate by ion implantation using the structures as the mask. A low temperature silicon dioxide layer is blanket deposited over the surfaces of the structure. The blanket layer is etched to form a dielectric spacer structure upon the sidewalls of each of the gate electrode structures and over the adjacent portions of the substrate, and to remove the silicon oxide layer from the top surfaces of metal silicide layer. Driving in the pattern of lightly doped regions is accomplished by rapid thermal annealing at a temperature of more than about 1000.degree. C. and for a time of between about 30 to 60 seconds with the metal silicide layer having no covering thereover. Heavily doped regions are now formed in the substrate to produce the lightly doped drain under the spacer structure of an MOS FET device. A passivation layer is formed over the structures and electrical connecting structures thereover.
摘要翻译：描述了一种制造提供无剥离金属硅化物栅电极器件的轻掺杂漏极MOSFET集成电路器件的方法。该方法使用快速热退火工艺在大于约1000℃的温度和大约30至60秒的时间内对栅极氧化物，多晶硅层和金属硅化物层进行退火。通过使用该结构作为掩模的离子注入在衬底中形成轻掺杂区域的图案。低温二氧化硅层被覆盖在该结构的表面上。蚀刻覆盖层以在每个栅电极结构的侧壁上和衬底的相邻部分之上形成介电间隔物结构，并从金属硅化物层的顶表面去除氧化硅层。通过在大于约1000℃的温度下快速热退火并且在其间没有覆盖的金属硅化物层的时间为约30至60秒之间来实现轻掺杂区域的驱动。现在在衬底中形成重掺杂区域，以在MOS FET器件的间隔结构之下产生轻掺杂漏极。在其上的结构和电连接结构上形成钝化层。

4. 发明授权

US6033969A Method of forming a shallow trench isolation that has rounded and protected corners 失效
标题翻译：形成具有圆形和保护角的浅沟槽隔离的方法
公开(公告)号：US6033969A
公开(公告)日：2000-03-07
申请号：US721758
申请日：1996-09-30
申请人： Chue-San Yoo , R. Y. Lee , J. H. Tsai
发明人： Chue-San Yoo , R. Y. Lee , J. H. Tsai
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76202 , H01L21/76224 , H01L21/76235
摘要： A method is provided for forming a shallow trench isolation that has rounded and protected corners by first forming a bird's beak field oxide layer prior to the trench-forming step such that a rounded and protected top corner and a rounded bottom corner of the trench can be formed. The rounded top and bottom corners of the shallow trench opening have a radius of at least 100 .ANG. and a trench depth of not more than 5000 .ANG.. The top corner of the trench opening is protected by the beak portion of the bird's beak against etching in a subsequent oxide dip process before gate formation.
摘要翻译：提供了一种用于形成具有圆形和保护角的浅沟槽隔离的方法，首先在沟槽形成步骤之前形成鸟喙场氧化物层，使得沟槽的圆形和受保护的顶角和圆角底角可以是形成。浅沟槽开口的圆形顶部和底部角部的半径至少为100安培，沟槽深度不超过5000安培。沟槽开口的顶角由鸟喙的喙部分保护，在栅极形成之前的随后的氧化物浸渍过程中被蚀刻。

5. 发明授权

US6017791A Multi-layer silicon nitride deposition method for forming low oxidation temperature thermally oxidized silicon nitride/silicon oxide (no) layer 失效
标题翻译：用于形成低氧化温度的氧化氮化硅/氧化硅（no）层的多层氮化硅沉积方法
公开(公告)号：US6017791A
公开(公告)日：2000-01-25
申请号：US967655
申请日：1997-11-10
申请人： Chen-Jong Wang , Chue-San Yoo , Kuo-Hsien Cheng
发明人： Chen-Jong Wang , Chue-San Yoo , Kuo-Hsien Cheng
IPC分类号： H01L21/02 , H01L21/314 , H01L21/8242
CPC分类号： H01L27/1085 , H01L28/40 , H01L21/3145 , Y10S438/954
摘要： A method for forming a silicon nitride/silicon oxide (NO) layer within a microelectronics fabrication, and the microelectronics fabrication having the silicon nitride/silicon oxide (NO) layer formed therein. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a first silicon nitride layer through a first deposition method. There is then formed upon the first silicon nitride layer a second silicon nitride layer through a second deposition method. Finally, there is annealed thermally in an oxidizing environment the first silicon nitride layer and the second silicon nitride layer to form therefrom a silicon nitride/silicon oxide (NO) layer. The silicon nitride/silicon oxide (NO) layer may be formed with optimized resistivity properties at a reduced thermal annealing temperature and/or a reduced thermal annealing exposure time in comparison with an otherwise equivalent silicon nitride/silicon oxide (NO) layer formed through thermal annealing a single silicon nitride layer of thickness equivalent to the thickness of the first silicon nitride layer plus the thickness of the second silicon nitride layer. When formed upon a silicon oxide dielectric layer in turn formed upon a first capacitor plate within a capacitor within an integrated circuit, there may be formed employing the silicon nitride/silicon oxide (NO) layer a silicon oxide/silicon nitride/silicon oxide (ONO) capacitive dielectric layer.
摘要翻译：在微电子制造中形成氮化硅/氧化硅（NO）层的方法以及其中形成有氮化硅/氧化硅（NO）层的微电子制造。首先提供了在微电子制造中使用的衬底。然后通过第一沉积方法在衬底上形成第一氮化硅层。然后通过第二沉积方法在第一氮化硅层上形成第二氮化硅层。最后，在氧化环境中，热处理第一氮化硅层和第二氮化硅层，由此形成氮化硅/氧化硅（NO）层。氮化硅/氧化硅（NO）层可以在降低的热退火温度和/或降低的热退火暴露时间的情况下形成具有优化的电阻率特性，与通过热形成的其它等效的氮化硅/氧化硅（NO）层相比较退火厚度等于第一氮化硅层厚度的单个氮化硅层加上第二氮化硅层的厚度。当形成在集成电路内的电容器内的第一电容器板上的氧化硅电介质层上形成时，可以形成采用氮化硅/氧化硅（NO）层的氧化硅/氮化硅/氧化硅（ONO ）电容电介质层。

6. 发明授权

US5470779A Method of manufacture of SRAM with SIPOS resistor 失效
标题翻译：使用SIPOS电阻制造SRAM的方法
公开(公告)号：US5470779A
公开(公告)日：1995-11-28
申请号：US280219
申请日：1994-07-25
申请人： Chue-San Yoo
发明人： Chue-San Yoo
IPC分类号： H01L21/02 , H01L21/8244 , H01L27/11 , H01L21/70 , H01L27/00
CPC分类号： H01L28/20 , H01L27/11 , H01L27/1112 , Y10S257/904
摘要： A method of manufacture of a semiconductor device on a semiconductor substrate including an SRAM cell with a resistor comprises formation of a polysilicon 1 layer on said semiconductor substrate. The polysilicon 1 layer is patterned and etched. An interpolyslicon layer is formed over the polysilicon 1 layer, patterned and etched forming an opening through the interpolysilicon layer exposing a contact area on the surface of the polysilicon 1 layer. A SIPOS layer forms a resistor material over the interpolysilicon layer in contact with the polysilicon 1 layer through the opening. A load resistor mask is formed over a load resistor region to be formed in the SIPOS layer, and ions are implanted in the remainder of the SIPOS layer not covered by the load resistor mask to convert the remainder of the SIPOS layer from a resistor into an interconnect structure integral with a load resistor in the load resistor region.
摘要翻译：在包括具有电阻器的SRAM单元的半导体衬底上制造半导体器件的方法包括在所述半导体衬底上形成多晶硅1层。多晶硅1层被图案化和蚀刻。在多晶硅1层上形成多层硅化物层，经图案化和蚀刻，形成穿过多晶硅层的开口，暴露多晶硅1层表面上的接触面积。 SIPOS层在通过开口与多晶硅1层接触的多晶硅层上形成电阻材料。在要形成在SIPOS层中的负载电阻器区域上形成负载电阻器掩模，并且将离子注入到不被负载电阻器掩模覆盖的SIPOS层的其余部分中，以将SIPOS层的其余部分从电阻器转换成互连结构与负载电阻器区域中的负载电阻器成一体。

7. 发明授权

US5411907A Capping free metal silicide integrated process 失效
标题翻译：无盖金属硅化物集成工艺
公开(公告)号：US5411907A
公开(公告)日：1995-05-02
申请号：US937735
申请日：1992-09-01
申请人： Chue-San Yoo , Jyh-Min Tsaur , Chong-Shi Chen , Pin-Nan Tseng
发明人： Chue-San Yoo , Jyh-Min Tsaur , Chong-Shi Chen , Pin-Nan Tseng
IPC分类号： H01L21/336 , H01L21/265
CPC分类号： H01L29/6659
摘要： A method is described for fabricating a lightly doped drain MOS FET integrated circuit device with a peeling-free metal silicide gate electrode continues by annealing the gate oxide, the polysilicon layer and the metal silicide layer using a furnace process at a temperature more than about 920.degree. C. and for a time of less than about 40 minutes. A pattern of lightly doped regions is formed in the substrate by ion implantation using the structures as the mask. A low temperature silicon dioxide layer is blanket deposited over the surfaces of the structure. The pattern of lightly doped regions is driven in while maintaining the low temperature silicon oxide over the metal silicide layer by annealing at a temperature of more than about 920.degree. C. The blanket layer is etched to form a dielectric spacer structure upon the sidewalls of each of the gate electrode structures and over the adjacent portions of the substrate, and to remove the silicon oxide layer from the top surfaces of metal silicide layer. Heavily doped regions are formed. A passivation layer which includes a silicon oxide layer and a thicker dielectric layer is formed over the structures. The heavily doped regions are annealed to drivein the impurities at a temperature of more than about 920.degree. C. while maintaining said passivation layer over said metal silicide layer.
摘要翻译：描述了一种用于制造具有无剥离金属硅化物栅电极的轻掺杂漏极MOS FET集成电路器件的方法，其通过使用炉法在大于约920的温度下退火栅极氧化物，多晶硅层和金属硅化物层并且时间小于约40分钟。通过使用该结构作为掩模的离子注入在衬底中形成轻掺杂区域的图案。低温二氧化硅层被覆盖在该结构的表面上。驱动轻掺杂区域的图案，同时通过在超过约920℃的温度下退火，在金属硅化物层上保持低温氧化硅的同时，蚀刻覆盖层以在每个侧壁上形成电介质间隔物结构的栅极电极结构和衬底的相邻部分之上，并从金属硅化物层的顶表面去除氧化硅层。形成重掺杂区域。在结构上形成包括氧化硅层和较厚电介质层的钝化层。重掺杂区域被退火以在大于约920℃的温度下驱动杂质，同时将所述钝化层保持在所述金属硅化物层上。

8. 发明授权

US5943569A Method for making improved capacitors on dynamic random access memory having increased capacitance, longer refresh times, and improved yields 失效
标题翻译：用于在动态随机存取存储器中制造改进的电容器的方法，其具有增加的电容，更长的刷新次数和提高的
公开(公告)号：US5943569A
公开(公告)日：1999-08-24
申请号：US880854
申请日：1997-06-23
申请人： Cheng-Yeh Shih , Yuan-Chang Huang , Chue-San Yoo , Wen-Chan Lin
发明人： Cheng-Yeh Shih , Yuan-Chang Huang , Chue-San Yoo , Wen-Chan Lin
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/1085 , H01L27/10852 , H01L28/60
摘要： A method for making improved capacitor bottom electrodes (capacitor nodes) having longer refresh cycle times and increased capacitance for DRAM cells has been achieved. The method involves using a polysilicon high-temperature film (HTF) instead of the conventional doped polysilicon to form the node capacitors. After forming the DRAM pass transistors (FETs) and depositing an insulating layer, node contact openings are etched in the insulator to the drain of the FET. The capacitor bottom electrodes are formed by depositing a polysilicon HTF at a temperature of at least 650.degree. C. using a reactant gas mixture of H.sub.2 /SiH.sub.4 /PH.sub.3, which results in a longer refresh cycle time and increased capacitance. This results in a significantly improved final die yield. After forming an interelectrode dielectric layer on the bottom electrodes, another doped polysilicon layer is deposited to form the top electrodes to complete the DRAM cells.
摘要翻译：已经实现了具有更长的刷新周期时间和DRAM单元的增加的电容的改进的电容器底部电极（电容器节点）的方法。该方法包括使用多晶硅高温膜（HTF）代替常规的掺杂多晶硅以形成节点电容器。在形成DRAM通过晶体管（FET）和沉积绝缘层之后，将节点接触开口在绝缘体中蚀刻到FET的漏极。通过使用H 2 / SiH 4 / PH 3的反应气体混合物在至少650℃的温度下沉积多晶硅HTF来形成电容器底部电极，这导致更长的刷新周期时间和增加的电容。这导致最终模具产量显着提高。在底部电极上形成电极间电介质层之后，沉积另一个掺杂多晶硅层以形成顶部电极以完成DRAM单元。

9. 发明授权

US5670423A Method for using disposable hard mask for gate critical dimension control 失效
标题翻译：使用一次性硬掩模进行浇口关键尺寸控制的方法
公开(公告)号：US5670423A
公开(公告)日：1997-09-23
申请号：US663431
申请日：1996-06-13
申请人： Chue-San Yoo
发明人： Chue-San Yoo
IPC分类号： H01L21/28 , H01L21/3213 , H01L21/762
CPC分类号： H01L21/76202 , H01L21/28123 , H01L21/32139 , Y10S438/95 , Y10S438/952
摘要： A new method of controlling the critical dimension width of polysilicon by using a disposable hard mask is described. A semiconductor substrate is provided wherein the surface of the substrate has an uneven topography. A layer of polysilicon is deposited over the uneven surface of the substrate. The polysilicon layer is covered with a spin-on-glass layer wherein the spin-on-glass material planarizes the surface of the underlying topography. A semiconductor layer is deposited over the surface of the planarization layer to act as a hard mask wherein the semiconductor layer is opaque to actinic light. The semiconductor layer is covered with a uniform thickness layer of photoresist. The photoresist layer is exposed to actinic light wherein the semiconductor layer prevents reflection of the actinic light from its surface. The photoresist layer is developed and patterned to form the desired photoresist mask for the polysilicon layer. The semiconductor layer, the spin-on-glass layer, and the polysilicon layer not covered by the photoresist mask are anisotropically etched away to form polysilicon gate electrodes and interconnection lines. The photoresist mask, the hard mask, and the spin-on-glass layer are removed to complete the formation of polysilicon gate electrodes and interconnection lines having uniform critical dimension in the fabrication of an integrated circuit.
摘要翻译：描述了通过使用一次性硬掩模来控制多晶硅的临界尺寸宽度的新方法。提供半导体衬底，其中衬底的表面具有不平坦的形貌。在衬底的不平坦表面上沉积多晶硅层。多晶硅层被旋涂玻璃层覆盖，其中旋涂玻璃材料平坦化底层地形的表面。半导体层沉积在平坦化层的表面上以用作硬掩模，其中半导体层对于光化光是不透明的。半导体层被均匀厚度的光致抗蚀剂层覆盖。光致抗蚀剂层暴露于光化学光，其中半导体层防止光化反射光从其表面。显影和图案化光致抗蚀剂层以形成多晶硅层所需的光刻胶掩模。将不被光致抗蚀剂掩模覆盖的半导体层，旋涂玻璃层和多晶硅层各向异性地蚀刻掉以形成多晶硅栅电极和互连线。去除光致抗蚀剂掩模，硬掩模和旋涂玻璃层，以在集成电路的制造中完成多晶硅栅电极和具有均匀临界尺寸的互连线的形成。

10. 发明授权

US5573980A Method of forming salicided self-aligned contact for SRAM cells 失效
标题翻译：形成SRAM单元的水银自对准接触的方法
公开(公告)号：US5573980A
公开(公告)日：1996-11-12
申请号：US583917
申请日：1996-04-22
申请人： Chue-San Yoo
发明人： Chue-San Yoo
IPC分类号： H01L21/285 , H01L21/28
CPC分类号： H01L21/28518
摘要： This invention provides a method of forming very low resistance self-aligned silicide contacts to devices formed in a silicon integrated circuit substrate while avoiding the formation of stringers or stray silicide conductor paths. The method uses a thin layer of polysilicon which is patterned so as to only cover the contact region of the device being contacted. A layer of metal such as titanium is then deposited and the silicide is formed using rapid thermal annealing. The unreacted metal is then etched away. The primary application is to form a low resistance V.sub.ss plate for adjacent pull down transistors in SRAM cells but can be used in any device requiring a low resistance contact to silicon.
摘要翻译：本发明提供了一种形成非常低电阻的自对准硅化物触点到形成在硅集成电路衬底中的器件的方法，同时避免形成桁条或杂散硅化物导体路径。该方法使用图案化的薄层多晶硅，以仅覆盖被接触的器件的接触区域。然后沉积诸如钛的金属层，并且使用快速热退火形成硅化物。然后将未反应的金属蚀刻掉。主要的应用是形成用于SRAM单元中的相邻下拉晶体管的低电阻Vss板，但可用于需要与硅电阻低的触点的任何器件中。

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