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1. 发明申请

US20100061026A1 ESD PROTECTION CIRCUIT AND METHOD THEREOF 有权
标题翻译： ESD保护电路及其方法
公开(公告)号：US20100061026A1
公开(公告)日：2010-03-11
申请号：US12206748
申请日：2008-09-09
申请人： I-Cheng Lin , Tao Cheng
发明人： I-Cheng Lin , Tao Cheng
IPC分类号： H02H9/04
CPC分类号： H02H9/046 , H02H3/006
摘要： An Electrostatic Discharge protection circuit, the circuit includes a transient detecting circuit, a level adjusting circuit, a discharging circuit, and a sustaining circuit. The transient detecting circuit is coupled to a first pad for detecting an input signal at the first pad to generate a transient signal; the level adjusting circuit is coupled to the transient detecting circuit for adjusting an output voltage at an output terminal of the level adjusting circuit; the discharging circuit is coupled to the first pad and the output terminal of the level adjusting circuit for discharging the input signal of the first pad to a second pad when enabled by the output voltage; and the sustaining circuit is coupled between the level adjusting circuit and the transient detecting circuit, for selectively controlling the level adjusting circuit to sustain an enablement of the discharging circuit according to the transient signal.
摘要翻译：一种静电放电保护电路，电路包括瞬态检测电路，电平调节电路，放电电路和维持电路。瞬态检测电路耦合到第一焊盘，用于检测第一焊盘处的输入信号以产生瞬态信号; 电平调节电路耦合到瞬态检测电路，用于调整电平调节电路的输出端的输出电压; 放电电路耦合到电平调节电路的第一焊盘和输出端，用于当由输出电压使能时将第一焊盘的输入信号放电到第二焊盘; 并且所述维持电路耦合在所述电平调整电路和所述瞬态检测电路之间，用于选择性地控制所述电平调整电路，以根据所述瞬态信号维持所述放电电路的使能。

2. 发明授权

US08023237B2 ESD protection circuit and method thereof 有权
标题翻译： ESD保护电路及其方法
公开(公告)号：US08023237B2
公开(公告)日：2011-09-20
申请号：US12206748
申请日：2008-09-09
申请人： I-Cheng Lin , Tao Cheng
发明人： I-Cheng Lin , Tao Cheng
IPC分类号： H02H9/00
CPC分类号： H02H9/046 , H02H3/006
摘要： An Electrostatic Discharge protection circuit, the circuit includes a transient detecting circuit, a level adjusting circuit, a discharging circuit, and a sustaining circuit. The transient detecting circuit is coupled to a first pad for detecting an input signal at the first pad to generate a transient signal; the level adjusting circuit is coupled to the transient detecting circuit for adjusting an output voltage at an output terminal of the level adjusting circuit; the discharging circuit is coupled to the first pad and the output terminal of the level adjusting circuit for discharging the input signal of the first pad to a second pad when enabled by the output voltage; and the sustaining circuit is coupled between the level adjusting circuit and the transient detecting circuit, for selectively controlling the level adjusting circuit to sustain an enablement of the discharging circuit according to the transient signal.
摘要翻译：一种静电放电保护电路，电路包括瞬态检测电路，电平调节电路，放电电路和维持电路。瞬态检测电路耦合到第一焊盘，用于检测第一焊盘处的输入信号以产生瞬态信号; 电平调节电路耦合到瞬态检测电路，用于调整电平调节电路的输出端的输出电压; 放电电路耦合到电平调节电路的第一焊盘和输出端，用于当由输出电压使能时将第一焊盘的输入信号放电到第二焊盘; 并且所述维持电路耦合在所述电平调整电路和所述瞬态检测电路之间，用于选择性地控制所述电平调整电路以根据所述瞬态信号维持所述放电电路的使能。

3. 发明授权

US09594831B2 Targeted disambiguation of named entities 有权
标题翻译：指定实体的消除歧视
公开(公告)号：US09594831B2
公开(公告)日：2017-03-14
申请号：US13531493
申请日：2012-06-22
申请人： Chi Wang , Kaushik Chakrabarti , Tao Cheng , Surajit Chaudhuri
发明人： Chi Wang , Kaushik Chakrabarti , Tao Cheng , Surajit Chaudhuri
IPC分类号： G06F17/30 , G06F17/27
CPC分类号： G06F17/30687 , G06F17/278
摘要： A targeted disambiguation system is described herein which determines true mentions of a list of named entities in a collection of documents. The list of named entities is homogenous in the sense that the entities pertain to the same subject matter domain. The system determines the true mentions by leveraging the homogeneity in the list, and, more specifically by applying a context similarity hypothesis, a co-mention hypothesis, and an interdependency hypothesis. In one implementation, the system executes its analysis using a graph-based model. The system can operate without the existence of additional information regarding the entities in the list; nevertheless, if such information is available, the system can integrate it into its analysis.
摘要翻译：本文描述了一种有针对性的消歧系统，其确定了文档集合中真实提到的命名实体的列表。在实体属于相同主题领域的意义上，命名实体的列表是同质的。系统通过利用列表中的同质性来确定真实的提及，更具体地说，通过应用上下文相似性假设，共同提及假设和相互依赖性假设。在一个实现中，系统使用基于图的模型来执行其分析。该系统可以在没有关于列表中的实体的附加信息的情况下运行; 然而，如果这些信息可用，系统可以将其整合到其分析中。

4. 发明申请

US20130346421A1 TARGETED DISAMBIGUATION OF NAMED ENTITIES 有权
标题翻译：有名的实体的失明
公开(公告)号：US20130346421A1
公开(公告)日：2013-12-26
申请号：US13531493
申请日：2012-06-22
申请人： Chi Wang , Kaushik Chakrabarti , Tao Cheng , Surajit Chaudhuri
发明人： Chi Wang , Kaushik Chakrabarti , Tao Cheng , Surajit Chaudhuri
IPC分类号： G06F17/30
CPC分类号： G06F17/30687 , G06F17/278
摘要： A targeted disambiguation system is described herein which determines true mentions of a list of named entities in a collection of documents. The list of named entities is homogenous in the sense that the entities pertain to the same subject matter domain. The system determines the true mentions by leveraging the homogeneity in the list, and, more specifically by applying a context similarity hypothesis, a co-mention hypothesis, and an interdependency hypothesis. In one implementation, the system executes its analysis using a graph-based model. The system can operate without the existence of additional information regarding the entities in the list; nevertheless, if such information is available, the system can integrate it into its analysis.
摘要翻译：本文描述了一种有针对性的消歧系统，其确定了文档集合中真实提到的命名实体的列表。在实体属于相同主题领域的意义上，命名实体的列表是同质的。系统通过利用列表中的同质性来确定真实的提及，更具体地说，通过应用上下文相似性假设，共同提及假设和相互依赖性假设。在一个实现中，系统使用基于图的模型来执行其分析。该系统可以在没有关于列表中的实体的附加信息的情况下运行; 然而，如果这些信息可用，系统可以将其整合到其分析中。

5. 发明授权

US08138616B2 Bond pad structure 有权
标题翻译：焊盘结构
公开(公告)号：US08138616B2
公开(公告)日：2012-03-20
申请号：US12168161
申请日：2008-07-07
申请人： Tien-Chang Chang , Tao Cheng , Chien-Hui Chuang , Bo-Shih Huang
发明人： Tien-Chang Chang , Tao Cheng , Chien-Hui Chuang , Bo-Shih Huang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/05 , H01L23/522 , H01L23/585 , H01L23/60 , H01L2224/02166 , H01L2224/05093 , H01L2224/05095 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01023 , H01L2924/01025 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/05042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/30105 , H01L2924/00014 , H01L2924/00
摘要： A bond pad structure of an integrated circuit includes a conductive pad disposed on a first dielectric layer, a first conductive block formed in a second dielectric layer below the first dielectric layer and electrically connected to the conductive pad through a first via plug formed in the first dielectric layer, and an electrically floating first conductive plate situated under the conductive pad.
摘要翻译：集成电路的接合焊盘结构包括设置在第一介电层上的导电焊盘，形成在第一电介质层下面的第二电介质层中的第一导电块，并且通过形成在第一电介质层中的第一通孔插塞电连接到导电焊盘电介质层和位于导电垫下方的电浮置的第一导电板。

6. 发明申请

US20120038055A1 POWER AND GROUND ROUTING OF INTEGRATED CIRCUIT DEVICES WITH IMPROVED IR DROP AND CHIP PERFORMANCE 有权
标题翻译：具有改进的红外线和芯片性能的集成电路设备的电源和接地布线
公开(公告)号：US20120038055A1
公开(公告)日：2012-02-16
申请号：US13281458
申请日：2011-10-26
申请人： Ching-Chung Ko , Tao Cheng , Tien-Yueh Liu , Dar-Shii Chou , Peng-Cheng Kao
发明人： Ching-Chung Ko , Tao Cheng , Tien-Yueh Liu , Dar-Shii Chou , Peng-Cheng Kao
IPC分类号： H01L23/535
CPC分类号： H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit chip includes a semiconductor substrate having thereon a plurality of IMD layers and first conductive layers embedded in the IMD layers; a first insulating layer overlying the IMD layers and the first conductive layers; a plurality of first power/ground mesh wiring lines, in a second conductive layer overlying the first Insulating layer, for distributing power signal or ground signal; and a second insulating layer covering the second conductive layer and the first insulating layer.
摘要翻译：集成电路芯片包括其上具有多个IMD层的半导体衬底和嵌入IMD层中的第一导电层; 覆盖IMD层和第一导电层的第一绝缘层; 在覆盖所述第一绝缘层的第二导电层中的多个第一电源/接地网状布线，用于分配电力信号或接地信号; 以及覆盖所述第二导电层和所述第一绝缘层的第二绝缘层。

7. 发明授权

US08117208B2 System for entity search and a method for entity scoring in a linked document database 有权
标题翻译：用于实体搜索的系统和在链接的文档数据库中实体评分的方法
公开(公告)号：US08117208B2
公开(公告)日：2012-02-14
申请号：US12233812
申请日：2008-09-19
申请人： Kevin Chen-Chuan Chang , Tao Cheng , Xifeng Yan
发明人： Kevin Chen-Chuan Chang , Tao Cheng , Xifeng Yan
IPC分类号： G06F7/00 , G06F17/30
CPC分类号： G06F17/30867
摘要： A system has a processor coupled to access a document database that indexes keywords and instances of entities having entity types in a plurality of documents. The processor is programmed to receive an input query including one or more keywords and one or more entity types, and search the database for documents having the keywords and entities with the entity types of the input query. The processor is programmed for aggregating a respective score for each of a plurality of entity tuples across the plurality of documents. The aggregated scores are normalized. Each respective normalized score provides a ranking of a respective entity tuple, relative to other entity tuples, as an answer to the input query. The processor has an interface to a storage or display device or network for outputting a list including a subset of the entity tuples having the highest normalized scores among the plurality of entity tuples.
摘要翻译：系统具有处理器，其耦合到访问文档数据库，所述文档数据库在多个文档中对具有实体类型的关键字和实体的实例进行索引。处理器被编程为接收包括一个或多个关键字和一个或多个实体类型的输入查询，并且搜索数据库中具有关键词和具有输入查询的实体类型的实体的文档。处理器被编程用于聚集跨多个文档的多个实体元组中的每一个的相应分数。综合得分归一化。每个相应的归一化分数提供相对于其他实体元组的相应实体元组作为输入查询的答案的排序。处理器具有到存储或显示设备或网络的接口，用于输出包括多个实体元组中具有最高归一化分数的实体元组的子集的列表。

8. 发明授权

US07894170B2 ESD protection device 有权
标题翻译： ESD保护装置
公开(公告)号：US07894170B2
公开(公告)日：2011-02-22
申请号：US11081705
申请日：2005-03-17
申请人： Hsueh-Kun Liao , Tao Cheng
发明人： Hsueh-Kun Liao , Tao Cheng
IPC分类号： H02H9/00
CPC分类号： H01L27/0266
摘要： For maintaining the regular operating current in an inner circuit under electrostatic discharge (ESD) event, an ESD protection device is provided to control an ESD path switch in the turned-on condition by employing a MOS device and a latch-detected turned-on circuit. The MOS device has a self-aligned silicidation (Salicide) therein. The ESD protection device is used to stabilize operation efficiency and reduce the area of an ESD protection device without a silicide block disposed therein for enhancing the ESD protection capability.
摘要翻译：为了在静电放电（ESD）事件下保持内部电路中的常规工作电流，提供ESD保护装置，以通过采用MOS器件和锁存检测的导通电路来控制导通状态下的ESD路径开关。 MOS器件中具有自对准硅化物（Salicide）。 ESD保护装置用于稳定运行效率并减小ESD保护装置的面积，而不会在其中设置硅化物块，以增强ESD保护能力。

9. 发明授权

US07821038B2 Power and ground routing of integrated circuit devices with improved IR drop and chip performance 有权
标题翻译：集成电路器件的电源和接地布线具有改进的IR降低和芯片性能
公开(公告)号：US07821038B2
公开(公告)日：2010-10-26
申请号：US12052735
申请日：2008-03-21
申请人： Ching-Chung Ko , Tao Cheng , Tien-Yueh Liu , Dar-Shii Chou , Peng-Cheng Kao
发明人： Ching-Chung Ko , Tao Cheng , Tien-Yueh Liu , Dar-Shii Chou , Peng-Cheng Kao
IPC分类号： H01L27/10
CPC分类号： H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit chip with reduced IR drop and improved chip performance is disclosed. The integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of copper metal layers embedded in respective the plurality of IMD layers; a first passivation layer overlying the plurality of IMD layers and the plurality of copper metal layers; a first power/ground ring of a circuit block of the integrated circuit chip formed in a topmost layer of the plurality of copper metal layers; a second power/ground ring of the circuit block of the integrated circuit chip formed in an aluminum layer over the first passivation layer; and a second passivation layer covering the second power/ground ring and the first passivation layer.
摘要翻译：公开了具有降低的IR降低和芯片性能改善的集成电路芯片。集成电路芯片包括其上具有多个金属间电介质（IMD）层和嵌入在多个IMD层中的多个铜金属层的半导体衬底; 覆盖所述多个IMD层和所述多个铜金属层的第一钝化层; 所述集成电路芯片的电路块的第一电源/接地环形成在所述多个铜金属层的最上层中; 所述集成电路芯片的电路块的第二电源/接地环形成在所述第一钝化层上的铝层中; 以及覆盖所述第二电源/接地环和所述第一钝化层的第二钝化层。

10. 发明申请

US20100252860A1 LATERAL BIPOLAR JUNCTION TRANSISTOR WITH REDUCED BASE RESISTANCE 有权
标题翻译：具有降低基极电阻的侧向双极晶体管
公开(公告)号：US20100252860A1
公开(公告)日：2010-10-07
申请号：US12420046
申请日：2009-04-07
申请人： Ming-Tzong Yang , Tao Cheng , Ching-Chung Ko , Tung-Hsing Lee
发明人： Ming-Tzong Yang , Tao Cheng , Ching-Chung Ko , Tung-Hsing Lee
IPC分类号： H01L29/735
CPC分类号： H01L29/735 , H01L29/0692 , H01L29/423
摘要： A lateral bipolar junction transistor formed in a semiconductor substrate includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; a collector region having at least one open side and being disposed about a periphery of the base region; a shallow trench isolation (STI) region disposed about a periphery of the collector region; a base contact region disposed about a periphery of the STI region; and an extension region merging with the base contact region and laterally extending to the gate on the open side of the collector region.
摘要翻译：形成在半导体衬底中的横向双极结型晶体管包括发射极区域; 围绕发射极区域的基极区域; 设置在所述基部区域的至少一部分上的栅极; 具有至少一个开放侧并且围绕所述基底区域的周边设置的收集器区域; 设置在集电极区域周围的浅沟槽隔离（STI）区域; 设置在所述STI区域周围的基极接触区域; 以及与所述基极接触区域合并并横向延伸到所述集电极区域的开放侧的栅极的延伸区域。

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