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1. 发明申请

US20130013899A1 Using Hardware Transaction Primitives for Implementing Non-Transactional Escape Actions Inside Transactions 审中-公开
标题翻译：使用硬件事务原语在事务内部实现非事务性转义操作
公开(公告)号：US20130013899A1
公开(公告)日：2013-01-10
申请号：US13176833
申请日：2011-07-06
申请人： Christopher M. Barton , Harold W. Cain, III , Bradly G. Frey , Hung Q. Le , Maged M. Michael , Raul E. Silvera , Derek E. Williams , Michael Wong , Peng Wu
发明人： Christopher M. Barton , Harold W. Cain, III , Bradly G. Frey , Hung Q. Le , Maged M. Michael , Raul E. Silvera , Derek E. Williams , Michael Wong , Peng Wu
IPC分类号： G06F9/30
CPC分类号： G06F9/466
摘要： Mechanisms are provided for performing escape actions within transactions. These mechanisms execute a transaction comprising a transactional section and an escape action. The transactional section is comprised of one or more instructions that are to be executed in an atomic manner as part of the transaction. The escape action is comprised of one or more instructions to be executed in a non-transactional manner. These mechanisms further populate at least one actions list data structure, associated with a thread of the data processing system that is executing the transaction, with one or more actions associated with the escape action. Moreover, these mechanisms execute one or more actions in the actions list data structure based upon whether the transaction commits successfully or is aborted.
摘要翻译：提供了在事务中执行转义操作的机制。这些机制执行包括事务部分和转义动作的事务。事务部分由作为事务的一部分以原子方式执行的一个或多个指令组成。转义动作由以非事务方式执行的一个或多个指令组成。这些机制进一步填充与执行交易的数据处理系统的线程相关联的至少一个动作列表数据结构，其中一个或多个动作与转义动作相关联。此外，这些机制基于事务提交成功还是中止，在动作列表数据结构中执行一个或多个动作。

2. 发明授权

US08423750B2 Hardware assist thread for increasing code parallelism 有权
公开(公告)号：US08423750B2
公开(公告)日：2013-04-16
申请号：US12778192
申请日：2010-05-12
申请人： Ronald P. Hall , Hung Q. Le , Raul E. Silvera , Balaram Sinharoy
发明人： Ronald P. Hall , Hung Q. Le , Raul E. Silvera , Balaram Sinharoy
IPC分类号： G06F9/48
CPC分类号： G06F9/3851 , G06F9/3009 , G06F9/30101 , G06F9/30149 , G06F9/30189
摘要： Mechanisms are provided for offloading a workload from a main thread to an assist thread. The mechanisms receive, in a fetch unit of a processor of the data processing system, a branch-to-assist-thread instruction of a main thread. The branch-to-assist-thread instruction informs hardware of the processor to look for an already spawned idle thread to be used as an assist thread. Hardware implemented pervasive thread control logic determines if one or more already spawned idle threads are available for use as an assist thread. The hardware implemented pervasive thread control logic selects an idle thread from the one or more already spawned idle threads if it is determined that one or more already spawned idle threads are available for use as an assist thread, to thereby provide the assist thread. In addition, the hardware implemented pervasive thread control logic offloads a portion of a workload of the main thread to the assist thread.

3. 发明申请

US20110283095A1 Hardware Assist Thread for Increasing Code Parallelism 有权
标题翻译：硬件辅助线程增加代码并行性
公开(公告)号：US20110283095A1
公开(公告)日：2011-11-17
申请号：US12778192
申请日：2010-05-12
申请人： Ronald P. Hall , Hung Q. Le , Raul E. Silvera , Balaram Sinharoy
发明人： Ronald P. Hall , Hung Q. Le , Raul E. Silvera , Balaram Sinharoy
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3851 , G06F9/3009 , G06F9/30101 , G06F9/30149 , G06F9/30189
摘要： Mechanisms are provided for offloading a workload from a main thread to an assist thread. The mechanisms receive, in a fetch unit of a processor of the data processing system, a branch-to-assist-thread instruction of a main thread. The branch-to-assist-thread instruction informs hardware of the processor to look for an already spawned idle thread to be used as an assist thread. Hardware implemented pervasive thread control logic determines if one or more already spawned idle threads are available for use as an assist thread. The hardware implemented pervasive thread control logic selects an idle thread from the one or more already spawned idle threads if it is determined that one or more already spawned idle threads are available for use as an assist thread, to thereby provide the assist thread. In addition, the hardware implemented pervasive thread control logic offloads a portion of a workload of the main thread to the assist thread.
摘要翻译：提供了将工作负载从主线程卸载到辅助线程的机制。机构在数据处理系统的处理器的提取单元中接收主线程的分支到辅助线程指令。分支到辅助线程指令通知处理器的硬件来查找已经产生的空闲线程以用作辅助线程。硬件实现的普遍线程控制逻辑确定一个或多个已经产生的空闲线程是否可用作辅助线程。如果确定一个或多个已经产生的空闲线程可用作辅助线程，则实现的普遍线程控制逻辑的硬件从一个或多个已经产生的空闲线程中选择空闲线程，从而提供辅助线程。此外，实现的普遍线程控制逻辑的硬件将主线程的一部分工作量卸载到辅助线程。

4. 发明授权

US09037837B2 Hardware assist thread for increasing code parallelism 有权
标题翻译：用于增加代码并行性的硬件辅助线程
公开(公告)号：US09037837B2
公开(公告)日：2015-05-19
申请号：US13438087
申请日：2012-04-03
申请人： Ronald P. Hall , Hung Q. Le , Raul E. Silvera , Balaram Sinharoy
发明人： Ronald P. Hall , Hung Q. Le , Raul E. Silvera , Balaram Sinharoy
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3851 , G06F9/3009 , G06F9/30101 , G06F9/30149 , G06F9/30189
摘要： Mechanisms are provided for offloading a workload from a main thread to an assist thread. The mechanisms receive, in a fetch unit of a processor of the data processing system, a branch-to-assist-thread instruction of a main thread. The branch-to-assist-thread instruction informs hardware of the processor to look for an already spawned idle thread to be used as an assist thread. Hardware implemented pervasive thread control logic determines if one or more already spawned idle threads are available for use as an assist thread. The hardware implemented pervasive thread control logic selects an idle thread from the one or more already spawned idle threads if it is determined that one or more already spawned idle threads are available for use as an assist thread, to thereby provide the assist thread. In addition, the hardware implemented pervasive thread control logic offloads a portion of a workload of the main thread to the assist thread.
摘要翻译：提供了将工作负载从主线程卸载到辅助线程的机制。机构在数据处理系统的处理器的提取单元中接收主线程的分支到辅助线程指令。分支到辅助线程指令通知处理器的硬件来查找已经产生的空闲线程以用作辅助线程。硬件实现的普遍线程控制逻辑确定一个或多个已经产生的空闲线程是否可用作辅助线程。如果确定一个或多个已经产生的空闲线程可用作辅助线程，则实现的普遍线程控制逻辑的硬件从一个或多个已经产生的空闲线程中选择空闲线程，从而提供辅助线程。此外，实现的普遍线程控制逻辑的硬件将主线程的一部分工作量卸载到辅助线程。

5. 发明申请

US20120254594A1 Hardware Assist Thread for Increasing Code Parallelism 审中-公开
标题翻译：硬件辅助线程增加代码并行性
公开(公告)号：US20120254594A1
公开(公告)日：2012-10-04
申请号：US13438087
申请日：2012-04-03
申请人： Ronald P. Hall , Hung Q. Le , Raul E. Silvera , Balaram Sinharoy
发明人： Ronald P. Hall , Hung Q. Le , Raul E. Silvera , Balaram Sinharoy
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3009 , G06F9/30101 , G06F9/30149 , G06F9/30189
摘要： Mechanisms are provided for offloading a workload from a main thread to an assist thread. The mechanisms receive, in a fetch unit of a processor of the data processing system, a branch-to-assist-thread instruction of a main thread. The branch-to-assist-thread instruction informs hardware of the processor to look for an already spawned idle thread to be used as an assist thread. Hardware implemented pervasive thread control logic determines if one or more already spawned idle threads are available for use as an assist thread. The hardware implemented pervasive thread control logic selects an idle thread from the one or more already spawned idle threads if it is determined that one or more already spawned idle threads are available for use as an assist thread, to thereby provide the assist thread. In addition, the hardware implemented pervasive thread control logic offloads a portion of a workload of the main thread to the assist thread.
摘要翻译：提供了将工作负载从主线程卸载到辅助线程的机制。机构在数据处理系统的处理器的提取单元中接收主线程的分支到辅助线程指令。分支到辅助线程指令通知处理器的硬件来查找已经产生的空闲线程以用作辅助线程。硬件实现的普遍线程控制逻辑确定一个或多个已经产生的空闲线程是否可用作辅助线程。如果确定一个或多个已经产生的空闲线程可用作辅助线程，则实现的普遍线程控制逻辑的硬件从一个或多个已经产生的空闲线程中选择空闲线程，从而提供辅助线程。此外，实现的普遍线程控制逻辑的硬件将主线程的一部分工作量卸载到辅助线程。

6. 发明申请

US20110209155A1 SPECULATIVE THREAD EXECUTION WITH HARDWARE TRANSACTIONAL MEMORY 有权
标题翻译：具有硬件交互式存储器的线性螺纹执行
公开(公告)号：US20110209155A1
公开(公告)日：2011-08-25
申请号：US12711352
申请日：2010-02-24
申请人： Mark E. Giampapa , Thomas M. Gooding , Raul E. Silvera , Kai-Ting Amy Wang , Peng Wu , Xiaotong Zhuang
发明人： Mark E. Giampapa , Thomas M. Gooding , Raul E. Silvera , Kai-Ting Amy Wang , Peng Wu , Xiaotong Zhuang
IPC分类号： G06F9/46 , G06F12/08 , G06F12/00
CPC分类号： G06F9/466 , G06F9/3842 , G06F9/467 , G06F9/4843 , G06F9/4881 , G06F9/5016 , G06F9/52 , G06F12/0862
摘要： In an embodiment, if a self thread has more than one conflict, a transaction of the self thread is aborted and restarted. If the self thread has only one conflict and an enemy thread of the self thread has more than one conflict, the transaction of the self thread is committed. If the self thread only conflicts with the enemy thread and the enemy thread only conflicts with the self thread and the self thread has a key that has a higher priority than a key of the enemy thread, the transaction of the self thread is committed. If the self thread only conflicts with the enemy thread, the enemy thread only conflicts with the self thread, and the self thread has a key that has a lower priority than the key of the enemy thread, the transaction of the self thread is aborted.
摘要翻译：在一个实施例中，如果自线程具有多于一个冲突，则自线程的事务被中止并重新启动。如果自线程只有一个冲突，并且自线程的敌方线程有多个冲突，则自线程的事务被提交。如果自线程只与敌方线程冲突，敌方线程只与自线程冲突，自线程的密钥优先级高于敌方线程的密钥，则自线程的事务被提交。如果自线程只与敌方线程相冲突，敌方线程只会与自身线程冲突，自线程的密钥优先级低于敌方线程的密钥，自身线程的事务中止。

7. 发明授权

US08438568B2 Speculative thread execution with hardware transactional memory 有权
标题翻译：使用硬件事务内存的推测线程执行
公开(公告)号：US08438568B2
公开(公告)日：2013-05-07
申请号：US12711352
申请日：2010-02-24
申请人： Mark E. Giampapa , Thomas M. Gooding , Raul E. Silvera , Kai-Ting Amy Wang , Peng Wu , Xiaotong Zhuang
发明人： Mark E. Giampapa , Thomas M. Gooding , Raul E. Silvera , Kai-Ting Amy Wang , Peng Wu , Xiaotong Zhuang
IPC分类号： G06F9/46 , G06F7/00 , G06F13/00
CPC分类号： G06F9/466 , G06F9/3842 , G06F9/467 , G06F9/4843 , G06F9/4881 , G06F9/5016 , G06F9/52 , G06F12/0862
摘要： In an embodiment, if a self thread has more than one conflict, a transaction of the self thread is aborted and restarted. If the self thread has only one conflict and an enemy thread of the self thread has more than one conflict, the transaction of the self thread is committed. If the self thread only conflicts with the enemy thread and the enemy thread only conflicts with the self thread and the self thread has a key that has a higher priority than a key of the enemy thread, the transaction of the self thread is committed. If the self thread only conflicts with the enemy thread, the enemy thread only conflicts with the self thread, and the self thread has a key that has a lower priority than the key of the enemy thread, the transaction of the self thread is aborted.
摘要翻译：在一个实施例中，如果自线程具有多于一个冲突，则自线程的事务被中止并重新启动。如果自线程只有一个冲突，并且自线程的敌方线程有多个冲突，则自线程的事务被提交。如果自线程只与敌方线程冲突，敌方线程只与自线程冲突，自线程的密钥优先级高于敌方线程的密钥，则自线程的事务被提交。如果自线程只与敌方线程相冲突，敌方线程只会与自身线程冲突，自线程的密钥优先级低于敌方线程的密钥，自身线程的事务中止。

8. 发明授权

US08056066B2 Method and apparatus for address taken refinement using control flow information 失效
标题翻译：使用控制流信息进行地址改善的方法和装置
公开(公告)号：US08056066B2
公开(公告)日：2011-11-08
申请号：US11843369
申请日：2007-08-22
申请人： Edwin Chan , Raul E. Silvera
发明人： Edwin Chan , Raul E. Silvera
IPC分类号： G06F9/45
CPC分类号： G06F8/434
摘要： A computer implemented method, apparatus, and computer program product for obtaining aliasing information for a target variable in a computer program. A control flow graph representing the computer program is partitioned into an taken address portion that includes all reachable nodes in which an address of the target variable is taken and an untaken address portion that includes all other reachable nodes. All references to the target variable are replaced with a temporary variable in the untaken address portion. The target variable is initialized with the value from the temporary variable at each intermediary node in a set of intermediary nodes in the taken address portion. An intermediary node is a node at which an address of a target variable is taken. The aliasing information for the target variable is generated using the modified computer program.
摘要翻译：一种用于在计算机程序中获得目标变量的混叠信息的计算机实现的方法，装置和计算机程序产品。表示计算机程序的控制流程图被划分成一个取得的地址部分，该部分包括其中取得目标变量的地址的所有可到达节点以及包含所有其他可到达节点的未被捕获的地址部分。所有对目标变量的引用将被替换为未被捕获的地址部分中的临时变量。目标变量用被采取的地址部分中的一组中间节点中的每个中间节点处的临时变量的值初始化。中间节点是采用目标变量的地址的节点。使用修改的计算机程序生成目标变量的混叠信息。

9. 发明授权

US08015556B2 Efficient method of data reshaping for multidimensional dynamic array objects in the presence of multiple object instantiations 失效
标题翻译：在存在多个对象实例化的情况下，用于多维动态数组对象的数据重构的高效方法
公开(公告)号：US08015556B2
公开(公告)日：2011-09-06
申请号：US11548725
申请日：2006-10-12
申请人： Shimin Cui , Raul E. Silvera
发明人： Shimin Cui , Raul E. Silvera
IPC分类号： G06F9/45
CPC分类号： G06F12/0253
摘要： A method of data reshaping for multidimensional dynamic array objects in the presence of multiple object instantiations. The method includes collecting all alias information using interprocedural point escape analysis, and collecting all shape information using interprocedural shape analysis. The method progresses with selecting the candidate dynamic objects based on alias and shape analysis, and determining the types of data reshaping for the candidate dynamic objects. The method further includes creating objects for selected dynamic objects with multiple object instantiations. The method proceeds by updating the memory allocation operations for the selected dynamic objects and inserting statements to initialize object descriptors. The method further includes creating the copy of the object descriptors for selected dynamic object assignments. The method concludes by replacing the object references by array-indexed references for selected dynamic objects using object descriptors.
摘要翻译：在存在多个对象实例化的情况下，用于多维动态数组对象的数据整形方法。该方法包括使用过程间点逃逸分析来收集所有别名信息，并使用过程间形状分析收集所有形状信息。该方法通过基于别名和形状分析来选择候选动态对象，并确定为候选动态对象重新整形的类型。该方法还包括为具有多个对象实例化的所选择的动态对象创建对象。该方法通过更新所选动态对象的内存分配操作并插入语句来初始化对象描述符。该方法还包括为所选择的动态对象分配创建对象描述符的副本。该方法通过使用对象描述符替换对所选动态对象的数组索引引用的对象引用。

10. 发明申请

US20090064119A1 Systems, Methods, And Computer Products For Compiler Support For Aggressive Safe Load Speculation 失效
标题翻译：用于编译器支持的系统，方法和计算机产品进行安全负载投机
公开(公告)号：US20090064119A1
公开(公告)日：2009-03-05
申请号：US11845491
申请日：2007-08-27
申请人： Roch G. Archambault , Geoffrey O. Blandy , Roland Froese , Yaoqing Gao , Liangxiao Hu , James L. McInnes , Raul E. Silvera
发明人： Roch G. Archambault , Geoffrey O. Blandy , Roland Froese , Yaoqing Gao , Liangxiao Hu , James L. McInnes , Raul E. Silvera
IPC分类号： G06F9/45
CPC分类号： G06F8/4441
摘要： Systems, methods and computer products for compiler support for aggressive safe load speculation. Exemplary embodiments include a method for aggressive safe load speculation for a compiler in a computer system, the method including building a control flow graph, identifying both countable and non-countable loops, gathering a set of candidate loops for load speculation, for each candidate loop in the set of candidate loops gathered for load speculation performing computing an estimate of the iteration count, delay cycles, and code size, performing a profitability analysis and determine an unroll factor based on the delay cycles and the code size, transforming the loop by generating a prologue loop to achieve data alignment and an unrolled main loop with loop directives, indicating which loads can safely be executed speculatively and performing low-level instruction on the generated unrolled main loop.
摘要翻译：用于编译器的系统，方法和计算机产品支持攻击性安全负载推测。示例性实施例包括用于计算机系统中的编译器的积极安全负载推测的方法，所述方法包括建立控制流程图，识别可计数循环和不可计数循环，为每个候选循环收集用于负载推测的一组候选循环在针对负载推测而收集的候选循环集合中，执行计算迭代计数，延迟周期和代码大小的估计，执行盈利能力分析并基于延迟周期和代码大小来确定展开因子，通过生成用于实现数据对齐的序言循环和循环指令的展开主循环，指示哪些负载可以安全地推测执行，并对生成的非滚动主循环执行低级指令。

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