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1. 发明申请

US20130013899A1 Using Hardware Transaction Primitives for Implementing Non-Transactional Escape Actions Inside Transactions 审中-公开
标题翻译：使用硬件事务原语在事务内部实现非事务性转义操作
公开(公告)号：US20130013899A1
公开(公告)日：2013-01-10
申请号：US13176833
申请日：2011-07-06
申请人： Christopher M. Barton , Harold W. Cain, III , Bradly G. Frey , Hung Q. Le , Maged M. Michael , Raul E. Silvera , Derek E. Williams , Michael Wong , Peng Wu
发明人： Christopher M. Barton , Harold W. Cain, III , Bradly G. Frey , Hung Q. Le , Maged M. Michael , Raul E. Silvera , Derek E. Williams , Michael Wong , Peng Wu
IPC分类号： G06F9/30
CPC分类号： G06F9/466
摘要： Mechanisms are provided for performing escape actions within transactions. These mechanisms execute a transaction comprising a transactional section and an escape action. The transactional section is comprised of one or more instructions that are to be executed in an atomic manner as part of the transaction. The escape action is comprised of one or more instructions to be executed in a non-transactional manner. These mechanisms further populate at least one actions list data structure, associated with a thread of the data processing system that is executing the transaction, with one or more actions associated with the escape action. Moreover, these mechanisms execute one or more actions in the actions list data structure based upon whether the transaction commits successfully or is aborted.
摘要翻译：提供了在事务中执行转义操作的机制。这些机制执行包括事务部分和转义动作的事务。事务部分由作为事务的一部分以原子方式执行的一个或多个指令组成。转义动作由以非事务方式执行的一个或多个指令组成。这些机制进一步填充与执行交易的数据处理系统的线程相关联的至少一个动作列表数据结构，其中一个或多个动作与转义动作相关联。此外，这些机制基于事务提交成功还是中止，在动作列表数据结构中执行一个或多个动作。

2. 发明申请

US20140013060A1 ENSURING CAUSALITY OF TRANSACTIONAL STORAGE ACCESSES INTERACTING WITH NON-TRANSACTIONAL STORAGE ACCESSES 有权
公开(公告)号：US20140013060A1
公开(公告)日：2014-01-09
申请号：US13543325
申请日：2012-07-06
申请人： Bradly G. Frey , Cathy May , Derek E. Williams
发明人： Bradly G. Frey , Cathy May , Derek E. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0842 , G06F9/466 , G06F12/0813 , G06F12/0831
摘要： A data processing system implements a weak consistency memory model for a distributed shared memory system. The data processing system concurrently executes, on a plurality of processor cores, one or more transactional memory instructions within a memory transaction and one or more non-transactional memory instructions. The one or more non-transactional memory instructions include a non-transactional store instruction. The data processing system commits the memory transaction to the distributed shared memory system only in response to enforcement of causality of the non-transactional store instruction with respect to the memory transaction.

3. 发明授权

US09244846B2 Ensuring causality of transactional storage accesses interacting with non-transactional storage accesses 有权
标题翻译：确保交易存储访问的因果关系与非事务性存储访问进行交互
公开(公告)号：US09244846B2
公开(公告)日：2016-01-26
申请号：US13543325
申请日：2012-07-06
申请人： Bradly G. Frey , Cathy May , Derek E. Williams
发明人： Bradly G. Frey , Cathy May , Derek E. Williams
IPC分类号： G06F12/08 , G06F9/46
CPC分类号： G06F12/0842 , G06F9/466 , G06F12/0813 , G06F12/0831
摘要： A data processing system implements a weak consistency memory model for a distributed shared memory system. The data processing system concurrently executes, on a plurality of processor cores, one or more transactional memory instructions within a memory transaction and one or more non-transactional memory instructions. The one or more non-transactional memory instructions include a non-transactional store instruction. The data processing system commits the memory transaction to the distributed shared memory system only in response to enforcement of causality of the non-transactional store instruction with respect to the memory transaction.
摘要翻译：数据处理系统为分布式共享存储器系统实现弱一致性存储器模型。数据处理系统在多个处理器核心上同时执行存储器事务内的一个或多个事务存储器指令和一个或多个非事务存储器指令。一个或多个非事务存储器指令包括非事务存储指令。数据处理系统只是为了响应于关于存储器事务的非事务性存储指令的因果关系的强制而将存储器事务提交给分布式共享存储器系统。

4. 发明申请

US20140013055A1 ENSURING CAUSALITY OF TRANSACTIONAL STORAGE ACCESSES INTERACTING WITH NON-TRANSACTIONAL STORAGE ACCESSES 审中-公开
标题翻译：确保与非交易存储访问交互的交易存储访问的原理
公开(公告)号：US20140013055A1
公开(公告)日：2014-01-09
申请号：US13777161
申请日：2013-02-26
申请人： Bradly G. Frey , Cathy May , Derek E. Williams
发明人： Bradly G. Frey , Cathy May , Derek E. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0842 , G06F9/466 , G06F12/0813 , G06F12/0831
摘要： A data processing system implements a weak consistency memory model for a distributed shared memory system. The data processing system concurrently executes, on a plurality of processor cores, one or more transactional memory instructions within a memory transaction and one or more non-transactional memory instructions. The one or more non-transactional memory instructions include a non-transactional store instruction. The data processing system commits the memory transaction to the distributed shared memory system only in response to enforcement of causality of the non-transactional store instruction with respect to the memory transaction.
摘要翻译：数据处理系统为分布式共享存储器系统实现弱一致性存储器模型。数据处理系统在多个处理器核心上同时执行存储器事务内的一个或多个事务存储器指令和一个或多个非事务存储器指令。一个或多个非事务存储器指令包括非事务存储指令。数据处理系统只是为了响应于关于存储器事务的非事务性存储指令的因果关系的强制而将存储器事务提交给分布式共享存储器系统。

5. 发明授权

US08495308B2 Processor, data processing system and method supporting a shared global coherency state 失效
标题翻译：处理器，数据处理系统和支持共享全局一致性状态的方法
公开(公告)号：US08495308B2
公开(公告)日：2013-07-23
申请号：US11539694
申请日：2006-10-09
申请人： Guy L. Guthrie , William J. Starke , Derek E. Williams , Phillip G. Williams
发明人： Guy L. Guthrie , William J. Starke , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0817
摘要： A multiprocessor data processing system includes at least first and second coherency domains, where the first coherency domain includes a system memory and a cache memory. According to a method of data processing, a cache line is buffered in a data array of the cache memory and a state field in a cache directory of the cache memory is set to a coherency state to indicate that the cache line is valid in the data array, that the cache line is held in the cache memory non-exclusively, and that another cache in said second coherency domain may hold a copy of the cache line.
摘要翻译：多处理器数据处理系统至少包括第一和第二相干域，其中第一相干域包括系统存储器和高速缓冲存储器。根据数据处理的方法，将高速缓存行缓冲在高速缓冲存储器的数据阵列中，高速缓冲存储器的高速缓存目录中的状态字段被设置为一致性状态，以指示高速缓存行在数据中是有效的数组，高速缓存存储器行被非排他地保存在高速缓冲存储器中，并且所述第二相干域中的另一个高速缓冲存储器可以保存高速缓存行的副本。

6. 发明授权

US08453080B2 Model build in the presence of a non-binding reference 失效
标题翻译：存在非绑定引用的模型构建
公开(公告)号：US08453080B2
公开(公告)日：2013-05-28
申请号：US12335766
申请日：2008-12-16
申请人： Wolfgang Roesner , Robert J. Shadowen , Derek E. Williams
发明人： Wolfgang Roesner , Robert J. Shadowen , Derek E. Williams
IPC分类号： G06F17/50 , G06F9/455 , G06F7/62
CPC分类号： G06F17/5045
摘要： One or more hardware description language (HDL) files describe a plurality of hierarchically arranged design entities defining a digital design to be simulated and a plurality of configuration entities not belonging to the digital design that logically control settings of a plurality of configuration latches in the digital design. The HDL file(s) are compiled to obtain a simulation executable model of the digital design and an associated configuration database. The compiling includes parsing a configuration statement that specifies an association between an instance of a configuration entity and a specified configuration latch, determining whether or not the specified configuration latch is described in the HDL file(s), and if not, creating an indication in the configuration database that the instance of the configuration latch had a specified association to a configuration latch to which it failed to bind.
摘要翻译：一个或多个硬件描述语言（HDL）文件描述了定义要仿真的数字设计的多个分层布置的设计实体以及不属于数字设计的多个配置实体，所述多个配置实体逻辑地控制数字的多个配置锁存器的设置设计。编译HDL文件以获得数字设计的模拟可执行模型和相关联的配置数据库。编译包括解析配置语句，该配置语句指定配置实体的实例与指定的配置锁存器之间的关联，确定在HDL文件中是否描述了指定的配置锁存器，以及如果不是，则创建指示配置数据库，配置锁存器的实例与其无法绑定到的配置锁存器具有指定的关联。

7. 发明授权

US08108199B2 Phase events in a simulation model of a digital system 失效
标题翻译：数字系统仿真模型中的相位事件
公开(公告)号：US08108199B2
公开(公告)日：2012-01-31
申请号：US12130104
申请日：2008-05-30
申请人： Gabor Bobok , Wolfgang Roesner , Derek E. Williams
发明人： Gabor Bobok , Wolfgang Roesner , Derek E. Williams
IPC分类号： G06F9/45
CPC分类号： G06F17/5022
摘要： According to a method of simulation processing, an instrumented simulation executable model of a design is built by compiling one or more hardware description language (HDL) files specifying one or more design entities within the design and one or more instrumentation entities and instantiating instances of the one or more instrumentation entities within instances of the one or more design entities. Operation of the design is then simulated utilizing the instrumented simulation executable model. Simulating operation includes each of multiple instantiations of the one or more instrumentation entities generating a respective external phase signal representing an occurrence of a particular phase of operation and instrumentation combining logic generating from external phase signals of the multiple instantiations of the one or more instrumentation entities an aggregate phase signal representing an occurrence of the particular phase.
摘要翻译：根据模拟处理的方法，通过编译指定设计中的一个或多个设计实体的一个或多个硬件描述语言（HDL）文件和一个或多个设备实体和一个或多个设备实例的实例化来构建设计的仪器化模拟可执行模型在一个或多个设计实体的实例内的一个或多个仪表实体。然后使用仪器化模拟可执行模型对设计的操作进行模拟。模拟操作包括一个或多个仪器实体的多个实例中的每个实例，其产生表示特定操作阶段的出现的相应的外部相位信号，以及组合从一个或多个仪器实体的多个实例的外部相位信号产生的逻辑聚合相位信号表示特定相位的出现。

8. 发明授权

US07984256B2 Data processing system and method in which a participant initiating a read operation protects data integrity 失效
标题翻译：数据处理系统和方法，其中发起读取操作的参与者保护数据完整性
公开(公告)号：US07984256B2
公开(公告)日：2011-07-19
申请号：US11250022
申请日：2005-10-13
申请人： James S. Fields, Jr. , Guy L. Guthrie , John T. Hollaway, Jr. , Derek E. Williams
发明人： James S. Fields, Jr. , Guy L. Guthrie , John T. Hollaway, Jr. , Derek E. Williams
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0831 , G06F12/0815 , G06F12/0824
摘要： A data processing system includes a plurality of requestors and a memory controller for a system memory. In response to receiving from the requestor a read-type request targeting a memory block in the system memory, the memory controller protects the memory block from modification, and in response to an indication that the memory controller is responsible for servicing the read-type request, the memory controller transmits the memory block to the requestor. Prior to receipt of the memory block by the requestor, the memory controller ends protection of the memory block from modification, and the requestor begins protection of the memory block from modification. In response to receipt of the memory block, the requestor ends its protection of the memory block from modification.
摘要翻译：数据处理系统包括多个请求者和用于系统存储器的存储器控制器。响应于从请求者接收到针对系统存储器中的存储器块的读取型请求，存储器控制器保护存储器块免受修改，并且响应于存储器控制器负责维护读取类型请求的指示存储器控制器将该存储器块发送给请求者。在请求者接收到存储器块之前，存储器控制器结束对存储器块的保护而不被修改，并且请求者开始保护存储器块免受修改。响应于存储器块的接收，请求者结束其对存储器块的保护以免修改。

9. 发明授权

US07912694B2 Print events in the simulation of a digital system 有权
标题翻译：在数字系统的模拟中打印事件
公开(公告)号：US07912694B2
公开(公告)日：2011-03-22
申请号：US11668542
申请日：2007-01-30
申请人： Gabor Bobok , Wolfgang Roesner , Derek E. Williams
发明人： Gabor Bobok , Wolfgang Roesner , Derek E. Williams
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5022
摘要： According to a method of simulation processing, one or more HDL source files describing a digital design including a plurality of hierarchically arranged design entities are received. The one or more HDL source files include one or more statements instantiating a plurality of print events within the plurality of hierarchically arranged design entities, where each print event has an associated message and at least one associated signal in the digital design. The one or more HDL source files are processed to obtain a simulation executable model including a data structure describing the plurality of print events defined for the simulation executable model and associating each of the plurality of print events with its respective associated signal.
摘要翻译：根据模拟处理的方法，接收描述包括多个分层布置的设计实体的数字设计的一个或多个HDL源文件。一个或多个HDL源文件包括实例化多个分层布置的设计实体中的多个打印事件的一个或多个语句，其中每个打印事件具有相关联的消息和数字设计中的至少一个相关联的信号。处理一个或多个HDL源文件以获得模拟可执行模型，其包括描述为模拟可执行模型定义的多个打印事件的数据结构，并将多个打印事件中的每一个与其相应的相关信号相关联。

10. 发明申请

US20110047352A1 MEMORY COHERENCE DIRECTORY SUPPORTING REMOTELY SOURCED REQUESTS OF NODAL SCOPE 失效
标题翻译：记忆协调指导原则支持远程请求的NODAL范围
公开(公告)号：US20110047352A1
公开(公告)日：2011-02-24
申请号：US12545246
申请日：2009-08-21
申请人： Paul A. Ganfield , Guy L. Guthrie , David J. Krolak , Michael S. Siegel , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams
发明人： Paul A. Ganfield , Guy L. Guthrie , David J. Krolak , Michael S. Siegel , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams
IPC分类号： G06F15/76 , G06F9/02 , G06F12/08
CPC分类号： G06F12/0817
摘要： A data processing system includes at least a first through third processing nodes coupled by an interconnect fabric. The first processing node includes a master, a plurality of snoopers capable of participating in interconnect operations, and a node interface that receives a request of the master and transmits the request of the master to the second processing unit with a nodal scope of transmission limited to the second processing node. The second processing node includes a node interface having a directory. The node interface of the second processing node permits the request to proceed with the nodal scope of transmission if the directory does not indicate that a target memory block of the request is cached other than in the second processing node and prevents the request from succeeding if the directory indicates that the target memory block of the request is cached other than in the second processing node.
摘要翻译：数据处理系统至少包括通过互连结构耦合的第一至第三处理节点。第一处理节点包括主机，能够参与互连操作的多个侦听器，以及接收主机请求的节点接口，并将主机的请求传送到第二处理单元，传送范围限于第二处理节点。第二处理节点包括具有目录的节点接口。第二处理节点的节点接口允许请求继续进行节点传输范围，如果该目录没有指示该请求的目标存储器块不是在第二处理节点中被缓存，并且如果该请求成功目录指示除第二处理节点之外的请求的目标存储块被缓存。

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