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1. 发明申请

US20080077667A1 METHOD FOR ADAPTIVE GROUP SCHEDULING USING MOBILE AGENTS IN PEER-TO-PEER GRID COMPUTING ENVIRONMENT 审中-公开
标题翻译：使用移动代理在对等网格计算环境中进行自适应组调度的方法
公开(公告)号：US20080077667A1
公开(公告)日：2008-03-27
申请号：US11535159
申请日：2006-09-26
申请人： Chong-Sun Hwang , Sung-Jin Choi , Hong-Soo Kim , Eun-Joung Byun , Seok-In Kim , Soo-Jin Koo
发明人： Chong-Sun Hwang , Sung-Jin Choi , Hong-Soo Kim , Eun-Joung Byun , Seok-In Kim , Soo-Jin Koo
IPC分类号： G06F15/16
CPC分类号： H04L67/34 , G06F9/505 , G06F2209/5017
摘要： Embodiments of the present invention relates to mobile agent technology which includes a scheduling mechanism adaptive to dynamic peer-to-peer grid computing environments. A mobile agent is a software program that migrates from one node to another while performing various tasks on behalf of a user.
摘要翻译：本发明的实施例涉及移动代理技术，其包括适应动态对等网格计算环境的调度机制。移动代理是从代表用户执行各种任务的一个节点迁移到另一个节点的软件程序。

2. 发明申请

US20090201733A1 FLASH MEMORY DEVICE 失效
标题翻译：闪存存储器件
公开(公告)号：US20090201733A1
公开(公告)日：2009-08-13
申请号：US12367889
申请日：2009-02-09
申请人： Hong-Soo Kim , Hwa-Kyung Shin , Min-Chul Kim
发明人： Hong-Soo Kim , Hwa-Kyung Shin , Min-Chul Kim
IPC分类号： G11C16/06 , G11C8/00
CPC分类号： G11C16/08
摘要： A flash memory device can include a memory cell array that includes a plurality of memory blocks, where each of the memory blocks has memory cells arranged at intersections of word lines and bit lines, where ones of the plurality of memory blocks are immediately adjacent to one another and define memory block pairs. The flash memory device can further include a row selection circuit that is configured to drive the word lines responsive to memory operations associated with a memory address, where the row selection circuit can include respective shield lines that are located between the memory blocks included in each pair and each of the memory blocks in the pair has a common source line therebetween.
摘要翻译：闪速存储器件可以包括存储单元阵列，其包括多个存储器块，其中每个存储器块具有排列在字线和位线的交点处的存储器单元，其中多个存储器块中的一个存储器块紧邻于一个存储器块另一个并定义内存块对。闪存器件还可以包括行选择电路，其被配置为响应于与存储器地址相关联的存储器操作来驱动字线，其中行选择电路可以包括位于每对中包括的存储器块之间的各个屏蔽线并且该对中的每个存储器块之间具有公共源极线。

3. 发明授权

US06979628B2 Methods of forming semiconductor devices having field oxides in trenches and devices formed thereby 有权
标题翻译：在沟槽中形成具有场氧化物的半导体器件和由此形成的器件的方法
公开(公告)号：US06979628B2
公开(公告)日：2005-12-27
申请号：US10726788
申请日：2003-12-02
申请人： Hong-Soo Kim , Kyu-Charn Park , Jung-Dal Choi , Seong-Soon Cho
发明人： Hong-Soo Kim , Kyu-Charn Park , Jung-Dal Choi , Seong-Soon Cho
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76229 , H01L21/76205 , H01L21/76213 , H01L21/76232 , H01L21/76237
摘要： Semiconductor devices and methods of forming devices that have field oxides in trenches are disclosed. According to the methods, a semiconductor substrate is prepared. An upper trench is formed at a predetermined region of the semiconductor substrate and a bottom trench is formed at a bottom surface of the upper trench. A field oxide is formed to fill the bottom trench and the upper trench. At this time, the upper trench has a wider width than the bottom trench.
摘要翻译：公开了在沟槽中形成具有场氧化物的器件的半导体器件和方法。根据该方法制备半导体衬底。在半导体衬底的预定区域处形成上沟槽，并且在上沟槽的底表面处形成底沟槽。形成场氧化物以填充底部沟槽和上部沟槽。此时，上沟槽的宽度比底沟宽。

4. 发明授权

US06873016B2 Semiconductor device and method of forming the same 失效
公开(公告)号：US06873016B2
公开(公告)日：2005-03-29
申请号：US10678586
申请日：2003-10-03
申请人： Jin-Taek Park , Hong-Soo Kim
发明人： Jin-Taek Park , Hong-Soo Kim
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8247 , H01L27/06 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L28/20 , H01L27/0629
摘要： A semiconductor device including a resistor and a method of forming the same. In the semiconductor device, a conductive pattern, which connects source regions, and a resistor are formed of the same material, which can be polysilicon. In the method, the conductive pattern and the resistor are simultaneously formed. Thus, it is possible to obtain a constant sheet resistance without an additional photo mask.

5. 发明授权

US06828637B2 Semiconductor memory devices having dummy active regions 有权
标题翻译：半导体存储器件具有虚拟有源区
公开(公告)号：US06828637B2
公开(公告)日：2004-12-07
申请号：US10794533
申请日：2004-03-05
申请人： Hong-Soo Kim , Jung-Dal Choi , Jong-Sun Sel , Yong-Joon Choi
发明人： Hong-Soo Kim , Jung-Dal Choi , Jong-Sun Sel , Yong-Joon Choi
IPC分类号： H01L2976
CPC分类号： H01L23/564 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device having a dummy active region is provided, which includes a plurality of parallel main active regions and a dummy active region coupled to ends of the main active regions. The main preferably active regions are arranged in a main memory cell array region and extend to or through a dummy cell array region surrounding the main memory cell array region. Further, the dummy active region is perpendicular to the main active regions. A redundancy cell array region may intervene between the main memory cell array region and the dummy cell array region. In this case, the main active regions are extended to the dummy cell array region through the redundancy cell array region.
摘要翻译：提供了具有虚设有源区的半导体存储器件，其包括多个平行的主有效区和与主有效区的端部耦合的虚拟有源区。主要优选的有源区域被布置在主存储单元阵列区域中并且延伸到或通过围绕主存储单元阵列区域的虚设单元阵列区域。此外，虚拟有源区域垂直于主要有源区域。冗余单元阵列区域可以介于主存储单元阵列区域和虚设单元阵列区域之间。在这种情况下，主要有源区域通过冗余单元阵列区域扩展到虚拟单元阵列区域。

6. 发明申请

US20060289938A1 Non-volatile memory devices and related methods 审中-公开
标题翻译：非易失性存储器件及相关方法
公开(公告)号：US20060289938A1
公开(公告)日：2006-12-28
申请号：US11473788
申请日：2006-06-23
申请人： Hong-Soo Kim
发明人： Hong-Soo Kim
IPC分类号： H01L29/76
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11534 , H01L29/6656
摘要： A semiconductor device may include a semiconductor substrate having an active region on a surface thereof. First, second, and third gate lines may cross the active region of the semiconductor substrate, and the first, second, and third gate lines may be arranged in parallel across the active region, and the second gate line may be between the first and third gate lines. A first insulating layer may fill a space between the first and second gate lines on the active region, and the first insulating layer may be a layer of a first insulating material. First insulating spacers may be provided on opposing sidewalls of the third gate line and on a sidewall of the second gate line adjacent to the third gate line, and the first insulating spacers may be spacers of the first insulating material. Second insulating spacers may be provided on sidewalls of the first insulating spacers so that the first insulating spacers are between the second insulating spacers and sidewalls of the second and third gate lines. Moreover, the second insulating spacers may be spacers of a second insulating material different than the first insulating material. Related methods are also discussed.
摘要翻译：半导体器件可以包括在其表面上具有有源区的半导体衬底。第一，第二和第三栅极线可以跨越半导体衬底的有源区，并且第一，第二和第三栅极线可以跨越有源区域并联布置，并且第二栅极线可以在第一和第三栅极线之间门线。第一绝缘层可以填充有源区上的第一和第二栅极线之间的空间，并且第一绝缘层可以是第一绝缘材料层。可以在第三栅极线的相对的侧壁和与第三栅极线相邻的第二栅极线的侧壁上设置第一绝缘间隔物，并且第一绝缘间隔物可以是第一绝缘材料的间隔物。第二绝缘间隔物可以设置在第一绝缘间隔物的侧壁上，使得第一绝缘隔离物位于第二绝缘间隔物和第二和第三栅极线的侧壁之间。此外，第二绝缘间隔物可以是与第一绝缘材料不同的第二绝缘材料的间隔物。还讨论了相关方法。

7. 发明申请

US20050009332A1 Integrated circuit devices having a resistor pattern and plug pattern that are made from a same material and methods of forming the same 有权
标题翻译：具有由相同材料制成的电阻器图案和插头图案的集成电路器件及其形成方法
公开(公告)号：US20050009332A1
公开(公告)日：2005-01-13
申请号：US10880919
申请日：2004-06-30
申请人： Sung-Bok Lee , Hong-Soo Kim , Han-Soo Kim
发明人： Sung-Bok Lee , Hong-Soo Kim , Han-Soo Kim
IPC分类号： H01L21/70 , H01L21/8247 , H01L27/00 , H01L27/08 , H01L27/105 , H01L31/113
CPC分类号： H01L27/0629 , H01L27/0802 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L27/11531 , H01L28/20
摘要： An integrated circuit device is formed by forming a resistor pattern on a substrate. An interlayer dielectric layer is formed on the resistor pattern. The interlayer dielectric layer is patterned to form at least one opening that exposes the resistor pattern. A plug pattern is formed that fills the at least one opening and the plug pattern and resistor pattern are formed using a same material.
摘要翻译：通过在基板上形成电阻图案形成集成电路器件。在电阻图案上形成层间电介质层。图案化层间电介质层以形成暴露电阻器图案的至少一个开口。形成填充至少一个开口的插头图案，并且使用相同的材料形成插头图案和电阻器图案。

8. 发明授权

US08878253B2 Semiconductor devices 有权
标题翻译：半导体器件
公开(公告)号：US08878253B2
公开(公告)日：2014-11-04
申请号：US13099482
申请日：2011-05-03
申请人： Hong-Soo Kim , Hwa-Kyung Shin , Moo-Kyung Lee , Jong-Ho Lim
发明人： Hong-Soo Kim , Hwa-Kyung Shin , Moo-Kyung Lee , Jong-Ho Lim
IPC分类号： H01L27/118 , H01L27/115 , H01L21/28 , H01L29/788 , H01L29/423
CPC分类号： H01L29/42324 , H01L21/28273 , H01L27/11526 , H01L27/11546 , H01L29/7881
摘要： A semiconductor device and method of manufacturing a semiconductor device include a plurality of first active regions and a second active region being formed on a substrate. The second active region is formed between two of the first active regions. A plurality of gate structures is formed on respective first active regions. A dummy gate structure is formed on the second active region, and a first voltage is applied to the dummy gate structure.
摘要翻译：半导体器件和半导体器件的制造方法包括在衬底上形成的多个第一有源区和第二有源区。第二有源区形成在两个第一有源区之间。在相应的第一有源区上形成多个栅极结构。在第二有源区上形成虚拟栅极结构，并将第一电压施加到虚拟栅极结构。

9. 发明授权

US07508048B2 Methods of fabricating a semiconductor device having multi-gate insulation layers and semiconductor devices fabricated thereby 有权
标题翻译：制造具有多栅极绝缘层的半导体器件和由此制造的半导体器件的方法
公开(公告)号：US07508048B2
公开(公告)日：2009-03-24
申请号：US10758802
申请日：2004-01-15
申请人： Dae-Woong Kang , Hong-Soo Kim , Jung-Dal Choi , Kyu-Charn Park , Seong-Soon Cho , Yong-Sik Yim , Sung-Nam Chang
发明人： Dae-Woong Kang , Hong-Soo Kim , Jung-Dal Choi , Kyu-Charn Park , Seong-Soon Cho , Yong-Sik Yim , Sung-Nam Chang
IPC分类号： H01L29/00
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11526 , H01L27/11543
摘要： Methods of fabricating a semiconductor device having multi-gate insulation layers and semiconductor devices fabricated thereby are provided. The method includes forming a pad insulation layer and an initial high voltage gate insulation layer on a first region and a second region of a semiconductor substrate respectively. The initial high voltage gate insulation layer is formed to be thicker than the pad insulation layer. A first isolation layer that penetrates the pad insulation layer and is buried in the semiconductor substrate is formed to define a first active region in the first region, and a second isolation layer that penetrates the initial high voltage gate insulation layer and is buried in the semiconductor substrate is formed to define a second active region in the second region. The pad insulation layer is then removed to expose the first active region. A low voltage gate insulation layer is formed on the exposed first active region. Accordingly, it can minimize a depth of recessed regions (dent regions) to be formed at edge regions of the first isolation layer during removal of the pad insulation layer, and it can prevent dent regions from being formed at edge regions of the second isolation layer.
摘要翻译：提供了制造具有多栅极绝缘层的半导体器件和由此制造的半导体器件的方法。该方法包括分别在半导体衬底的第一区域和第二区域上形成衬垫绝缘层和初始高电压栅极绝缘层。初始高压栅绝缘层形成为比焊垫绝缘层厚。形成穿过焊盘绝缘层并被埋在半导体衬底中的第一隔离层，以限定第一区域中的第一有源区和穿过初始高电压栅极绝缘层并被埋在半导体中的第二隔离层形成衬底以限定第二区域中的第二有源区。然后去除焊盘绝缘层以露出第一有源区。在暴露的第一有源区上形成低压栅极绝缘层。因此，能够最大限度地减少在去除焊盘绝缘层期间在第一隔离层的边缘区域形成的凹陷区域（凹陷区域）的深度，并且可以防止凹陷区域形成在第二隔离层的边缘区域。

10. 发明申请

US20070114591A1 Integrated circuit devices having a resistor pattern and plug pattern that are made from a same material 审中-公开
标题翻译：具有由相同材料制成的电阻器图案和插头图案的集成电路器件
公开(公告)号：US20070114591A1
公开(公告)日：2007-05-24
申请号：US11654114
申请日：2007-01-17
申请人： Sung-Bok Lee , Hong-Soo Kim , Han-Soo Kim
发明人： Sung-Bok Lee , Hong-Soo Kim , Han-Soo Kim
IPC分类号： H01L29/788
CPC分类号： H01L27/0629 , H01L27/0802 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L27/11531 , H01L28/20
摘要： An integrated circuit device is formed by forming a resistor pattern on a substrate. An interlayer dielectric layer is formed on the resistor pattern. The interlayer dielectric layer is patterned to form at least one opening that exposes the resistor pattern. A plug pattern is formed that fills the at least one opening and the plug pattern and resistor pattern are formed using a same material.
摘要翻译：通过在基板上形成电阻图案形成集成电路器件。在电阻图案上形成层间电介质层。图案化层间电介质层以形成暴露电阻器图案的至少一个开口。形成填充至少一个开口的插头图案，并且使用相同的材料形成插头图案和电阻器图案。

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