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1. 发明授权

US5792680A Method of forming a low cost DRAM cell with self aligned twin tub CMOS devices and a pillar shaped capacitor 失效
标题翻译：用自对准双槽CMOS器件和柱状电容器形成低成本DRAM单元的方法
公开(公告)号：US5792680A
公开(公告)日：1998-08-11
申请号：US756129
申请日：1996-11-25
申请人： Janmye Sung , Chih-Yuan Lu , Howard Clayton Kirsch
发明人： Janmye Sung , Chih-Yuan Lu , Howard Clayton Kirsch
IPC分类号： H01L21/8239 , H01L21/8242 , H01L27/108 , H01L21/8238
CPC分类号： H01L27/10852 , H01L27/1052 , H01L27/10817
摘要： The invention is a method of forming a reduced cost DRAM. The process has two embodiments for forming twin wells and two embodiments for forming pillar shaped capacitor electrodes. The twin well embodiments are simple low cost processes. The embodiments for forming the electrode pillars begin by forming a tungsten silicide conductive layer on a first planarization layer. For the first embodiment, the pillars are formed using a photolithography mask with a pattern of spaced transparent areas. The dimensions of the spaced transparent areas and distances between the spaced transparent areas are smaller that the resolution of the lithographic tool. Spaced oxide islands are formed with the mask and are used as an etch mask to form spaced pillars from the conductive layer. This first embodiment for fabricating the multiple pillar capacitor forms pillars of a smaller dimension than the resolution of the photolithography tool. The second embodiment for forming the pillars involves using small titanium silicide islands as an etch mask to define the pillars.
摘要翻译：本发明是一种形成降低成本的DRAM的方法。该方法具有用于形成双阱的两个实施例和用于形成柱状电容器电极的两个实施例。双阱实施例是简单的低成本处理。用于形成电极柱的实施例开始于在第一平坦化层上形成硅化钨导电层。对于第一实施例，使用具有间隔透明区域的图案的光刻掩模形成柱。间隔透明区域的尺寸和间隔开的透明区域之间的距离小于光刻工具的分辨率。用掩模形成间隔氧化物岛，并用作蚀刻掩模以与导电层形成间隔的柱。用于制造多支柱电容器的第一实施例形成比光刻工具的分辨率小的尺寸的柱。用于形成柱的第二实施例涉及使用小的硅化钛岛作为蚀刻掩模来限定柱。

2. 发明授权

US5679589A FET with gate spacer 失效
标题翻译： FET带栅极间隔
公开(公告)号：US5679589A
公开(公告)日：1997-10-21
申请号：US866942
申请日：1992-04-03
申请人： Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
发明人： Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
IPC分类号： H01L21/265 , H01L21/336 , H01L29/78 , H01L21/28
CPC分类号： H01L29/66575 , H01L29/6656 , H01L29/6659 , H01L29/78
摘要： A semiconductor integrated circuit structure and method of fabrication is disclosed. The structure includes a FET gate with adjacent double or triple layered gate spacers. The spacers permit precise tailoring of lightly doped drain junction profiles having deep and shallow junction portions. In addition, a self-aligned silicide may be formed solely over the deep junction portion thus producing a reliable low contact resistance connection to source and drain.
摘要翻译：公开了一种半导体集成电路结构及其制造方法。该结构包括具有相邻的双层或三层栅极间隔物的FET栅极。间隔物允许精细地定制具有深浅接合部分的轻掺杂漏极结型材。此外，自对准硅化物可以仅形成在深结部分上方，从而产生与源极和漏极的可靠的低接触电阻连接。

3. 发明授权

US5153145A FET with gate spacer 失效
标题翻译：带栅极间隔的FET
公开(公告)号：US5153145A
公开(公告)日：1992-10-06
申请号：US422834
申请日：1989-10-17
申请人： Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
发明人： Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
IPC分类号： H01L21/265 , H01L21/336 , H01L29/78
CPC分类号： H01L29/66575 , H01L29/6656 , H01L29/6659 , H01L29/78
摘要： A semiconductor integrated circuit structure and method of fabrication is disclosed. The structure includes a FET gate with adajcent double or triple-layered gate spacers. The spacers permit precise tailoring of lightly doped drain junction profiles having deep and shallow junction portions. In addition, a self-aligned silicide may be formed solely over the deep junction portion thus producing a reliable low contact resistance connection to source and drain.

4. 发明授权

US5943581A Method of fabricating a buried reservoir capacitor structure for high-density dynamic random access memory (DRAM) circuits 失效
标题翻译：制造用于高密度动态随机存取存储器（DRAM）电路的埋藏式电容器结构的方法
公开(公告)号：US5943581A
公开(公告)日：1999-08-24
申请号：US964808
申请日：1997-11-05
申请人： Chih-Yuan Lu , Janmye Sung
发明人： Chih-Yuan Lu , Janmye Sung
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/70
CPC分类号： H01L27/10858 , H01L27/10832
摘要： An improved DRAM cell using a novel buried reservoir capacitor is achieved. The method forms an array of N.sup.+ doped regions in a substrate. P-wells are formed in an epitaxy layer on the substrate. A field oxide (FOX) is formed surrounding the device areas aligned over the N.sup.+ regions. Holes are etched in the epi layer to the N.sup.+ regions, and a selective wet etch removes the N.sup.+ doped regions to form cavities. A thin dielectric layer is deposited on the cavity walls, and an N.sup.+ polysilicon layer is deposited and polished back to form the buried reservoir capacitors. The N.sup.+ polysilicon in the holes forms the capacitor node contacts for the FETs in the device areas. The array of DRAM cells is completed by growing a gate oxide, depositing and patterning a first polycide layer to form FET gate electrodes on the device areas over the capacitors, thereby providing increased capacitance while reducing the cell area. Lightly doped source/drain (LDD) areas, sidewall spacers and heavily doped source/drain contacts are formed for the FETs. A node strap is formed between one source/drain contact and the node contact to make good electrical contact. An insulating layer is deposited having bit line contact holes, and a second polycide layer is patterned to form the bit lines for the DRAM.
摘要翻译：实现了使用新颖的埋藏式电容器的改进的DRAM单元。该方法在衬底中形成N +掺杂区域的阵列。在衬底上的外延层中形成P阱。围绕在N +区域上排列的器件区域周围形成场氧化物（FOX）。将孔在外延层中蚀刻到N +区，并且选择性湿蚀刻去除N +掺杂区以形成空穴。在空腔壁上沉积薄的电介质层，并且沉积并抛光N +多晶硅层以形成埋藏的储存电容器。孔中的N +多晶硅形成器件区域中的FET的电容器节点接触。通过生长栅极氧化物，沉积和图案化第一多晶硅层以在电容器上的器件区域上形成FET栅电极来完成DRAM单元的阵列，从而在减小电池面积的同时提供增加的电容。形成用于FET的轻掺杂源极/漏极（LDD）区域，侧壁间隔物和重掺杂源极/漏极接触。节点带形成在一个源极/漏极接触点和节点接触点之间以形成良好的电接触。沉积具有位线接触孔的绝缘层，并且图案化第二多晶硅化物层以形成用于DRAM的位线。

5. 发明授权

US5002898A Integrated-circuit device isolation 失效
标题翻译：集成电路器件隔离
公开(公告)号：US5002898A
公开(公告)日：1991-03-26
申请号：US423992
申请日：1989-10-19
申请人： Larry B. Fritzinger , Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
发明人： Larry B. Fritzinger , Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
IPC分类号： H01L21/76 , H01L21/316 , H01L21/32 , H01L21/762
CPC分类号： H01L21/32 , H01L21/76202
摘要： In the manufacture of integrated-circuit semiconductor devices, prior to formation of a field oxide, a mask structure is provided on a silicon device area, comprising a pad oxide layer, a polysilicon buffer layer, a protective oxide layer, and a silicon nitride mask layer. Inclusion of the protective layer between polysilicon and silicon nitride layers prevents pad oxide failure and attendant substrate etching during strip-etching of the structure overlying the pad oxide.

6. 发明授权

US4999317A Metallization processing 失效
标题翻译：金属化处理
公开(公告)号：US4999317A
公开(公告)日：1991-03-12
申请号：US414888
申请日：1989-09-29
申请人： Chih-Yuan Lu , Janmye Sung , Yiu M. Wong
发明人： Chih-Yuan Lu , Janmye Sung , Yiu M. Wong
IPC分类号： H01L21/28 , H01L21/285 , H01L23/482
CPC分类号： H01L23/4824 , H01L2924/0002
摘要： When forming a metallization layer in integrated-circuit semiconductor device fabrication, metal such as tungsten, for example, adheres poorly to a dielectric such as, e.g., silicon oxide, and tends to flake off from wafer areas not covered by a glue layer. Processing of the invention prevents such flaking by, first, removing the dielectric from the back side, edge, and "clip-mark" areas of the wafer and, second, depositing a glue layer on remaining dielectric on the face of the wafer. Removal of dielectric material is by etching in the presence of a protective layer on the face of the wafer.

7. 发明授权

US4935376A Making silicide gate level runners 失效
标题翻译：制作硅化物浇口水平赛跑者
公开(公告)号：US4935376A
公开(公告)日：1990-06-19
申请号：US420207
申请日：1989-10-12
申请人： Steven J. Hillenius , Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
发明人： Steven J. Hillenius , Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
IPC分类号： H01L29/78 , H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/768
CPC分类号： H01L21/76889 , H01L21/28052 , H01L21/28123
摘要： Integrated circuits are fabricated with thick self-aligned silicide runners on the field oxide by etching back the first dielectric to expose patterned polysilicon on the field oxide and then forming a silicide on the patterned polysilicon.

8. 发明授权

US6137130A Capacitor over bit line structure using a straight bit line shape 有权
标题翻译：使用直线形状的位线结构电容器
公开(公告)号：US6137130A
公开(公告)日：2000-10-24
申请号：US455357
申请日：1999-12-06
申请人： Janmye Sung
发明人： Janmye Sung
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852
摘要： A method of creating a capacitor over bit line structure, used for high density, DRAM designs, has been developed. The process consists of creating a straight bit line shape, connected to an underlying polysilicon contact plug structure, which in turn contacts an underlying source and drain region. A storage node contact hole is opened through insulator layers and through the straight bit line shape. After passivation of the storage node contact hole with silicon nitride spacers, a storage node structure is formed on an overlying insulator layer, as well as in the storage node contact hole, overlying and contacting another polysilicon contact plug.
摘要翻译：已经开发了用于高密度DRAM设计的位线结构上产生电容器的方法。该过程包括产生直的位线形状，连接到下面的多晶硅接触插塞结构，其又接触下面的源极和漏极区域。存储节点接触孔通过绝缘体层和直的位线形状打开。在用氮化硅间隔物钝化存储节点接触孔之后，在覆盖的绝缘体层以及存储节点接触孔中形成存储节点结构，覆盖并接触另一个多晶硅接触插塞。

9. 发明授权

US6136643A Method for fabricating capacitor-over-bit-line dynamic random access memory (DRAM) using self-aligned contact etching technology 有权
标题翻译：使用自对准接触蚀刻技术制造电容器 - 位线动态随机存取存储器（DRAM）的方法
公开(公告)号：US6136643A
公开(公告)日：2000-10-24
申请号：US248727
申请日：1999-02-11
申请人： Erik S. Jeng , Chun-Yao Chen , Ing-Ruey Liaw , Janmye Sung
发明人： Erik S. Jeng , Chun-Yao Chen , Ing-Ruey Liaw , Janmye Sung
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/10888 , H01L28/91
摘要： A method for making capacitor-over-bit line (COB) DRAM using a self-aligned contact etching technology is achieved. After forming FET gate electrodes, sidewall spacers are formed from a first Si.sub.3 N.sub.4 etch-stop layer, while a portion of the Si.sub.3 N.sub.4 is retained as an etch-stop layer on the source/drain areas. Self-aligned contact openings are etched in a first oxide layer to the source/drain areas, and polysilicon landing plugs are formed in all the self-aligned openings. A second oxide layer is deposited and contact holes are etched to the landing plugs for bit lines. A polycide layer having a cap layer is deposited and patterned to form bit lines. A third Si.sub.3 N.sub.4 etch-stop layer is conformally deposited over the bit lines and patterned to form openings over the landing plugs for the capacitor node contacts while forming Si.sub.3 N.sub.4 sidewall spacers on the bit lines exposed in the openings. A third oxide layer is deposited, and openings having relaxed alignment tolerances, can be etched to the capacitor node contacts because the underlying third etch-stop layer prevents overetching. A conducting layer is deposited and etched back to form bottom electrodes in the openings, and the third oxide layer is removed, while the Si.sub.3 N.sub.4 etch-stop layers prevents over-etching. An interelectrode dielectric layer is deposited, and capacitor top electrodes are formed.
摘要翻译：实现了使用自对准接触蚀刻技术制造电容器对位线（COB）DRAM的方法。在形成FET栅电极之后，侧壁间隔物由第一Si 3 N 4蚀刻停止层形成，而一部分Si 3 N 4作为蚀刻停止层保留在源/漏区上。自对准的接触开口在第一氧化物层中蚀刻到源极/漏极区域，并且在所有自对准开口中形成多晶硅着色塞。沉积第二氧化物层，并将接触孔蚀刻到位线的着陆塞。沉积具有盖层的多晶硅化物层并构图以形成位线。第三个Si 3 N 4蚀刻停止层被保形地沉积在位线上并被图案化以在用于电容器节点接触的着陆塞上形成开口，同时在开口中暴露的位线上形成Si 3 N 4侧壁间隔物。沉积第三氧化物层，并且具有松弛的取向公差的开口可被蚀刻到电容器节点接点，因为下面的第三蚀刻停止层防止过蚀刻。导电层被沉积并回蚀刻以在开口中形成底部电极，并且去除第三氧化物层，而Si 3 N 4蚀刻停止层防止过蚀刻。沉积电极间电介质层，形成电容器顶部电极。

10. 发明授权

US5656510A Method for manufacturing gate oxide capacitors including wafer backside dielectric and implantation electron flood gun current control 失效
标题翻译：制造栅极氧化物电容器的方法，包括晶片背面电介质和注入电子喷枪电流控制
公开(公告)号：US5656510A
公开(公告)日：1997-08-12
申请号：US344318
申请日：1994-11-22
申请人： Terry Chrapacz , Kenneth Gordon Moerschel , William A. Possanza , Michael Allen Prozonic , Janmye Sung
发明人： Terry Chrapacz , Kenneth Gordon Moerschel , William A. Possanza , Michael Allen Prozonic , Janmye Sung
IPC分类号： H01L21/265 , H01L21/28 , H01L21/318 , H01L21/322 , H01L23/60
CPC分类号： H01L23/60 , H01L21/28035 , H01L2924/0002 , Y10S438/928
摘要： A method is provided for optimizing the manufacturing yield of semiconductors. The method provides a backside dielectric layer which protects the semiconductor from electro-static discharge damage during manufacturing. The backside dielectric layer may be a nitride. The backside dielectric layer may be an oxide. The method also provides for optimized ion implantation flood gun current control.
摘要翻译：提供了一种优化半导体制造产量的方法。该方法提供了在制造期间保护半导体免受静电放电损坏的背面电介质层。背面电介质层可以是氮化物。背面电介质层可以是氧化物。该方法还提供优化的离子注入洪水枪电流控制。

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