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1. 发明授权

US06372653B1 Method of forming dual damascene structure 有权
标题翻译：形成双镶嵌结构的方法
公开(公告)号：US06372653B1
公开(公告)日：2002-04-16
申请号：US09611563
申请日：2000-07-07
申请人： Chine-Gie Lou , Su-Yuan Chang
发明人： Chine-Gie Lou , Su-Yuan Chang
IPC分类号： H01L213065
CPC分类号： H01L21/76829 , H01L21/76811 , H01L21/76813 , H01L21/7688
摘要： A method of forming a dual damascene structure. A first organic low dielectric constant dielectric layer, a heat diffusion layer and a second organic low dielectric constant dielectric layer are formed sequentially over a substrate. A first mask layer having a via opening pattern and a second mask layer having a trench pattern are formed sequentially over the second organic. The second organic low dielectric constant dielectric layer exposed by the via opening pattern is etched using the first mask layer as a hard mask layer. The heat diffusion layer exposed by the first mask layer and the via opening in the trench region are removed using the second mask layer and the second organic low dielectric constant dielectric layer as masks. Hence, the trench pattern and the via opening pattern are transferred to the first mask layer and the heat diffusion layer, respectively. The second and the first organic low dielectric constant dielectric layer are etched using the second mask layer and the heat diffusion layer as a hard mask. Ultimately, the trench and via opening of a dual damascene structure are formed.
摘要翻译：形成双镶嵌结构的方法。在衬底上依次形成第一有机低介电常数介电层，热扩散层和第二有机低介电常数介质层。在第二有机物上依次形成具有通孔开口图案的第一掩模层和具有沟槽图案的第二掩模层。使用第一掩模层作为硬掩模层来蚀刻由通孔图案曝光的第二有机低介电常数介电层。使用第二掩模层和第二有机低介电常数介电层作为掩模去除由沟槽区域中的第一掩模层和通孔开口暴露的热扩散层。因此，沟槽图案和通孔开口图案分别转移到第一掩模层和热扩散层。使用第二掩模层和热扩散层作为硬掩模蚀刻第二和第一有机低介电常数介电层。最终，形成双镶嵌结构的沟槽和通孔开口。

2. 发明授权

US07195982B2 Method for manufacturing anti-punch through semiconductor device 有权
标题翻译：制造抗冲穿半导体器件的方法
公开(公告)号：US07195982B2
公开(公告)日：2007-03-27
申请号：US10908379
申请日：2005-05-10
申请人： Min-San Huang , Rex Young , Su-Yuan Chang
发明人： Min-San Huang , Rex Young , Su-Yuan Chang
IPC分类号： H01L21/336
CPC分类号： H01L29/66621 , H01L27/0214 , H01L27/0921 , H01L27/10829 , H01L27/10861 , H01L29/1083 , H01L29/66181 , H01L29/78
摘要： A method for manufacturing an anti-punch through semiconductor device is described. The method is applied to a substrate having a plurality of device isolation structures in parallel arrangements and the upper surface of the device isolation structures is protruded from the surface of the substrate. A plurality of conductive layers in parallel arrangement is formed on the substrate and crosses the device isolation structures. A plurality of trench devices is formed between device isolation structures under the conductive layers. Each trench device includes a first conductive doping region at the bottom of the trench. The method further includes forming spacers on the sidewalls of the device isolation structures and the conductive layers. A dopant implant process is then performed by using the spacers as a mask to form a second conductive doping region between adjacent first conductive doping regions.
摘要翻译：描述了用于制造抗穿通半导体器件的方法。该方法应用于具有多个平行布置的器件隔离结构的衬底，并且器件隔离结构的上表面从衬底的表面突出。多个平行布置的导电层形成在衬底上并穿过器件隔离结构。在导电层之下的器件隔离结构之间形成多个沟槽器件。每个沟槽器件包括在沟槽底部的第一导电掺杂区域。该方法还包括在器件隔离结构和导电层的侧壁上形成间隔物。然后通过使用间隔物作为掩模来执行掺杂剂注入工艺，以在相邻的第一导电掺杂区域之间形成第二导电掺杂区域。

3. 发明申请

US20060216915A1 METHOD FOR FORMING BURIED DOPED REGION 有权
标题翻译：形成钻孔区域的方法
公开(公告)号：US20060216915A1
公开(公告)日：2006-09-28
申请号：US11163728
申请日：2005-10-28
申请人： Chiu-Tsung Huang , Su-Yuan Chang
发明人： Chiu-Tsung Huang , Su-Yuan Chang
IPC分类号： H01L21/425
CPC分类号： H01L21/74 , H01L21/26513
摘要： A method for forming a buried doped region is provided. A first insulating layer is formed on a substrate and the first insulating layer is patterned to from an opening that extends in a first direction. A buried doped region is formed in the substrate exposed by the opening. Thereafter, a second insulating layer is formed on the substrate to fill the opening. The second insulating layer together with the first insulation layer form a third insulating layer. The third insulating layer is patterned to form an isolation layer that exposes the substrate and the buried doped region. The isolation layer extends in a second direction and crosses over the first direction. A semiconductor layer is formed on the substrate to fill the areas on the respective sides of the isolation layer.
摘要翻译：提供一种形成掩埋掺杂区域的方法。第一绝缘层形成在基板上，并且第一绝缘层从沿第一方向延伸的开口图案化。在由开口暴露的衬底中形成掩埋掺杂区域。此后，在基板上形成第二绝缘层以填充开口。第二绝缘层与第一绝缘层一起形成第三绝缘层。将第三绝缘层图案化以形成暴露衬底和掩埋掺杂区域的隔离层。隔离层在第二方向上延伸并跨过第一方向。在衬底上形成半导体层以填充隔离层的相应侧面上的区域。

4. 发明申请

US20060189074A1 STRUCTURE CONTAINING SELF-ALIGNED CONDUCTIVE LINES AND FABRICATING METHOD THEREOF 审中-公开
标题翻译：包含自对准导线的结构及其制造方法
公开(公告)号：US20060189074A1
公开(公告)日：2006-08-24
申请号：US11162077
申请日：2005-08-29
申请人： Hann-Jye Hsu , Su-Yuan Chang , Min-San Huang
发明人： Hann-Jye Hsu , Su-Yuan Chang , Min-San Huang
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L27/115 , H01L27/11556
摘要： A method for fabricating self-aligned conductive lines is provided. A substrate with a plurality of isolation structures is provided. The isolation structures are protrusive from the surface of the substrate, and an active region is defined between two adjacent isolation structures. A plurality of semiconductor devices is formed in the active region. A conductive material layer is then formed on the substrate. Thereafter, a portion of the conductive material layer is removed by using the isolation structures as a removing-stop layer until the surfaces of the isolation structures are exposed and a plurality of conductive lines are formed in a self-aligned manner to electrically connect devices. As the size of the devices is scaled down, the design rule of the lithography process does not limit the size of self-aligned conductive lines. Consequently, the fabricated conductive lines are capable of effectively connecting the semiconductor devices.
摘要翻译：提供一种制造自对准导电线的方法。提供具有多个隔离结构的基板。隔离结构从衬底的表面突出，并且在两个相邻隔离结构之间限定有源区。在有源区域中形成多个半导体器件。然后在衬底上形成导电材料层。此后，通过使用隔离结构作为去除阻挡层去除导电材料层的一部分，直到隔离结构的表面露出，并且以自对准的方式形成多个导电线以电连接器件。随着器件的尺寸缩小，光刻工艺的设计规则并不限制自对准导电线的尺寸。因此，制造的导线能够有效地连接半导体器件。

5. 发明申请

US20060102948A1 METHOD OF FABRICATING FLASH MEMORY 审中-公开
标题翻译：制作闪速存储器的方法
公开(公告)号：US20060102948A1
公开(公告)日：2006-05-18
申请号：US11160326
申请日：2005-06-20
申请人： Ko-Hsing Chang , Su-Yuan Chang
发明人： Ko-Hsing Chang , Su-Yuan Chang
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11521
摘要： A method of fabricating a flash memory is provided. The method includes forming a mask layer with first openings on the substrate. A tunneling dielectric layer is formed at bottom in the first openings. Strips of conductive spacers are formed on sidewalls of the first openings, and source/drain regions are formed in the substrate within the first openings. The strips of conductive spacers are patterned to form floating gates. A first inter-gate dielectric layer is formed over the substrate. Control gates are formed on the substrate to fill the first openings. Mask layer is removed to form second openings. Gate dielectric layer is formed at bottom of second openings, and second inter-gate dielectric layer is formed on the sidewalls of floating gates, and the sidewalls and top surface of the control gates. Word lines are formed to fill second openings disposed between the floating gates and cover the control gates.
摘要翻译：提供一种制造闪速存储器的方法。该方法包括在基板上形成具有第一开口的掩模层。隧道电介质层形成在第一开口的底部。导电间隔物条形成在第一开口的侧壁上，并且源/漏区形成在第一开口内的基板中。将导电间隔物的条带图案化以形成浮栅。在衬底上形成第一栅极间电介质层。在基板上形成控制栅极以填充第一开口。去除掩模层以形成第二开口。栅介电层形成在第二开口的底部，第二栅极间电介质层形成在浮动栅极的侧壁以及控制栅极的侧壁和顶表面上。字线被形成以填充设置在浮动栅极之间并覆盖控制栅极的第二开口。

6. 发明授权

US07550372B2 Method of fabricating conductive lines with silicide layer 有权
标题翻译：用硅化物层制作导线的方法
公开(公告)号：US07550372B2
公开(公告)日：2009-06-23
申请号：US11162115
申请日：2005-08-29
申请人： Su-Yuan Chang , Min-San Huang , Hann-Jye Hsu
发明人： Su-Yuan Chang , Min-San Huang , Hann-Jye Hsu
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/461
CPC分类号： H01L21/76838 , H01L21/76889
摘要： A method of fabricating conductive lines is described. A substrate having a polysilicon layer thereon is provided. A mask layer having an opening that exposes the polysilicon layer is formed on the polysilicon layer. Then, spacers are formed on the sidewalls of the mask layer. Using the mask layer and the spacers as a mask, a portion of the polysilicon layer is removed until the substrate is exposed. After that, an insulating layer that completely fills the opening is formed over the substrate. The insulating layer has an etching selectivity different from the mask layer. Thereafter, the mask layer is removed to expose the polysilicon layer and then a metal silicide layer is formed on the upper surface of the polysilicon layer.
摘要翻译：描述制造导线的方法。提供其上具有多晶硅层的基板。在多晶硅层上形成具有露出多晶硅层的开口的掩模层。然后，在掩模层的侧壁上形成间隔物。使用掩模层和间隔物作为掩模，去除多晶硅层的一部分直到基板被暴露。之后，在基板上形成完全填充开口的绝缘层。绝缘层具有与掩模层不同的蚀刻选择性。此后，除去掩模层以露出多晶硅层，然后在多晶硅层的上表面上形成金属硅化物层。

7. 发明申请

US20080035981A1 ONE TIME PROGRAMMABLE MEMORY AND THE MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：一次性可编程存储器及其制造方法
公开(公告)号：US20080035981A1
公开(公告)日：2008-02-14
申请号：US11309444
申请日：2006-08-08
申请人： Ko-Hsing Chang , Su-Yuan Chang
发明人： Ko-Hsing Chang , Su-Yuan Chang
IPC分类号： H01L29/788 , H01L21/8238
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11556 , H01L29/42336 , H01L29/7881
摘要： A one time programmable memory including a first memory cell is provided. The first memory cell is disposed on a substrate having a trench disposed therein. The first memory cell includes a floating gate, a select gate, a first doped region, a second doped region and a third doped region. The floating gate is disposed on the sidewall of the trench. The select gate is disposed on the substrate outside the trench. The first doped region is disposed in the substrate at the bottom of the trench. The second and third doped regions are disposed in the substrate on both sides of the trench, and the second doped region is disposed between the floating gate and the select gate.
摘要翻译：提供了包括第一存储单元的一次可编程存储器。第一存储单元设置在其中布置有沟槽的衬底上。第一存储单元包括浮置栅极，选择栅极，第一掺杂区域，第二掺杂区域和第三掺杂区域。浮栅设置在沟槽的侧壁上。选择栅极设置在沟槽外部的衬底上。第一掺杂区域设置在沟槽底部的衬底中。第二和第三掺杂区域设置在沟槽两侧的衬底中，并且第二掺杂区域设置在浮置栅极和选择栅极之间。

8. 发明申请

US20070136441A1 Multimedia user interaction over IP network 审中-公开
标题翻译：多媒体用户通过IP网络进行交互
公开(公告)号：US20070136441A1
公开(公告)日：2007-06-14
申请号：US11296454
申请日：2005-12-08
申请人： Su-Yuan Chang , Yin-Ju Chen
发明人： Su-Yuan Chang , Yin-Ju Chen
IPC分类号： G06F15/16
CPC分类号： H04L29/06027 , H04L65/1006
摘要： The present invention is to disclose a multimedia interactive system, which comprising a plurality of multimedia interactive clients, a multimedia interactive server, and a multimedia content server connected to an IP (Internet Protocol) network. Each of said multimedia interactive client further comprising a SIP (Session Initiation Protocol) user agent and a web browser. The multimedia interactive server comprising a SIP proxy server for servicing said SIP user agents of said plurality of multimedia interactive clients. And the multimedia content server provides multimedia content, designated in SIP communication by said multimedia interactive server, to said web browsers of said plurality of multimedia interactive clients.
摘要翻译：本发明是公开一种多媒体交互系统，其包括多个多媒体交互式客户机，多媒体交互式服务器以及连接到IP（因特网协议）网络的多媒体内容服务器。所述多媒体交互式客户端中的每一个还包括SIP（会话发起协议）用户代理和网络浏览器。所述多媒体交互式服务器包括用于服务所述多个多媒体交互式客户端的所述SIP用户代理的SIP代理服务器。并且所述多媒体内容服务器提供由所述多媒体交互服务器在SIP通信中指定的多媒体内容到所述多个多媒体交互式客户端的所述网络浏览器。

9. 发明申请

US20060166497A1 METHOD OF FABRICATING CONDUCTIVE LINES 有权
标题翻译：制导导线的方法
公开(公告)号：US20060166497A1
公开(公告)日：2006-07-27
申请号：US11162115
申请日：2005-08-29
申请人： Su-Yuan Chang , Min-San Huang , Hann-Jye Hsu
发明人： Su-Yuan Chang , Min-San Huang , Hann-Jye Hsu
IPC分类号： H01L21/44
CPC分类号： H01L21/76838 , H01L21/76889
摘要： A method of fabricating conductive lines is described. A substrate having a polysilicon layer thereon is provided. A mask layer having an opening that exposes the polysilicon layer is formed on the polysilicon layer. Then, spacers are formed on the sidewalls of the mask layer. Using the mask layer and the spacers as a mask, a portion of the polysilicon layer is removed until the substrate is exposed. After that, an insulating layer that completely fills the opening is formed over the substrate. The insulating layer has an etching selectivity different from the mask layer. Thereafter, the mask layer is removed to expose the polysilicon layer and then a metal silicide layer is formed on the upper surface of the polysilicon layer.
摘要翻译：描述制造导线的方法。提供其上具有多晶硅层的基板。在多晶硅层上形成具有露出多晶硅层的开口的掩模层。然后，在掩模层的侧壁上形成间隔物。使用掩模层和间隔物作为掩模，去除多晶硅层的一部分直到基板被暴露。之后，在基板上形成完全填充开口的绝缘层。绝缘层具有与掩模层不同的蚀刻选择性。此后，除去掩模层以露出多晶硅层，然后在多晶硅层的上表面上形成金属硅化物层。

10. 发明授权

US07049189B2 Method of fabricating non-volatile memory cell adapted for integration of devices and for multiple read/write operations 失效
标题翻译：制造非易失性存储单元的方法，适用于器件集成和多重读/写操作
公开(公告)号：US07049189B2
公开(公告)日：2006-05-23
申请号：US10708904
申请日：2004-03-31
申请人： Ko-Hsing Chang , Su-Yuan Chang
发明人： Ko-Hsing Chang , Su-Yuan Chang
IPC分类号： H01L21/8238
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/7923
摘要： A method of manufacturing a non-volatile memory cell includes forming a bottom dielectric layer and a charge trapping layer on a substrate sequentially. The electron trapping layer is patterned to form a trench exposing a portion of the bottom dielectric layer. A top dielectric layer is formed over the substrate and covers the electron trapping layer and the exposed bottom dielectric layer. A conductive layer is then formed on the top dielectric layer. The conductive layer, the top dielectric layer, the electron trapping layer and the bottom dielectric layer are patterned to form a stacked structure, wherein a width of the stacked structure is larger than a width of the trench. A source/drain region is formed in the substrate adjacent to the edges of the stacked structure. Because the electron trapping layer of the memory cell is divided into two isolation structures according to the invention, it is adapted for the integration of devices and for long-time operation.
摘要翻译：制造非易失性存储单元的方法包括依次在衬底上形成底部电介质层和电荷俘获层。图案化电子俘获层以形成露出底部电介质层的一部分的沟槽。顶部电介质层形成在衬底上并覆盖电子俘获层和暴露的底部介电层。然后在顶部介电层上形成导电层。将导电层，顶部电介质层，电子俘获层和底部电介质层图案化以形成堆叠结构，其中层叠结构的宽度大于沟槽的宽度。源极/漏极区域形成在与层叠结构的边缘相邻的衬底中。因为根据本发明的存储器单元的电子俘获层被分成两个隔离结构，所以适用于器件的集成和长时间的操作。

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