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1. 发明授权

US06413818B1 Method for forming a contoured floating gate cell 有权
标题翻译：形成轮廓浮动栅极的方法
公开(公告)号：US06413818B1
公开(公告)日：2002-07-02
申请号：US09415936
申请日：1999-10-08
申请人： Chin-Yi Huang , Chih-Jen Huang , Yun Chang , James Hsu , Samuel C. Pan
发明人： Chin-Yi Huang , Chih-Jen Huang , Yun Chang , James Hsu , Samuel C. Pan
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： A floating gate having a first and second end region, each of which are positioned adjacent to a corresponding lateral end of the floating gate. A middle region is positioned laterally towards a middle of the floating gate relative to the first and second end regions. The first end region, the middle region and the second end region are formed of a same material during a single fabrication step, and the middle region formed has a thickness which is less than a thickness of the first or second end regions. This invention further includes a method for forming a contoured floating gate for use in a floating gate memory cell. The method includes forming a polysilicon layer over first and second spaced apart oxide structures and a floating gate region between the first and second oxide structures such that the polysilicon layer formed in the floating gate region has a first end region adjacent the first oxide structure, a second end region adjacent the second oxide structure, and a middle region positioned laterally between the first and second end regions. The method further includes removing a portion of the polysilicon layer in the floating gate region such that the vertical thickness of the first and second end regions remain greater than the vertical thickness of the middle region.
摘要翻译：一种具有第一和第二端区域的浮动栅极，每个都与浮置栅极的相应横向端相邻。中间区域相对于第一和第二端部区域侧向朝向浮动门的中间定位。在单个制造步骤期间，第一端区域，中间区域和第二端部区域由相同的材料形成，并且形成的中间区域的厚度小于第一或第二端部区域的厚度。本发明还包括一种用于形成在浮动栅极存储单元中使用的轮廓浮动栅极的方法。该方法包括在第一和第二间隔开的氧化物结构之上形成多晶硅层和在第一和第二氧化物结构之间的浮栅区域，使得形成在浮动栅极区域中的多晶硅层具有与第一氧化物结构相邻的第一端区域，与第二氧化物结构相邻的第二端区域和位于第一和第二端部区域之间横向定位的中间区域。该方法还包括去除浮动栅极区域中的多晶硅层的一部分，使得第一和第二端部区域的垂直厚度保持大于中间区域的垂直厚度。

2. 发明授权

US06248631B1 Method for forming a v-shaped floating gate 有权
标题翻译：用于形成v形浮动门的方法
公开(公告)号：US06248631B1
公开(公告)日：2001-06-19
申请号：US09415788
申请日：1999-10-08
申请人： Chin-Yi Huang , Yun Chang , Samuel C. Pan
发明人： Chin-Yi Huang , Yun Chang , Samuel C. Pan
IPC分类号： H01L218242
CPC分类号： H01L27/11521 , H01L27/115
摘要： The invention provides a floating gate memory cell, where the floating gate comprises a first lateral end region and a second lateral end region. A middle region is positioned towards a middle of the floating gate with respect to the first lateral end region and the second lateral end region. The thickness of the floating gate decreases continuously from at least one of the first or second lateral end regions to the middle region. This invention also provides for a method of forming a contoured floating gate for use in a floating gate memory cell. The method includes forming a polysilicon structure between a first alignment structure and a second alignment structure, where the polysilicon structure has a maximum thickness at a first lateral end region adjacent to the first alignment structure and at a second lateral end region adjacent to the second alignment structure, and where the polysilicon structure has a minimum thickness at a middle region positioned between the first lateral end regions and the second lateral end region. The method further includes forming a polysilicon layer over the polysilicon structure such that the polysilicon layer adopts a contour of the polysilicon structure.
摘要翻译：本发明提供一种浮动栅极存储单元，其中浮动栅极包括第一侧向端部区域和第二侧向端部区域。中间区域相对于第一横向端部区域和第二横向端部区域朝向浮动栅极的中间定位。浮动栅极的厚度从第一或第二横向端部区域中的至少一个到中间区域连续地减小。本发明还提供了一种形成用于浮动栅极存储单元的轮廓浮动栅极的方法。该方法包括在第一对准结构和第二对准结构之间形成多晶硅结构，其中多晶硅结构在与第一对准结构相邻的第一横向端部区域处具有最大厚度，并且在邻近第二对准结构的第二横向端部区域结构，并且其中多晶硅结构在位于第一侧端部区域和第二侧向端部区域之间的中间区域处具有最小厚度。该方法还包括在多晶硅结构上形成多晶硅层，使得多晶硅层采用多晶硅结构的轮廓。

3. 发明授权

US06177317B1 Method of making nonvolatile memory devices having reduced resistance diffusion regions 有权
标题翻译：制造具有减小的电阻扩散区域的非易失性存储器件的方法
公开(公告)号：US06177317B1
公开(公告)日：2001-01-23
申请号：US09291915
申请日：1999-04-14
申请人： Chin-Yi Huang , Huei Huarng Chen , Yun Chang , Samuel C. Pan
发明人： Chin-Yi Huang , Huei Huarng Chen , Yun Chang , Samuel C. Pan
IPC分类号： H01L218247
CPC分类号： H01L27/11521
摘要： A method is described for manufacturing nonvolatile memory devices having reduced resistance diffusion regions. One embodiment of the method includes forming a multilayer structure over a substrate which includes a tunnel oxide layer, a polysilicon layer, and an etch stop layer. A photoresist masking process is performed on the multilayer structure to define gates of the nonvolatile memory device. A spacer layer is then deposited and etched back to form sidewall spacers adjacent the gates. The width of the sidewall spacers is used to define the width of the source and drain regions, and the width of trenches between the gates. Trenches are formed using a high selectivity etch which etches through the substrate faster than the sidewall spacers and the etch stop layer. A conductive layer is formed over the area of the device and etched to form the reduced resistance diffusion regions and the desired trench configuration. The trenches are then filled with an insulating material.
摘要翻译：描述了一种用于制造具有减小的电阻扩散区域的非易失性存储器件的方法。该方法的一个实施例包括在包括隧道氧化物层，多晶硅层和蚀刻停止层的衬底上形成多层结构。在多层结构上执行光致抗蚀剂掩模处理以限定非易失性存储器件的栅极。然后沉积间隔层并回蚀刻以形成邻近栅极的侧壁间隔物。侧壁间隔物的宽度用于限定源极和漏极区域的宽度以及栅极之间的沟槽的宽度。使用高选择性蚀刻形成沟槽，其蚀刻通过衬底比侧壁间隔物和蚀刻停止层更快。在器件的区域上形成导电层并进行蚀刻以形成减小的电阻扩散区域和所需的沟槽结构。然后用绝缘材料填充沟槽。

4. 发明授权

US06680506B2 Method for forming a flash memory cell having contoured floating gate surface 有权
标题翻译：用于形成具有轮廓浮动栅极表面的闪存单元的方法
公开(公告)号：US06680506B2
公开(公告)日：2004-01-20
申请号：US10231505
申请日：2002-08-30
申请人： Yun Chang , Chin-Yi Huang
发明人： Yun Chang , Chin-Yi Huang
IPC分类号： H01L2976
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： Methods are provided for forming a contoured floating gate for use in a floating gate memory cell. One method includes forming a floating gate that has a polysilicon layer over a substrate; forming oxide layers on opposing sides of the floating gate, the oxide layer having a vertical thickness greater than a vertical thickness of the floating gate; forming a spacer layer over the oxide layers and the floating gate; removing a portion of the spacer layer such that a top surface of the floating gate positioned laterally toward a middle region of the floating gate is exposed; and removing a portion of the floating gate underlying the exposed top surface of the middle region to form the contoured floating gate.
摘要翻译：提供了用于形成用于浮动栅极存储单元的轮廓浮动栅极的方法。一种方法包括形成在衬底上具有多晶硅层的浮置栅极; 在所述浮置栅极的相对侧上形成氧化物层，所述氧化物层具有大于所述浮动栅极的垂直厚度的垂直厚度; 在所述氧化物层和所述浮动栅极上形成间隔层; 去除间隔层的一部分，使得横向朝向浮动栅极的中间区域定位的浮动栅极的顶表面被暴露; 以及移除位于中间区域的暴露顶表面下方的浮动栅极的一部分以形成轮廓浮动栅极。

5. 发明授权

US5836772A Interpoly dielectric process 失效
标题翻译： Interpoly介电过程
公开(公告)号：US5836772A
公开(公告)日：1998-11-17
申请号：US829028
申请日：1997-03-31
申请人： Yun Chang , Fuchia Shone , Chin-Yi Huang , Nai chen Peng
发明人： Yun Chang , Fuchia Shone , Chin-Yi Huang , Nai chen Peng
IPC分类号： H01L21/28 , H01L29/51 , H01L21/8247
CPC分类号： H01L29/518 , H01L21/28273 , H01L29/511
摘要： A process is provided for fabricating a nonvolatile memory cell. According to the process, source and drain regions are formed on a first conductivity-type semiconductor substrate; and insulating layer is formed on the source and drain regions; a floating gate is formed on the insulating layer; a dielectric composite is formed on the floating gate; and a control gate is formed on the dielectric composite. The dielectric composite includes a bottom layer of silicon dioxide formed on the floating gate; a layer of silicon nitride formed on the bottom silicon dioxide layer; and a top layer of silicon dioxide formed on the nitride layer such that the silicon nitride layer of the composite is thinner than the top or the bottom silicon dioxide layer.
摘要翻译：提供了制造非易失性存储单元的过程。根据该工艺，源极和漏极区域形成在第一导电型半导体衬底上; 并且在源区和漏区上形成绝缘层; 在绝缘层上形成浮栅; 在浮动栅极上形成介电复合材料; 并且在电介质复合体上形成控制栅极。介电复合材料包括在浮栅上形成的二氧化硅底层; 形成在底部二氧化硅层上的一层氮化硅; 以及形成在氮化物层上的顶层二氧化硅，使得复合材料的氮化硅层比顶部或底部二氧化硅层薄。

6. 发明授权

US06544844B2 Method for forming a flash memory cell having contoured floating gate surface 有权
标题翻译：用于形成具有轮廓浮动栅极表面的闪存单元的方法
公开(公告)号：US06544844B2
公开(公告)日：2003-04-08
申请号：US09818078
申请日：2001-03-27
申请人： Yun Chang , Chin-Yi Huang
发明人： Yun Chang , Chin-Yi Huang
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： Methods are provided for forming a contoured floating gate for use in a floating gate memory cell. One method includes forming a floating gate that has a polysilicon layer over a substrate, forming oxide layers on opposing sides of the floating gate, the oxide layer having a vertical thickness greater than a vertical thickness of the floating gate; forming a spacer layer over the oxide layers and the floating gate; removing a portion of the spacer layer such that a top surface of the floating gate positioned laterally toward a middle region of the floating gate is exposed; and removing a portion of the floating gate underlying the exposed top surface of the middle region to form the contoured floating gate.
摘要翻译：提供了用于形成用于浮动栅极存储单元的轮廓浮动栅极的方法。一种方法包括形成在衬底上具有多晶硅层的浮置栅极，在浮置栅极的相对侧上形成氧化物层，该氧化物层的垂直厚度大于浮动栅极的垂直厚度; 在所述氧化物层和所述浮动栅极上形成间隔层; 去除间隔层的一部分，使得横向朝向浮动栅极的中间区域定位的浮动栅极的顶表面被暴露; 以及移除位于中间区域的暴露顶表面下方的浮动栅极的一部分以形成轮廓浮动栅极。

7. 发明授权

US06459119B1 Contact array structure for buried type transistor 有权
标题翻译：埋式晶体管的触点阵列结构
公开(公告)号：US06459119B1
公开(公告)日：2002-10-01
申请号：US09436091
申请日：1999-11-08
申请人： Chin-Yi Huang , Yun Chang
发明人： Chin-Yi Huang , Yun Chang
IPC分类号： H01L2976
CPC分类号： G11C7/18 , H01L27/115
摘要： Systems and methods are described for providing an array of buried transistor cells with at least one contact array structure. A contact array structure for a buried type transistor array includes a first diffusion bit line coupled to the plurality of transistors; a first plurality of contacts coupled to the source diffusion bit line; and a first conductor coupled to the first plurality of contacts. The systems and methods provide advantages in that the diffusion line resistance is reduced, the read current and speed are reduced, and the voltage-time distribution is tightened when writing by hot electron programming.
摘要翻译：描述了用于提供具有至少一个接触阵列结构的埋入晶体管电池阵列的系统和方法。掩埋型晶体管阵列的接触阵列结构包括耦合到多个晶体管的第一扩散位线; 耦合到源扩散位线的第一多个触点; 以及耦合到所述第一多个触点的第一导体。该系统和方法提供了扩散线电阻降低，读取电流和速度降低以及通过热电子编程写入时的电压 - 时间分布紧缩的优点。

8. 发明授权

US06191000B1 Shallow trench isolation method used in a semiconductor wafer 有权
标题翻译：在半导体晶片中使用的浅沟槽隔离方法
公开(公告)号：US06191000B1
公开(公告)日：2001-02-20
申请号：US09378700
申请日：1999-08-23
申请人： Chin-Yi Huang , Chin-Jen Huang , Chen-Chin Liu , Yun Chang
发明人： Chin-Yi Huang , Chin-Jen Huang , Chen-Chin Liu , Yun Chang
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： The invention relates to a shallow trench isolation method used in a semiconductor wafer that comprises a plurality of predetermined active regions, a plurality of shallow trenches used for electrically isolating the plurality of active regions, and a wafer alignment region wherein at least one recess having a predetermined pattern is formed on the surface of the wafer. In the method of the present invention, an insulation layer is first formed on the surface of the semiconductor wafer to fill the recesses in the wafer alignment region and the plurality of shallow trenches. An etching process is then implemented to reduce the thickness of the insulation layer on the surface of the working region, the working region having a relatively high density of active regions. Also, the insulation layer is completely removed from the recesses within the wafer alignment region. Finally, a chemical mechanical process (CMP) is performed on the surface of the semiconductor wafer to remove the insulation layer and to keep the surface of the insulation layer in the shallow trenches even with the semiconductor wafer.
摘要翻译：本发明涉及一种在半导体晶片中使用的浅沟槽隔离方法，其包括多个预定有源区，用于电隔离多个有源区的多个浅沟槽和晶片对准区域，其中至少一个具有在晶片的表面上形成预定图案。在本发明的方法中，首先在半导体晶片的表面上形成绝缘层，以填充晶片对准区域和多个浅沟槽中的凹槽。然后执行蚀刻工艺以减小工作区域表面上的绝缘层的厚度，工作区域具有较高密度的活性区域。此外，绝缘层完全从晶片对准区域内的凹部移除。最后，在半导体晶片的表面上进行化学机械工艺（CMP）以去除绝缘层，并且即使使用半导体晶片也能将绝缘层的表面保持在浅沟槽中。

9. 发明授权

US07214384B2 Lipid-conjugated polyamide compounds 失效
标题翻译：脂质共轭聚酰胺化合物
公开(公告)号：US07214384B2
公开(公告)日：2007-05-08
申请号：US10445642
申请日：2003-05-27
申请人： Ronald N. Zuckermann , Chin-Yi Huang , John E. Murphy , Tetsuo Uno
发明人： Ronald N. Zuckermann , Chin-Yi Huang , John E. Murphy , Tetsuo Uno
IPC分类号： A61K9/127 , C08K5/20 , C12N15/00 , C07C231/00
CPC分类号： C12N15/87 , A61K47/645
摘要： In accordance with the present invention, there are provided lipid-conjugated polyamide compounds and related compositions and methods thereof. Lipid-conjugated polyamide compounds of the present invention are particularly useful as vehicles for delivering biologically active agents to a target site. In particular, the invention compounds are effective at facilitating the delivery of polynucleotides to cells. The present invention also provides a method for producing stable formulations of polynucleotides complexed with a delivery vehicle.
摘要翻译：根据本发明，提供了脂质共轭聚酰胺化合物及其相关组合物和方法。本发明的脂质偶联的聚酰胺化合物特别可用作将生物活性剂递送到靶位点的载体。特别地，本发明化合物有利于促进将多核苷酸递送至细胞。本发明还提供了用于制备与递送载体复合的多核苷酸的稳定制剂的方法。

10. 发明申请

US20060079459A1 Stabilized compositions comprising tissue factor pathway inhibitor protein or tissue factor pathway inhibitor variant proteins 失效
标题翻译：包含组织因子途径抑制蛋白或组织因子途径抑制剂变体蛋白的稳定组合物
公开(公告)号：US20060079459A1
公开(公告)日：2006-04-13
申请号：US11302208
申请日：2005-12-14
申请人： Bao-Lu Chen , Chin-Yi Huang
发明人： Bao-Lu Chen , Chin-Yi Huang
IPC分类号： A61K38/54
CPC分类号： A61K9/0014 , A61K38/57 , A61K47/12 , A61K47/18 , A61K47/183 , C07K14/8114
摘要： Stabilized aqueous compositions of tissue factor pathway inhibitor (TFPI) or TFPI variants comprise a solubilizing agent, an antioxidant, and a buffer. The combination of a solubilizing agent and an antioxidant can lead to a significant improvement in the storage life of TFPI or TFPI variant compositions. The solubilizing agent and antioxidant substantially counteract the effects of TFPI or TFPI variant degradation through aggregation and oxidation.
摘要翻译：组织因子途径抑制剂（TFPI）或TFPI变体的稳定含水组合物包含增溶剂，抗氧化剂和缓冲液。增溶剂和抗氧化剂的组合可导致TFPI或TFPI变体组合物的储存寿命的显着改善。增溶剂和抗氧化剂通过聚集和氧化基本上抵消了TFPI或TFPI变体降解的作用。

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