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1. 发明授权

US4719531A Overcurrent protective circuit for modulated-conductivity type MOSFET 失效
标题翻译：用于调制导电型MOSFET的过电流保护电路
公开(公告)号：US4719531A
公开(公告)日：1988-01-12
申请号：US863515
申请日：1986-05-15
申请人： Chihiro Okado , Yoshihiro Yamaguchi , Akio Nakagawa
发明人： Chihiro Okado , Yoshihiro Yamaguchi , Akio Nakagawa
IPC分类号： H02H3/38 , H03K17/08 , H03K17/0812 , H03K17/082 , H03K17/567 , H02H3/24
CPC分类号： H03K17/567 , H03K17/08128 , H03K17/0828 , H01L2924/0002
摘要： An overcurrent protective circuit for a modulated conductivity type MOSFET, i.e., a BIFET, which has a voltage detection circuit for detecting a voltage between the drain and source of the BIFET and a main switching circuit for lowering a voltage between the gate ad source of the BIFET and preventing the failure of the BIFET and delay of turn-on of the BIFET according to the output of the voltage detection circuit. The protective circuit produces a constant time delay before the main switching circuit becomes turned on during the initial turn-on period of the BIFET upon application of an ON-gate signal to the gate of the BIFET. The protection circuit thereby prevents, during the initial turn period of the BIFET, a situation where the main switching circuit is turned on but the BIFET is not turned on. The protective circuit further assures that after detection of an overvoltage across the source and drain of the BIFET as may be caused by a load failure, the BIFET gate is maintained at such a low voltage to assure at most a small current conduction through the BIFET even if a ringing voltage occurs across the BIFET.
摘要翻译：用于调制导电型MOSFET的过电流保护电路，即BIFET，其具有用于检测BIFET的漏极和源极之间的电压的电压检测电路和用于降低BIFET的栅极和源极之间的电压的主开关电路 BIFET，根据电压检测电路的输出，防止BIFET的故障和BIFET的导通延迟。在BIFET的初始接通周期中，当主开关电路在向BIFET的栅极施加导通栅极信号时，保护电路产生恒定的时间延迟。因此，保护电路在BIFET的初始转弯期间防止主开关电路接通但BIFET未导通的情况。保护电路进一步确保在BIFET的源极和漏极两端检测到负载故障可能引起的过电压之后，BIFET栅极保持在这样的低电压，以确保至少通过BIFET的小电流传导，甚至如果BIFET发生振铃电压。

2. 发明申请

US20080251838A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20080251838A1
公开(公告)日：2008-10-16
申请号：US12118159
申请日：2008-05-09
申请人： Syotaro Ono , Yoshihiro Yamaguchi , Yusuke Kawaguchi , Kazutoshi Nakamura , Norio Yasuhara , Kenichi Matsushita , Shinichi Hodama , Akio Nakagawa
发明人： Syotaro Ono , Yoshihiro Yamaguchi , Yusuke Kawaguchi , Kazutoshi Nakamura , Norio Yasuhara , Kenichi Matsushita , Shinichi Hodama , Akio Nakagawa
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0653 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/66712 , H01L29/7809
摘要： A semiconductor device includes: a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type; a first main electrode connected to the low-resistance drain layer; a high-resistance epitaxial layer of a second-conductivity type formed on the low-resistance drain layer; a second-conductivity type base layer selectively formed on the high-resistance epitaxial layer; a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer; a trench formed in a region sandwiched by the second-conductivity type base layers with a depth extending from the surface of the high-resistance epitaxial layer to the semiconductor substrate; a jfet layer of the first conductivity type formed on side walls of the trench; an insulating layer formed in the trench; an LDD layer of the first-conductivity type formed in a surface portion of the second-conductivity type base layer so as to be connected to the first-conductivity type jfet layer around a top face of the trench; a control electrode formed above the semiconductor substrate so as to be divided into a plurality of parts, and formed on a gate insulating film formed on a part of the surface of the LDD layer, on surfaces of end parts of the first-conductivity type source layer facing each other across the trench, and on a region of the surface of the second-conductivity type base layer sandwiched by the LDD layer and the first-conductivity type source layer; and a second main electrode in ohmic contact with the first-conductivity type source layer and the second-conductivity type base layer so as to sandwich the control electrode.
摘要翻译：半导体器件包括：半导体衬底，至少其表面部分用作第一导电类型的低电阻漏极层; 连接到所述低电阻漏极层的第一主电极; 形成在低电阻漏极层上的第二导电类型的高电阻外延层; 选择性地形成在高电阻外延层上的第二导电型基极层; 选择性地形成在所述第二导电型基底层的表面部分中的第一导电型源极层; 在由所述第二导电型基底层夹持的区域中形成的沟槽，其深度从所述高电阻外延层的表面延伸到所述半导体衬底; 形成在沟槽的侧壁上的第一导电类型的jfet层; 形成在沟槽中的绝缘层; 形成在第二导电型基底层的表面部分中的第一导电类型的LDD层，以便围绕沟槽的顶面连接到第一导电型jfet层; 控制电极，其形成在所述半导体衬底上，以被分成多个部分，并形成在形成在所述LDD层的一部分表面上的栅极绝缘膜上，所述第一导电型源的端部并且在由LDD层和第一导电型源极层夹在第二导电型基底层的表面的区域上，以及与所述第一导电型源极层和所述第二导电型基极欧姆接触以便夹持所述控制电极的第二主电极。

3. 发明申请

US20080035992A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20080035992A1
公开(公告)日：2008-02-14
申请号：US11836383
申请日：2007-08-09
申请人： Yusuke KAWAGUCHI , Yoshihiro Yamaguchi , Syotaro Ono , Akio Nakagawa , Miwako Akiyama , Kazuya Nakayama , Masakazu Yamaguchi
发明人： Yusuke KAWAGUCHI , Yoshihiro Yamaguchi , Syotaro Ono , Akio Nakagawa , Miwako Akiyama , Kazuya Nakayama , Masakazu Yamaguchi
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L21/2815 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/41766 , H01L29/42356 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/66734 , H01L29/7828
摘要： This semiconductor device comprises a drift layer of a first conductivity type formed on a drain layer of a first conductivity type, and a drain electrode electrically connected to the drain layer. A semiconductor base layer of a second conductivity type is formed in a surface of the drift layer, and a source region of a first conductivity type is further formed in the semiconductor base layer.A source electrode is electrically connected to the source region and a semiconductor base layer. Plural gate electrodes are formed through a gate insulation film so that a semiconductor base layer may be sandwiched by the gate electrodes. The width of the semiconductor base layer sandwiched by the gate electrodes is 0.3 micrometers or less.
摘要翻译：该半导体器件包括形成在第一导电类型的漏极层上的第一导电类型的漂移层和电连接到漏极层的漏电极。在漂移层的表面上形成第二导电类型的半导体基底层，并且在半导体基底层中进一步形成第一导电类型的源极区。源电极电连接到源区和半导体基层。多个栅电极通过栅极绝缘膜形成，使得半导体基底层可以被栅电极夹持。被栅电极夹持的半导体基底层的宽度为0.3微米以下。

4. 发明授权

US07230297B2 Trench-gated MOSFET including schottky diode therein 有权
标题翻译：沟槽栅MOSFET，其中包括肖特基二极管
公开(公告)号：US07230297B2
公开(公告)日：2007-06-12
申请号：US11127224
申请日：2005-05-12
申请人： Syotaro Ono , Akio Nakagawa , Yusuke Kawaguchi , Yoshihiro Yamaguchi
发明人： Syotaro Ono , Akio Nakagawa , Yusuke Kawaguchi , Yoshihiro Yamaguchi
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/1095
摘要： Disclosed is a trench MOSFET, including: a trench gate structure having a gate electrode and a gate insulating film; an n-type diffusion layer formed to face the gate electrode via the gate insulating film at an upper portion of the trench; a p-type base layer formed to face the gate electrode via the gate insulating film at a lower portion than the upper portion; an n-type epitaxial layer locating to face the gate electrode via the gate insulating film at a further lower portion than the lower portion; a metal layer formed departing from the trench in parallel with a depth direction of the trench, penetrating the n-type diffusion layer and the p-type base layer, to reach the n-type epitaxial layer; and a p-type layer with higher impurity concentration than the p-type base layer, locating to be in contact with the p-type base layer and the metal layer.
摘要翻译：公开了一种沟槽MOSFET，其包括：具有栅极电极和栅极绝缘膜的沟槽栅极结构; 形成为在沟槽的上部经由栅极绝缘膜与栅电极对置的n型扩散层; p型基底层，其在比上部更低的一部分处经由栅极绝缘膜形成为面对栅电极; n型外延层，其定位成在比下部更下方的一部分经由栅极绝缘膜面对栅电极; 与沟槽的深度方向平行地形成的穿过n型扩散层和p型基底层的金属层，以到达n型外延层; 以及比p型基底层高的杂质浓度的p型层，与p型基底层和金属层接触。

5. 发明授权

US5780887A Conductivity modulated MOSFET 失效
公开(公告)号：US5780887A
公开(公告)日：1998-07-14
申请号：US261254
申请日：1994-06-14
申请人： Akio Nakagawa , Hiromichi Ohashi , Yoshihiro Yamaguchi , Kiminori Watanabe , Thuneo Thukakoshi
发明人： Akio Nakagawa , Hiromichi Ohashi , Yoshihiro Yamaguchi , Kiminori Watanabe , Thuneo Thukakoshi
IPC分类号： H01L29/06 , H01L29/10 , H01L29/739 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L29/1095 , H01L29/0619 , H01L29/0696 , H01L29/7393 , H01L29/7395
摘要： A conductivity modulated MOSFET, having a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on the semiconductor substrate and having a high resistance, a base layer of the first conductivity type formed in the semiconductor layer, a source layer of the second conductivity type formed in the base layer, a gate electrode formed on a gate insulating film which is formed on a channel region, the channel region being formed in a surface of the base layer between the semiconductor layer and the source layer, a source electrode ohmic-contacting the source layer and the base layer, and a drain electrode formed on the surface of the semiconductor substrate opposite to the semiconductor layer, characterized in that the conductivity modulated MOSFET has a saturation current smaller than a latch-up current when a predetermined gate voltage is applied to the gate electrode.

6. 发明授权

US5463231A Method of operating thyristor with insulated gates 失效
公开(公告)号：US5463231A
公开(公告)日：1995-10-31
申请号：US353385
申请日：1994-12-02
申请人： Tsuneo Ogura , Kiminori Watanabe , Akio Nakagawa , Yoshihiro Yamaguchi , Norio Yasuhara , Tomoko Matsudai , Shigeru Hasegawa , Kazuya Nakayama
发明人： Tsuneo Ogura , Kiminori Watanabe , Akio Nakagawa , Yoshihiro Yamaguchi , Norio Yasuhara , Tomoko Matsudai , Shigeru Hasegawa , Kazuya Nakayama
IPC分类号： H01L27/06 , H01L29/74 , H01L29/745 , H01L29/749 , H01L31/111
CPC分类号： H01L27/0617 , H01L29/7436 , H01L29/7455 , H01L29/749
摘要： A thyristor with insulated gates includes turn-off and turn-on MOSFETs. The turn-on MOSFET has a turn-on gate employing a p-type base as a channel and extending over an n-type base and an n-type emitter. The turn-off MOSFET has n-type drain and source layers formed in a p-type base layer, and a turn-off gate extending over the drain and source layers. The n-type drain layer is short-circuited with the p-type base layer via a drain electrode. The drain electrode is formed near an n-type emitter layer. When the thyristor is to be turned off, the first voltage is applied to the turn-on gate, and the second voltage is applied to the turn-off gate while the first voltage is applied to the turn-on gate. After the application of the second voltage continues for a predetermined period of time, the application of the first voltage to the turn-on gate is stopped. With this operation, the thyristor can be turned off even with a large current.

7. 发明授权

US5124773A Conductivity-modulation metal oxide semiconductor field effect transistor 失效
标题翻译：电导率调制金属氧化物半导体场效应晶体管
公开(公告)号：US5124773A
公开(公告)日：1992-06-23
申请号：US563720
申请日：1990-08-07
申请人： Akio Nakagawa , Yoshihiro Yamaguchi , Kiminori Watanabe
发明人： Akio Nakagawa , Yoshihiro Yamaguchi , Kiminori Watanabe
IPC分类号： H01L29/06 , H01L29/08 , H01L29/40 , H01L29/739 , H01L29/745
CPC分类号： H01L29/405 , H01L29/0696 , H01L29/0834 , H01L29/402 , H01L29/7393 , H01L29/7395 , H01L29/7396 , H01L29/7455
摘要： A conductivity-modulation MOSFET employs a substrate of an N type conductivity as its N base. A first source layer of a heavily-doped N type conductivity is formed in a P base layer formed in the N base. A source electrode electrically conducts the P base and the source. A first gate electrode insulatively covers a channel region defined by the N.sup.+ source layer in the P base. A P drain layer is formed on an opposite substrate surface. An N.sup.+ second source layer is formed in a P type drain layer by diffusion to define a second channel region. A second gate electrode insulatively covers the second channel region, thus providing a voltage-controlled turn-off controlling transistor. A drain electrode of the MOSFET conducts the P type drain and second source. When the turn-off controlling transistor is rendered conductive to turn off the MOSFET a "shorted anode structure" is temporarily formed wherein the N type base is short-circuited to the drain electrode, whereby case, the flow of carriers accumulated in the N type base into the drain electrode is facilitated to accelerate dispersion of carriers upon turn-off of the transistor.
摘要翻译：导电调制型MOSFET采用N型导电性基板作为N基极。在形成在N基底中的P基底层中形成重掺杂N型导电性的第一源极层。源极电极导电P基极和源极。第一栅极绝缘地覆盖由P基底中的N +源层限定的沟道区域。在相对的基板表面上形成P漏极层。通过扩散在P型漏极层中形成N +第二源极层，以限定第二沟道区。第二栅电极绝缘地覆盖第二沟道区，从而提供电压控制关断控制晶体管。 MOSFET的漏电极导通P型漏极和第二源极。当关断控制晶体管导通以关断MOSFET时，暂时形成“短路阳极结构”，其中N型基极短路到漏极，由此情况下，累积在N型的载流子有助于在晶体管截止时加速载流子的分散。

8. 发明授权

US5105243A Conductivity-modulation metal oxide field effect transistor with single gate structure 失效
标题翻译：具有单栅极结构的电导率调制金属氧化物场效应晶体管
公开(公告)号：US5105243A
公开(公告)日：1992-04-14
申请号：US399342
申请日：1989-08-25
申请人： Akio Nakagawa , Yoshihiro Yamaguchi , Kiminori Watanabe
发明人： Akio Nakagawa , Yoshihiro Yamaguchi , Kiminori Watanabe
IPC分类号： H01L21/336 , H01L29/06 , H01L29/08 , H01L29/40 , H01L29/739
CPC分类号： H01L29/7396 , H01L29/0696 , H01L29/0834 , H01L29/402 , H01L29/405 , H01L29/7393 , H01L29/7395
摘要： There is disclosed a single-gate type conductivity-modulation field effect transistor having a first base layer, a second base layer, and a source layer formed in the second base layer. A source electrode is provided on a surface of the first base layer, for electrically shorting the second base layer with the source layer. A drain layer is provided in the first base layer surface. A drain electrode is formed on the layer surface to be in contact with the drain layer. A gate electrode is insulatively provided above the layer surface, for covering a certain surface portion of the second base layer which is positioned between the first base layer and the source layer to define a channel region below the gate electrode. A heavily-doped semiconductor layer is formed in the drain layer to have the opposite conductivity type to that of the drain layer. This semiconductor layer is in contact with the drain electrode. When the transistor is turned off, this layer facilitates carriers accumulated in the first base layer to flow into the drain electrode through the drain layer, thereby accelerating dispersion of the carriers in said transistor.
摘要翻译：公开了具有形成在第二基极层中的第一基极层，第二基极层和源极层的单栅极型导电调制场效应晶体管。源极电极设置在第一基极层的表面上，用于使第二基极层与源极层电气短路。在第一基层表面设置漏极层。漏极电极形成在层表面上以与漏极层接触。栅极电极被绝缘地设置在层表面之上，用于覆盖位于第一基极层和源极层之间的第二基极层的特定表面部分，以限定栅电极下方的沟道区。在漏极层中形成重掺杂的半导体层，以具有与漏极层相反的导电类型。该半导体层与漏电极接触。当晶体管截止时，该层便于积聚在第一基极层中的载流子通过漏极层流入漏电极，从而加速载流子在所述晶体管中的分散。

9. 发明授权

US5093701A Conductivity modulated MOSFET 失效
公开(公告)号：US5093701A
公开(公告)日：1992-03-03
申请号：US146405
申请日：1988-01-21
申请人： Akio Nakagawa , Hiromichi Ohashi , Yoshihiro Yamaguchi , Kiminori Watanabe , Thuneo Thukakoshi
发明人： Akio Nakagawa , Hiromichi Ohashi , Yoshihiro Yamaguchi , Kiminori Watanabe , Thuneo Thukakoshi
IPC分类号： H01L29/06 , H01L29/10 , H01L29/739
CPC分类号： H01L29/1095 , H01L29/0619 , H01L29/0696 , H01L29/7393 , H01L29/7395
摘要： A conductivity modulated MOSFET, having a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on the semiconductor substrate and having a high resistance, a base layer of the first conductivity type formed in the semiconductor layer, a source layer of the second conductivity type formed in the base layer, a gate electrode formed on a gate insulating film which is formed on a channel region, the channel region being formed in a surface of the base layer between the semiconductor layer and the source layer, a source electrode ohmic-contacting the source layer and the base layer, and a drain electrode formed on the surface of the semiconductor substrate opposite to the semiconductor layer, characterized in that the conductivity modulated MOSFET has a saturation current smaller than a latch-up current when a predetermined gate voltage is applied to the gate electrode.

10. 发明授权

US5068700A Lateral conductivity modulated MOSFET 失效
标题翻译：横向电导调制MOSFET
公开(公告)号：US5068700A
公开(公告)日：1991-11-26
申请号：US622351
申请日：1990-11-29
申请人： Yoshihiro Yamaguchi , Kiminori Watanabe , Akio Nakagawa
发明人： Yoshihiro Yamaguchi , Kiminori Watanabe , Akio Nakagawa
IPC分类号： H01L29/06 , H01L29/08 , H01L29/739
CPC分类号： H01L29/7394 , H01L29/0696 , H01L29/0834 , H01L29/7393
摘要： A lateral conductivity modulated MOSFET comprises a semiconductor wafer, a first-conductivity type base layer selectively formed in a surface region of the semiconductor wafer, a second-conductivity type source layer selectively formed in a surface region of the first-conductivity type base layer, a second-conductivity type base layer selectively formed in the semiconductor wafer, a first-conductivity type drain layer formed in a surface region of the second-conductivity type base layer, a gate insulation film formed on that surface portion of the first-conductivity type base layer which is sandwiched between the source layer and the second-conductivity type base layer, a gate electrode formed on the gate insulation film, a source electrode in contact with both the source layer and the first-conductivity type base layer, and a drain electrode in contact with the drain layer. A second-conductivity type cathode layer is formed in a surface region of the semiconductor wafer in such a manner that it is located adjacent to the second-conductivity type base layer. A cathode electrode is in contact with the cathode layer and is kept at the same potential level as that of the drain electrode.

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