专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07057940B2 Flash memory cell, flash memory cell array and manufacturing method thereof 失效
标题翻译：闪存单元，闪存单元阵列及其制造方法
公开(公告)号：US07057940B2
公开(公告)日：2006-06-06
申请号：US10907830
申请日：2005-04-18
申请人： Cheng-Yuan Hsu , Chih-Wei Hung , Chi-Shan Wu , Min-San Huang
发明人： Cheng-Yuan Hsu , Chih-Wei Hung , Chi-Shan Wu , Min-San Huang
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/0433 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A flash memory cell array comprises a substrate, a string of memory cell structures and source region/drain region. Each of memory cell structures includes a stack gate structure including a select gate dielectric layer, a select gate and a gate cap layer formed on the substrate; a spacer is set on the sidewall of the select gate; a control gate connected to the stack gate structure is set on the one side of the stack gate structure; a floating gate is set between the control gate and the substrate; an inter-gate dielectric layer is set between the control gate and the floating gate; and a tunneling dielectric layer is set between the floating gate and the substrate. The source region/drain region is set in the substrate near outer control gate and stack gate structure of the flash memory cell array.
摘要翻译：闪存单元阵列包括衬底，一串存储器单元结构和源极区/漏极区。每个存储单元结构包括堆叠栅极结构，其包括在基板上形成的选择栅极介电层，选择栅极和栅极盖层; 间隔件设置在选择门的侧壁上; 连接到堆叠栅极结构的控制栅极设置在堆叠栅极结构的一侧; 在控制栅极和衬底之间设置浮置栅极; 在控制栅极和浮置栅极之间设置栅极间电介质层; 并且在浮置栅极和衬底之间设置隧道电介质层。源区域/漏极区域设置在闪存单元阵列的外部控制栅极和堆叠栅极结构附近的衬底中。

2. 发明授权

US06911690B2 Flash memory cell, flash memory cell array and manufacturing method thereof 有权
标题翻译：闪存单元，闪存单元阵列及其制造方法
公开(公告)号：US06911690B2
公开(公告)日：2005-06-28
申请号：US10604819
申请日：2003-08-19
申请人： Cheng-Yuan Hsu , Chih-Wei Hung , Chi-Shan Wu , Min-San Huang
发明人： Cheng-Yuan Hsu , Chih-Wei Hung , Chi-Shan Wu , Min-San Huang
IPC分类号： G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/423 , H01L29/788
CPC分类号： H01L29/66825 , G11C16/0483 , H01L21/28273 , H01L29/42324
摘要： A flash memory cell array comprises a substrate, a string of memory cell structures and source region/drain region. Each of memory cell structures includes a stack gate structure including a select gate dielectric layer, a select gate and a gate cap layer formed on the substrate; a spacer is set on the sidewall of the select gate; a control gate connected to the stack gate structure is set on the one side of the stack gate structure; a floating gate is set between the control gate and the substrate; an inter-gate dielectric layer is set between the control gate and the floating gate; and a tunneling dielectric layer is set between the floating gate and the substrate. The source region/drain region is set in the substrate near outer control gate and stack gate structure of the flash memory cell array.
摘要翻译：闪存单元阵列包括衬底，一串存储器单元结构和源极区/漏极区。每个存储单元结构包括堆叠栅极结构，其包括在基板上形成的选择栅极介电层，选择栅极和栅极盖层; 间隔件设置在选择门的侧壁上; 连接到堆叠栅极结构的控制栅极设置在堆叠栅极结构的一侧; 在控制栅极和衬底之间设置浮置栅极; 在控制栅极和浮置栅极之间设置栅极间电介质层; 并且在浮置栅极和衬底之间设置隧道电介质层。源区域/漏极区域设置在闪存单元阵列的外部控制栅极和堆叠栅极结构附近的衬底中。

3. 发明授权

US07166513B2 Manufacturing method a flash memory cell array 失效
标题翻译：制造方法闪存单元阵列
公开(公告)号：US07166513B2
公开(公告)日：2007-01-23
申请号：US10907829
申请日：2005-04-18
申请人： Cheng-Yuan Hsu , Chih-Wei Hung , Chi-Shan Wu , Min-San Huang
发明人： Cheng-Yuan Hsu , Chih-Wei Hung , Chi-Shan Wu , Min-San Huang
IPC分类号： H01L21/336
CPC分类号： H01L29/66825 , G11C16/0483 , H01L21/28273 , H01L29/42324
摘要： A flash memory cell array comprises a substrate, a string of memory cell structures and source region/drain region. Each of memory cell structures includes a stack gate structure including a select gate dielectric layer, a select gate and a gate cap layer formed on the substrate; a spacer is set on the sidewall of the select gate; a control gate connected to the stack gate structure is set on the one side of the stack gate structure; a floating gate is set between the control gate and the substrate; an inter-gate dielectric layer is set between the control gate and the floating gate; and a tunneling dielectric layer is set between the floating gate and the substrate. The source region/drain region is set in the substrate near outer control gate and stack gate structure of the flash memory cell array.
摘要翻译：闪存单元阵列包括衬底，一串存储器单元结构和源极区/漏极区。每个存储单元结构包括堆叠栅极结构，其包括在基板上形成的选择栅极介电层，选择栅极和栅极盖层; 间隔件设置在选择门的侧壁上; 连接到堆叠栅极结构的控制栅极设置在堆叠栅极结构的一侧; 在控制栅极和衬底之间设置浮置栅极; 在控制栅极和浮置栅极之间设置栅极间电介质层; 并且在浮置栅极和衬底之间设置隧道电介质层。源区域/漏极区域设置在闪存单元阵列的外部控制栅极和堆叠栅极结构附近的衬底中。

4. 发明申请

US20050170579A1 FLASH MEMORY CELL, FLASH MEMORY CELL ARRAY AND MANUFACTURING METHOD THEREOF 失效
公开(公告)号：US20050170579A1
公开(公告)日：2005-08-04
申请号：US10907829
申请日：2005-04-18
申请人： Cheng-Yuan Hsu , Chih-Wei Hung , Chi-Shan Wu , Min-San Huang
发明人： Cheng-Yuan Hsu , Chih-Wei Hung , Chi-Shan Wu , Min-San Huang
IPC分类号： G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/423 , H01L29/788
CPC分类号： H01L29/66825 , G11C16/0483 , H01L21/28273 , H01L29/42324
摘要： A flash memory cell array comprises a substrate, a string of memory cell structures and source region/drain region. Each of memory cell structures includes a stack gate structure including a select gate dielectric layer, a select gate and a gate cap layer formed on the substrate; a spacer is set on the sidewall of the select gate; a control gate connected to the stack gate structure is set on the one side of the stack gate structure; a floating gate is set between the control gate and the substrate; an inter-gate dielectric layer is set between the control gate and the floating gate; and a tunneling dielectric layer is set between the floating gate and the substrate. The source region/drain region is set in the substrate near outer control gate and stack gate structure of the flash memory cell array.

5. 发明申请

US20050169035A1 FLASH MEMORY CELL, FLASH MEMORY CELL ARRAY AND MANUFACTURING METHOD THEREOF 失效
标题翻译：闪存存储单元，闪存存储单元阵列及其制造方法
公开(公告)号：US20050169035A1
公开(公告)日：2005-08-04
申请号：US10907830
申请日：2005-04-18
申请人： Cheng-Yuan Hsu , Chih-Wei Hung , Chi-Shan Wu , Min-San Huang
发明人： Cheng-Yuan Hsu , Chih-Wei Hung , Chi-Shan Wu , Min-San Huang
IPC分类号： G11C13/00 , G11C16/04 , H01L21/8247 , H01L27/115
CPC分类号： G11C16/0483 , G11C16/0433 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A flash memory cell array comprises a substrate, a string of memory cell structures and source region/drain region. Each of memory cell structures includes a stack gate structure including a select gate dielectric layer, a select gate and a gate cap layer formed on the substrate; a spacer is set on the sidewall of the select gate; a control gate connected to the stack gate structure is set on the one side of the stack gate structure; a floating gate is set between the control gate and the substrate; an inter-gate dielectric layer is set between the control gate and the floating gate; and a tunneling dielectric layer is set between the floating gate and the substrate. The source region/drain region is set in the substrate near outer control gate and stack gate structure of the flash memory cell array.
摘要翻译：闪存单元阵列包括衬底，一串存储器单元结构和源极区/漏极区。每个存储单元结构包括堆叠栅极结构，其包括在基板上形成的选择栅极介电层，选择栅极和栅极盖层; 间隔件设置在选择门的侧壁上; 连接到堆叠栅极结构的控制栅极设置在堆叠栅极结构的一侧; 在控制栅极和衬底之间设置浮置栅极; 在控制栅极和浮置栅极之间设置栅极间电介质层; 并且在浮置栅极和衬底之间设置隧道电介质层。源区域/漏极区域设置在闪存单元阵列的外部控制栅极和堆叠栅极结构附近的衬底中。

6. 发明申请

US20050087892A1 [NAND FLASH MEMORY CELL ROW, NAND FLASH MEMORY CELL ARRAY, OPERATION AND FABRICATION METHOD THEREOF] 审中-公开
标题翻译： [NAND FLASH MEMORY CELL ROW，NAND FLASH MEMORY CELL ARRAY，OPERATION AND FABRICATION METHOD YOUEROF]
公开(公告)号：US20050087892A1
公开(公告)日：2005-04-28
申请号：US10709125
申请日：2004-04-15
申请人： Cheng-Yuan Hsu , Chih-Wei Hung , Da Sung , Min-San Huang
发明人： Cheng-Yuan Hsu , Chih-Wei Hung , Da Sung , Min-San Huang
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/10 , H01L27/115
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115
摘要： A NAND flash memory cell array including a plurality of memory cell row is provided. Each of memory cell row includes a plurality of memory cells disposed between first selecting transistor and second selecting transistor connected in series. Each memory cell has a tunneling dielectric layer, a floating gate, an inter-gate dielectric, a control gate and source/drain regions. An erase gate is disposed between two adjacent memory cells. A plurality of word lines serve to connect the memory cells in rows. A source line serves to connect the source region of the first transistor in a row, whereas a plurality of bit lines serve to connect the drain region of second transistor in a row. A first selecting gate line and a second selecting gate line serve to connect the gate of the first transistor in a row and the gate of second transistor in a row respectively. A plurality of erase gate lines is connected to the erase gates in a row.
摘要翻译：提供包括多个存储单元行的NAND快闪存储单元阵列。每个存储单元行包括设置在串联连接的第一选择晶体管和第二选择晶体管之间的多个存储单元。每个存储单元具有隧道介电层，浮栅，栅极间电介质，控制栅极和源/漏区。擦除栅极设置在两个相邻的存储单元之间。多个字线用于以行的形式连接存储器单元。源极线用于将第一晶体管的源极区域连接成一行，而多个位线用于将第二晶体管的漏极区域连接成一行。第一选择栅极线和第二选择栅极线用于分别连接一行中的第一晶体管的栅极和第二晶体管的栅极。多条擦除栅极线一行连接到擦除栅极。

7. 发明授权

US06913974B2 Flash memory device structure and manufacturing method thereof 有权
标题翻译：闪存器件结构及其制造方法
公开(公告)号：US06913974B2
公开(公告)日：2005-07-05
申请号：US10709590
申请日：2004-05-17
申请人： Chih-Wei Hung , Min-San Huang
发明人： Chih-Wei Hung , Min-San Huang
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L21/336 , H01L21/3205 , H01L21/8238
CPC分类号： H01L27/11556 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/7883
摘要： A flash memory device structure is provided. The flash memory device consists of a P-type substrate with an opening, a deep N-well region in the P-type substrate, a first gate structure and a second gate structure on the respective sidewalls of the opening, an insulating layer in the space between the first gate structure and the second gate structure, a source region in the P-type substrate at the bottom section of the opening, a drain region in the P-type substrate at the top section of the opening, a P-well region in the deep N-well region such that the junction between the P-well and the deep N-well region is at a level higher than the bottom section of the opening and a P-type pocket doping region in the P-type substrate on the sidewalls of the opening such that the P-type pocket doping region connects the P-well region with the source region.
摘要翻译：提供闪速存储器件结构。闪存器件由具有开口的P型衬底，P型衬底中的深N阱区域，在开口的相应侧壁上的第一栅极结构和第二栅极结构组成，其中绝缘层第一栅极结构和第二栅极结构之间的间隔，开口底部的P型衬底中的源极区域，开口顶部的P型衬底中的漏极区域，P阱区域，使得P阱和深N阱区域之间的接合点处于比开口的底部部分高的水平面，并且P型衬底中的P型口袋掺杂区域在开口的侧壁上，使得P型袋掺杂区域将P阱区域与源极区域连接。

8. 发明授权

US06770934B1 Flash memory device structure and manufacturing method thereof 有权
标题翻译：闪存器件结构及其制造方法
公开(公告)号：US06770934B1
公开(公告)日：2004-08-03
申请号：US10249362
申请日：2003-04-03
申请人： Chih-Wei Hung , Min-San Huang
发明人： Chih-Wei Hung , Min-San Huang
IPC分类号： H01L29788
CPC分类号： H01L27/11556 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/7883
摘要： A flash memory device structure is provided. The flash memory device consists of a P-type substrate with an opening, a deep N-well region in the P-type substrate, a first gate structure and a second gate structure on the respective sidewalls of the opening, an insulating layer in the space between the first gate structure and the second gate structure, a source region in the P-type substrate at the bottom section of the opening, a drain region in the P-type substrate at the top section of the opening, a P-well region in the deep N-well region such that the junction between the P-well and the deep N-well region is at a level higher than the bottom section of the opening and a P-type pocket doping region in the P-type substrate on the sidewalls of the opening such that the P-type pocket doping region connects the P-well region with the source region.
摘要翻译：提供闪速存储器件结构。闪存器件由具有开口的P型衬底，P型衬底中的深N阱区域，在开口的相应侧壁上的第一栅极结构和第二栅极结构组成，其中绝缘层第一栅极结构和第二栅极结构之间的间隔，开口底部的P型衬底中的源极区域，开口顶部的P型衬底中的漏极区域，P阱区域，使得P阱和深N阱区域之间的接合点处于比开口的底部部分高的水平面，并且P型衬底中的P型口袋掺杂区域在开口的侧壁上，使得P型袋掺杂区域将P阱区域与源极区域连接。

9. 发明授权

US07391073B2 Non-volatile memory structure and method of fabricating non-volatile memory 有权
标题翻译：非易失性存储器结构和制造非易失性存储器的方法
公开(公告)号：US07391073B2
公开(公告)日：2008-06-24
申请号：US11162497
申请日：2005-09-13
申请人： Tsung-Lung Chen , Hui-Hung Kuo , Cheng-Yuan Hsu , Chih-Wei Hung
发明人： Tsung-Lung Chen , Hui-Hung Kuo , Cheng-Yuan Hsu , Chih-Wei Hung
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521
摘要： A method of fabricating a non-volatile memory is described. A substrate having a tunneling layer and a floating gate layer thereon is provided. A mask layer is formed on the floating gate. The mask layer has openings that expose a portion of the floating gate layer. Then, a portion of the floating gate layer is removed from the openings to form sunken regions on the surface of the floating gate layer. An inter-gate dielectric layer is formed on the floating gate layer. A control gate layer is formed on the inter-gate dielectric layer. After that, the mask layer and the floating gate layer under the mask layer are removed to form another opening. A select gate layer is formed inside the opening.
摘要翻译：描述了制造非易失性存储器的方法。提供了在其上具有隧道层和浮栅的衬底。在浮动栅极上形成掩模层。掩模层具有露出浮栅的一部分的开口。然后，从开口去除浮栅的一部分，以在浮栅层的表面上形成凹陷区域。栅极间介电层形成在浮栅层上。在栅极间电介质层上形成控制栅极层。之后，去除掩模层和掩模层下的浮栅层以形成另一个开口。在开口内形成选择栅极层。

10. 发明申请

US20070128799A1 METHOD OF FABRICATING FLASH MEMORY 审中-公开
标题翻译：制作闪速存储器的方法
公开(公告)号：US20070128799A1
公开(公告)日：2007-06-07
申请号：US11669163
申请日：2007-01-31
申请人： Jui-Yu Pan , Cheng-Yuan Hsu , I-Chun Chuang , Chih-Wei Hung
发明人： Jui-Yu Pan , Cheng-Yuan Hsu , I-Chun Chuang , Chih-Wei Hung
IPC分类号： H01L21/336 , H01L29/94
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/7782
摘要： A method for fabricating a flash memory is described. A mask layer having openings to expose a portion of the substrate is formed on the substrate. A tunneling dielectric layer is formed at the bottom surface of the openings. Conductive spacers are formed on the sidewalls of the openings. The conductive spacers are patterned to form a plurality of floating gates. A plurality of buried doped regions is formed in the substrate under the bottom surface of the openings. An inter-gate dielectric layer is formed over the substrate. A plurality of control gates is formed over the substrate to fill the openings. The mask layer is removed to form a plurality of memory units. A plurality of source regions and drain regions are formed in the substrate beside the memory units.
摘要翻译：描述了一种用于制造闪速存储器的方法。在基板上形成具有露出基板的一部分的开口的掩模层。在开口的底表面处形成隧道电介质层。导电间隔件形成在开口的侧壁上。将导电间隔物图案化以形成多个浮动栅极。在开口底面下方的基板中形成多个掩埋掺杂区域。栅极间电介质层形成在衬底上。多个控制栅极形成在衬底上以填充开口。去除掩模层以形成多个存储单元。在存储单元旁边的基板中形成多个源极区域和漏极区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式