专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09159791B2 Semiconductor device comprising a conductive region 有权
标题翻译：包括导电区域的半导体器件
公开(公告)号：US09159791B2
公开(公告)日：2015-10-13
申请号：US13489467
申请日：2012-06-06
申请人： Wei-Lin Chen , Ke-Feng Lin , Chih-Chien Chang , Chih-Chung Wang
发明人： Wei-Lin Chen , Ke-Feng Lin , Chih-Chien Chang , Chih-Chung Wang
IPC分类号： H01L29/66 , H01L29/08 , H01L29/417 , H01L29/78 , H01L29/06 , H01L21/225 , H01L21/265 , H01L29/45
CPC分类号： H01L29/0878 , H01L21/2255 , H01L21/2257 , H01L21/26586 , H01L29/0653 , H01L29/0873 , H01L29/41766 , H01L29/456 , H01L29/66719 , H01L29/7809
摘要： A semiconductor device includes a semiconductor substrate, a buried layer disposed in the semiconductor substrate; a deep well disposed in the semiconductor substrate; a first doped region disposed in the deep well, wherein the first doped region contacts the buried layer; a conductive region having the first conductivity type surrounding and being adjacent to the first doped region, wherein the conductive region has a concentration higher than the first doped region; a first heavily doped region disposed in the first doped region; a well having a second conductivity type disposed in the deep well; a second heavily doped region disposed in the well; a gate disposed on the semiconductor substrate between the first heavily doped region and the second heavily doped region; and a first trench structure and a second trench structure, wherein a depth of the second trench structure is substantially deeper than a depth of the buried layer.
摘要翻译：半导体器件包括半导体衬底，设置在半导体衬底中的掩埋层; 深井设置在半导体衬底中; 设置在所述深阱中的第一掺杂区，其中所述第一掺杂区接触所述掩埋层; 导电区域，具有围绕并邻近第一掺杂区域的第一导电类型，其中导电区域的浓度高于第一掺杂区域; 设置在所述第一掺杂区域中的第一重掺杂区域; 具有设置在深井中的具有第二导电类型的阱; 设置在井中的第二重掺杂区域; 设置在所述第一重掺杂区域和所述第二重掺杂区域之间的所述半导体衬底上的栅极; 以及第一沟槽结构和第二沟槽结构，其中所述第二沟槽结构的深度比所述掩埋层的深度更深。

2. 发明授权

US07732289B2 Method of forming a MOS device with an additional layer 有权
标题翻译：用附加层形成MOS器件的方法
公开(公告)号：US07732289B2
公开(公告)日：2010-06-08
申请号：US11174683
申请日：2005-07-05
申请人： Chii-Ming Wu , Chih-Wei Chang , Pang-Yen Tsai , Chih-Chien Chang
发明人： Chii-Ming Wu , Chih-Wei Chang , Pang-Yen Tsai , Chih-Chien Chang
IPC分类号： H01L21/366
CPC分类号： H01L29/665 , H01L21/28114 , H01L29/42376 , H01L29/6659 , H01L29/66636 , H01L29/7843
摘要： A method of forming MOS devices is provided. The method includes providing a semiconductor substrate, forming a gate dielectric over the semiconductor substrate, forming a gate electrode over the gate dielectric, forming a source/drain region in the semiconductor substrate, forming an additional layer, preferably by epitaxial growth, on the source/drain region, and siliciding at least a top portion of the additional layer. The additional layer compensates for at least a portion of the semiconductor material lost during manufacturing processes and increases the distance between the source/drain silicide and the substrate. As a result, the leakage current is reduced. A transistor formed using the preferred embodiment preferably includes a silicide over the gate electrode wherein the silicide extends beyond a sidewall boundary of the gate electrode.
摘要翻译：提供了一种形成MOS器件的方法。该方法包括提供半导体衬底，在半导体衬底上形成栅极电介质，在栅极电介质上形成栅电极，在半导体衬底中形成源/漏区，在源上形成附加层，优选通过外延生长 /漏极区域，并且至少将附加层的顶部部分硅化。附加层补偿在制造过程中损失的半导体材料的至少一部分，并且增加源极/漏极硅化物和衬底之间的距离。结果，泄漏电流降低。使用优选实施例形成的晶体管优选地包括在栅极上的硅化物，其中硅化物延伸超过栅电极的侧壁边界。

3. 发明授权

US07634183B2 Focus adjustable method of optical image 失效
标题翻译：光学图像聚焦可调方法
公开(公告)号：US07634183B2
公开(公告)日：2009-12-15
申请号：US11271363
申请日：2005-11-10
申请人： Hou-Ching Chin , Chih-Chien Chang
发明人： Hou-Ching Chin , Chih-Chien Chang
IPC分类号： G03B3/00 , G03B13/00
CPC分类号： G03B13/36 , G02B7/36
摘要： A focus adjustable method of an optical image is implemented by a numerical analysis. An external light beam is allowed to pass through a lens module, thereby generating an optical image. The focus values of the optical image at four corners thereof are computed according to specified formulas to obtain a two-dimensional geometric tilt vector T(X,Y), an image diagonal spinor D and an image tetragonal average value M. According to the values T(X,Y), D and M, the tilt amount and the tilt direction of the lens module are adjusted, the optical quality of the lens module is discriminated and the focus value distribution of the lens module is determined.
摘要翻译：通过数值分析实现光学图像的聚焦可调整方法。允许外部光束通过透镜模块，从而产生光学图像。根据指定的公式计算其四角的光学图像的焦点值，以获得二维几何倾斜向量T（X，Y），图像对角线旋转器D和图像四边形平均值M.根据值 T（X，Y），D和M，调整透镜模块的倾斜量和倾斜方向，确定透镜模块的光学质量并确定透镜模块的聚焦值分布。

4. 发明申请

US20080281536A1 SEMICONDUCTOR CP (CIRCUIT PROBE) TEST MANAGEMENT SYSTEM AND METHOD 有权
标题翻译：半导体CP（电路探头）测试管理系统和方法
公开(公告)号：US20080281536A1
公开(公告)日：2008-11-13
申请号：US11746222
申请日：2007-05-09
申请人： Chih-Chien Chang , Keng-Chia Yang , Yi-Sheng Huang , Ben Shin
发明人： Chih-Chien Chang , Keng-Chia Yang , Yi-Sheng Huang , Ben Shin
IPC分类号： G01R31/02 , G01R31/26
CPC分类号： G01R31/2834 , G01R31/2894
摘要： A system and method for semiconductor CP (circuit probe) test management. A control request message is received from a client computer, directing alignment of a probe unit or a wafer in a prober, attachment of a probe pin of the probe unit on a specific area of the wafer, and subsequent execution of CP testing. At least one control command corresponding to the control request message is issued to direct the prober for alignment of the probe unit or the wafer, attachment of the probe pin of the probe unit on the specific area of the wafer, and subsequent execution of CP testing.
摘要翻译：一种用于半导体CP（电路探头）测试管理的系统和方法。接收来自客户计算机的控制请求消息，指导探针单元或晶片在探测器中的对准，将探针单元的探针连接到晶片的特定区域上，以及随后执行CP测试。发出与控制请求消息对应的至少一个控制命令，以指导探测器对准探针单元或晶片，将探针单元的探针连接在晶片的特定区域上，以及随后执行CP测试。

5. 发明申请

US20070071349A1 Focus adjustable method of optical image 失效
标题翻译：光学图像聚焦可调方法
公开(公告)号：US20070071349A1
公开(公告)日：2007-03-29
申请号：US11271363
申请日：2005-11-10
申请人： Hou-Ching Chin , Chih-Chien Chang
发明人： Hou-Ching Chin , Chih-Chien Chang
IPC分类号： G06K9/40
CPC分类号： G03B13/36 , G02B7/36
摘要： A focus adjustable method of an optical image is implemented by a numerical analysis. An external light beam is allowed to pass through a lens module, thereby generating an optical image. The focus values of the optical image at four corners thereof are computed according to specified formulas to obtain a two-dimensional geometric tilt vector T(X,Y), an image diagonal spinor D and an image tetragonal average value M. According to the values T(X,Y), D and M, the tilt amount and the tilt direction of the lens module are adjusted, the optical quality of the lens module is discriminated and the focus value distribution of the lens module is determined.
摘要翻译：通过数值分析实现光学图像的聚焦可调整方法。允许外部光束通过透镜模块，从而产生光学图像。根据指定的公式计算其四角的光学图像的焦点值，以获得二维几何倾斜向量T（X，Y），图像对角线旋转器D和图像四边形平均值M.根据值 T（X，Y），D和M，调整透镜模块的倾斜量和倾斜方向，确定透镜模块的光学质量并确定透镜模块的聚焦值分布。

6. 发明授权

US07816217B2 Multi-step epitaxial process for depositing Si/SiGe 有权
标题翻译：用于沉积Si / SiGe的多步外延工艺
公开(公告)号：US07816217B2
公开(公告)日：2010-10-19
申请号：US11313768
申请日：2005-12-22
申请人： Li-Te S. Lin , Pang-Yen Tsai , Chih-Chien Chang , Tze-Liang Lee
发明人： Li-Te S. Lin , Pang-Yen Tsai , Chih-Chien Chang , Tze-Liang Lee
IPC分类号： H01L21/336
CPC分类号： H01L21/02639 , H01L21/02381 , H01L21/0245 , H01L21/02502 , H01L21/02532 , H01L21/0262 , H01L21/02661
摘要： A method for manufacturing a semiconductor device includes providing a substrate comprising silicon, cleaning the substrate, performing a first low pressure chemical vapor deposition (LPCVD) process using a first source gas to selectively deposit a seeding layer of silicon (Si) over the substrate, performing a second LPCVD process using a second source gas to selectively deposit a first layer of silicon germanium (SiGe) over the layer of Si, the second source gas including hydrochloride at a first flow rate, and performing a third LPCVD process using a third source gas including hydrochloride at a second flow rate. The first flow rate is substantially lower than the second flow rate.
摘要翻译：一种制造半导体器件的方法包括提供包括硅的衬底，清洁衬底，使用第一源气体执行第一低压化学气相沉积（LPCVD）工艺，以在衬底上选择性地沉积硅（Si）晶种层，使用第二源气体执行第二LPCVD处理，以选择性地在所述Si层上沉积第一层硅锗（SiGe），所述第二源气体以第一流速包括盐酸盐，并且使用第三源进行第三LPCVD处理气体包括盐酸盐以第二流量。第一流速基本上低于第二流量。

7. 发明授权

US07612389B2 Embedded SiGe stressor with tensile strain for NMOS current enhancement 有权
标题翻译：具有拉伸应变的嵌入式SiGe应力，用于NMOS电流增强
公开(公告)号：US07612389B2
公开(公告)日：2009-11-03
申请号：US11227592
申请日：2005-09-15
申请人： Li-Te S. Lin , Chih-Chien Chang , Tze-Liang Lee
发明人： Li-Te S. Lin , Chih-Chien Chang , Tze-Liang Lee
IPC分类号： H01L29/78
CPC分类号： H01L29/1083 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： MOS devices having localized stressors are provided. Embodiments of the invention comprise a gate electrode formed over a substrate and source/drain regions formed on either side of the gate electrode. The source/drain regions include an embedded stressor and a capping layer on the embedded stressor. Preferably, the embedded stressor has a lattice spacing greater than the substrate lattice spacing. In a preferred embodiment, the substrate is silicon and the embedded stressor is silicon germanium. A method of manufacturing is also provided, wherein strained PMOS and NMOS transistors may be formed simultaneously.
摘要翻译：提供具有局部应激源的MOS器件。本发明的实施例包括形成在衬底上的栅电极和形成在栅电极的任一侧上的源/漏区。源极/漏极区域包括嵌入的应力源和在嵌入的应力源上的覆盖层。优选地，嵌入的应力器具有大于衬底晶格间距的晶格间距。在优选实施例中，衬底是硅，并且嵌入的应力器是硅锗。还提供了一种制造方法，其中应变PMOS和NMOS晶体管可以同时形成。

8. 发明授权

US07587293B2 Semiconductor CP (circuit probe) test management system and method 有权
标题翻译：半导体CP（电路探头）测试管理系统及方法
公开(公告)号：US07587293B2
公开(公告)日：2009-09-08
申请号：US11746222
申请日：2007-05-09
申请人： Chih-Chien Chang , Keng-Chia Yang , Yi-Sheng Huang , Ben Shin
发明人： Chih-Chien Chang , Keng-Chia Yang , Yi-Sheng Huang , Ben Shin
IPC分类号： G06F19/00
CPC分类号： G01R31/2834 , G01R31/2894
摘要： A system and method for semiconductor CP (circuit probe) test management. A control request message is received from a client computer, directing alignment of a probe unit or a wafer in a prober, attachment of a probe pin of the probe unit on a specific area of the wafer, and subsequent execution of CP testing. At least one control command corresponding to the control request message is issued to direct the prober for alignment of the probe unit or the wafer, attachment of the probe pin of the probe unit on the specific area of the wafer, and subsequent execution of CP testing.
摘要翻译：一种用于半导体CP（电路探头）测试管理的系统和方法。接收来自客户计算机的控制请求消息，指导探针单元或晶片在探测器中的对准，将探针单元的探针连接到晶片的特定区域上，以及随后执行CP测试。发出与控制请求消息对应的至少一个控制命令，以指导探测器对准探针单元或晶片，将探针单元的探针连接在晶片的特定区域上，以及随后执行CP测试。

9. 发明申请

US20060228850A1 Pattern loading effect reduction for selective epitaxial growth 审中-公开
标题翻译：用于选择性外延生长的图案加载效应降低
公开(公告)号：US20060228850A1
公开(公告)日：2006-10-12
申请号：US11100053
申请日：2005-04-06
申请人： Pang-Yen Tsai , Chih-Chien Chang , Indira Yang , Tze-Liang Lee , Shih-Chang Chen
发明人： Pang-Yen Tsai , Chih-Chien Chang , Indira Yang , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/8238 , H01L21/76
CPC分类号： H01L29/66636 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/66628
摘要： A method of reducing the pattern-loading effect for selective epitaxial growth. The method includes the steps of: forming a mask layer over a substrate; forming an isolation region in the substrate isolating an active region and a dummy active region; removing at least a portion of the mask layer in the active region and thus forming a first opening, the substrate being exposed through the first opening; removing at least a portion of the mask layer in the dummy active region and thus forming a second opening, the substrate being exposed through the second opening; and performing selective epitaxial growth simultaneously on the substrate in the first opening and second openings. By introducing the second opening wherein epitaxial growth occurs, the pattern density is more uniform and thus the pattern-loading effect is reduced.
摘要翻译：降低选择性外延生长的图案负载效应的方法。该方法包括以下步骤：在衬底上形成掩模层; 在所述衬底中形成隔离有源区和虚拟有源区的隔离区; 去除所述有源区域中的所述掩模层的至少一部分，从而形成第一开口，所述基板通过所述第一开口露出; 去除所述虚拟有源区域中的所述掩模层的至少一部分，从而形成第二开口，所述基板通过所述第二开口露出; 以及在所述第一开口和所述第二开口中的所述衬底上同时执行选择性外延生长。通过引入其中发生外延生长的第二开口，图案密度更均匀，因此图案加载效应降低。

10. 发明申请

US20060113282A1 Method of depositing an epitaxial layer of SiGe subsequent to a plasma etch 有权
公开(公告)号：US20060113282A1
公开(公告)日：2006-06-01
申请号：US11001384
申请日：2004-12-01
申请人： Chih-Chien Chang , Shun Lin , Pang-Yen Tsai , Tze-Liang Lee , Shih-Chang Chen
发明人： Chih-Chien Chang , Shun Lin , Pang-Yen Tsai , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： B44C1/22 , B08B6/00 , B08B3/00 , C03C25/68
CPC分类号： H01L21/02658 , H01L21/02381 , H01L21/02532
摘要： A method of preparing a silicon layer or substrate surface for growing an epitaxial layer of SiGe thereon. The process comprises removing native oxide from the surface of the silicon with an HF solution, and then oxidizing the exposed silicon surface to form a chemically formed layer of silicon oxide of the process damaged silicon surface. The chemically formed layer of silicon oxide is then removed by a second HF cleaning process so as to leave a smooth silicon surface suitable for growing a SiGe layer.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式