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1. 发明申请

US20080235428A1 METHOD AND SYSTEM FOR DYNAMIC SWITCHING BETWEEN MULTIPLEXED INTERFACES 审中-公开
标题翻译：多路复用接口之间动态切换的方法与系统
公开(公告)号：US20080235428A1
公开(公告)日：2008-09-25
申请号：US11759360
申请日：2007-06-07
申请人： Chia-Hsing Yu , Lin-Hung Chen
发明人： Chia-Hsing Yu , Lin-Hung Chen
IPC分类号： G06F13/36
CPC分类号： G06F13/405
摘要： A bridge is disclosed. The bridge comprises a first interface having at least one multiplexed clock signal line. The multiplexed clock signal line outputs first and second control signals for respectively controlling the access to first and second devices coupled to the bridge. The bridge selectively outputs the first clock signal or the second clock signal to the multiplexed clock signal line to access the first device or the second device respectively.
摘要翻译：披露了一座桥梁。该桥包括具有至少一个复用的时钟信号线的第一接口。复用的时钟信号线输出第一和第二控制信号，用于分别控制对耦合到桥的第一和第二设备的访问。桥接器选择性地将第一时钟信号或第二时钟信号输出到复用的时钟信号线以分别访问第一设备或第二设备。

2. 发明授权

US07080282B2 Method for determining an operating voltage of floating point error detection 有权
公开(公告)号：US07080282B2
公开(公告)日：2006-07-18
申请号：US10063772
申请日：2002-05-11
申请人： Tsung-Yi Lin , Chia-Hsing Yu , Lin-Hung Chen
发明人： Tsung-Yi Lin , Chia-Hsing Yu , Lin-Hung Chen
IPC分类号： G06F11/00
CPC分类号： G06F11/24 , G01R31/3004
摘要： A method for determining an operating voltage of floating point error detection is implemented by a central processing unit (CPU) and a south bridge chipset. The CPU has a first output port connected to a test port of the south bridge. The test port is used to determine an operating voltage of the CPU. If the operating voltage of the CPU is greater than a predetermined value, the first output port is floating. If the operating voltage of the CPU is smaller than the predetermined value, the first output port is grounded. The method includes using a power supply and a resistor to provide a bias voltage and for measuring a voltage of the test port to determine the operating voltage of the CPU.

3. 发明授权

US08335941B2 Method for reducing power consumption of a computer system in the working state 有权
标题翻译：降低工作状态下计算机系统功耗的方法
公开(公告)号：US08335941B2
公开(公告)日：2012-12-18
申请号：US12752201
申请日：2010-04-01
申请人： Nai-Shung Chang , Chia-Hsing Yu
发明人： Nai-Shung Chang , Chia-Hsing Yu
IPC分类号： G06F1/04 , G06F1/12 , G06F5/06
CPC分类号： G06F1/324 , G06F1/3225 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method for reducing power consumption of a computer system in a working state is provided. The computer system comprises a processor, a memory and a chipset, and the processor is connected with the chipset through a processor bus. The method comprises classifying the power saving level of the computer system into a predetermined number of power saving modes, checking at least one power saving mode transition condition to determine whether to automatically raise the power saving mode of the computer system, and raising the power saving mode of the computer system by lowering a first voltage supply level of the chipset and a second voltage supply level of the memory and decreasing a first working frequency of the processor bus and a second working frequency of the memory. The power consumption of the computer system is further reduced in comparison with a normal working state when the power saving mode of the computer system is further raised.
摘要翻译：提供了一种降低处于工作状态的计算机系统的功耗的方法。计算机系统包括处理器，存储器和芯片组，并且处理器通过处理器总线与芯片组连接。该方法包括将计算机系统的省电水平分为预定数量的省电模式，检查至少一个省电模式转换条件，以确定是否自动提高计算机系统的省电模式，并提高节电通过降低芯片组的第一电压供应电平和存储器的第二电压供应电平并降低处理器总线的第一工作频率和存储器的第二工作频率来实现计算机系统的模式。当计算机系统的省电模式进一步提高时，与正常工作状态相比，计算机系统的功耗进一步降低。

4. 发明授权

US07032060B2 Control chip supporting plurality of buses and control chip set thereof 有权
标题翻译：控制芯片支持多个总线及其控制芯片组
公开(公告)号：US07032060B2
公开(公告)日：2006-04-18
申请号：US10710041
申请日：2004-06-15
申请人： Chia-Hsing Yu , Chi-Hsin Lin
发明人： Chia-Hsing Yu , Chi-Hsin Lin
IPC分类号： G06F13/20
CPC分类号： G06F13/4018
摘要： A control chip supporting a plurality of buses and control chip set thereof is provided. A control chip supporting a plurality of buses chooses a type of bus for complying with another control chip based on the bus type thereby, wherein a device and a driving circuit are included. The device generates required controlling timings based on selection pins. The driving circuit enables required transmitting direction of pins based on selection pins per se.
摘要翻译：提供了支持多个总线的控制芯片及其控制芯片组。支持多个总线的控制芯片基于总线类型选择一种用于符合另一个控制芯片的总线，其中包括设备和驱动电路。该器件根据选择引脚产生所需的控制时序。驱动电路基于选择引脚本身可实现引脚的所需传输方向。

5. 发明申请

US20070288782A1 METHOD FOR REDUCING POWER CONSUMPTION OF A COMPUTER SYSTEM IN THE WORKING STATE 有权
标题翻译：降低工作状态下计算机系统功耗的方法
公开(公告)号：US20070288782A1
公开(公告)日：2007-12-13
申请号：US11423722
申请日：2006-06-13
申请人： Nai-Shung Chang , Chia-Hsing Yu
发明人： Nai-Shung Chang , Chia-Hsing Yu
IPC分类号： G06F1/00
CPC分类号： G06F1/324 , G06F1/3225 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method for reducing power consumption of a computer system in a working state is provided. The computer system comprises a processor, a memory and a chipset, and the processor is connected with the chipset through a processor bus. The method comprises classifying the power saving level of the computer system into a predetermined number of power saving modes, checking at least one power saving mode transition condition to determine whether to automatically raise the power saving mode of the computer system, and raising the power saving mode of the computer system by lowering a first voltage supply level of the chipset and a second voltage supply level of the memory and decreasing a first working frequency of the processor bus and a second working frequency of the memory. The power consumption of the computer system is further reduced in comparison with a normal working state when the power saving mode of the computer system is further raised.
摘要翻译：提供了一种降低处于工作状态的计算机系统的功耗的方法。计算机系统包括处理器，存储器和芯片组，并且处理器通过处理器总线与芯片组连接。该方法包括将计算机系统的省电水平分为预定数量的省电模式，检查至少一个省电模式转换条件，以确定是否自动提高计算机系统的省电模式，并提高节电通过降低芯片组的第一电压供应电平和存储器的第二电压供应电平并降低处理器总线的第一工作频率和存储器的第二工作频率来实现计算机系统的模式。当计算机系统的省电模式进一步提高时，与正常工作状态相比，计算机系统的功耗进一步降低。

6. 发明授权

US06946731B2 Layout structure for providing stable power source to a main bridge chip substrate and a motherboard 有权
公开(公告)号：US06946731B2
公开(公告)日：2005-09-20
申请号：US10173231
申请日：2002-06-14
申请人： Nai-Shung Chang , Shu-Hui Chen , Tsai-Sheng Chen , Chia-Hsing Yu
发明人： Nai-Shung Chang , Shu-Hui Chen , Tsai-Sheng Chen , Chia-Hsing Yu
IPC分类号： H01L23/34 , H01L23/48 , H01L23/498 , H01L23/50 , H01L23/52 , H01L29/00 , H01L31/00 , H05K1/11 , H05K1/18
CPC分类号： H01L23/49838 , H01L23/50 , H01L24/48 , H01L2224/05599 , H01L2224/45099 , H01L2224/48227 , H01L2224/85399 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/30107 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： This invention relates to a layout structure for providing stable power supply to a four-layer motherboard and a main bridge chip substrate. In the invention, on the top signal layer and power path of the bottom solder layer for layout of the main bridge chip and on the power ring, the decoupling capacitors are connected in between the ground bonding pads/solder balls and the power bonding pads/solder balls of the power paths and power rings, so as to provide a stable power supply for the operation of the main bridge chip. In this invention, the ground bonding pad/solder ball connected with each power bonding pad/solder ball can be the closest ground bonding pad/solder ball to the power bonding pad/solder ball. In addition, in the embodiment of the main bridge chip substrate, decoupling capacitors can be disposed at four corners of the power ring or underneath the bonding wires, or can be packaged inside the molding compound.

7. 发明授权

US06944783B2 Power controller and associated multi-processor type supporting computer system 有权
标题翻译：电源控制器和相关的多处理器类型支持计算机系统
公开(公告)号：US06944783B2
公开(公告)日：2005-09-13
申请号：US10037896
申请日：2001-10-22
申请人： Chia-Hsing Yu , Nai-Shung Chang
发明人： Chia-Hsing Yu , Nai-Shung Chang
IPC分类号： G06F1/26
CPC分类号： G06F1/26
摘要： A power controller for a computer system capable of supporting multiple processor types. The power controller receives a voltage identification signal from the microprocessor and a microprocessor selection signal from a motherboard to provide a correct voltage specification signal and terminal voltage to the microprocessor. The invention also provides voltage specification signals and terminal voltages to the motherboard of a computer system that can support a multiple of processor types.
摘要翻译：一种能够支持多种处理器类型的计算机系统的电源控制器。功率控制器接收来自微处理器的电压识别信号和来自母板的微处理器选择信号，以向微处理器提供正确的电压指定信号和端电压。本发明还向可以支持多种处理器类型的计算机系统的主板提供电压指定信号和端电压。

8. 发明授权

US06750868B2 Universal accelerated graphic port system and method for operating the same 有权
标题翻译：通用加速图形端口系统及操作方法
公开(公告)号：US06750868B2
公开(公告)日：2004-06-15
申请号：US10131170
申请日：2002-04-23
申请人： Chia-Hsing Yu
发明人： Chia-Hsing Yu
IPC分类号： G06F1314
CPC分类号： G06F3/14
摘要： An accelerated graphic port (AGP) system uses several control signals to allow an AGP graphic card to enter into negotiation with a motherboard. These control signals can drive the motherboard to provide AGP operating voltage (VCCQ) and providing a first reference voltage for the motherboard according to the AGP operating voltage. On the other hand, the motherboard will provide a second reference voltage to the AGP graphic card according to the determination of whether or not the AGP graphic card is an AGP8X card. Therefore the universal AGP connector of the present invention can enable all kinds of AGP graphic cards to be coupled to the motherboard, and can prompt the motherboard to meet with all the AGP system specifications and support all kinds of AGP graphic cards.
摘要翻译：加速图形端口（AGP）系统使用几个控制信号来允许AGP图形卡与主板进行协商。这些控制信号可以驱动主板以提供AGP工作电压（VCCQ），并根据AGP工作电压为主板提供第一个参考电压。另一方面，根据AGP图形卡是否是AGP8X卡的确定，主板将向AGP图形卡提供第二参考电压。因此，本发明的通用AGP连接器可以使各种AGP图形卡耦合到主板，并且可以提示主板满足所有的AGP系统规格并支持各种AGP图形卡。

9. 发明授权

US09042104B2 Portable electronic device and electronic module fixing structure thereof 有权
标题翻译：便携式电子装置及其电子模块固定结构
公开(公告)号：US09042104B2
公开(公告)日：2015-05-26
申请号：US13596083
申请日：2012-08-28
申请人： Yu-Han Tsai , Chun-Wang Lin , Ching-Wei Ku , Chia-Hsing Yu , Yao-Te Tsai , Chia-Hung Tsai
发明人： Yu-Han Tsai , Chun-Wang Lin , Ching-Wei Ku , Chia-Hsing Yu , Yao-Te Tsai , Chia-Hung Tsai
IPC分类号： H05K7/00 , G06F1/18 , G11B33/12
CPC分类号： G06F1/187 , G11B33/124
摘要： A portable electronic device includes an electronic module and an electronic module fixing structure. The electronic module fixing structure includes a main body, a sliding component, a rod and an elastic component connected between the main body and the sliding component. The main body has a track with a positioning portion. The sliding component is slidably disposed on the main body. The rod is rotatably connected with the sliding component. An end of the rod is adapted to move along the track. When the end is located at the positioning portion, the end and the positioning portion are interfered with each other to position the sliding component. When the electronic module pushes the sliding component, the rod is rotated to drive the end to move away from the positioning portion, and the sliding component pushes the electronic module away from the main body through elastic force of the elastic component.
摘要翻译：便携式电子设备包括电子模块和电子模块固定结构。电子模块固定结构包括连接在主体和滑动部件之间的主体，滑动部件，杆和弹性部件。主体具有具有定位部分的轨道。滑动部件可滑动地设置在主体上。杆与滑动部件可旋转地连接。杆的端部适于沿着轨道移动。当端部位于定位部分时，端部和定位部分相互干涉以定位滑动部件。当电子模块推动滑动部件时，杆被旋转以驱动端部移动远离定位部分，并且滑动部件通过弹性部件的弹力将电子模块推离主体。

10. 发明授权

US07689847B2 Method for increasing the data processing capability of a computer system 有权
标题翻译：提高计算机系统数据处理能力的方法
公开(公告)号：US07689847B2
公开(公告)日：2010-03-30
申请号：US11423718
申请日：2006-06-13
申请人： Nai-Shung Chang , Chia-Hsing Yu
发明人： Nai-Shung Chang , Chia-Hsing Yu
IPC分类号： G06F1/00
CPC分类号： G06F1/206 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/124 , Y02D10/126 , Y02D10/172
摘要： A method for dynamically increasing the data processing capability of a computer system is provided. The computer system comprises a processor, a memory and a chipset. The data processing capability of the computer system is classified into a predetermined number of performance enhancing modes. At least one performance enhancing mode transition condition is checked to determine whether to automatically raise the performance enhancing mode of the computer system. The processor is suspended from using the processor bus during the transition of the performance enhancing mode of the computer system. The performance enhancing mode of the computer system is raised by increasing a first working frequency of the processor, a second working frequency of the processor bus and a third working frequency of the memory. The data processing rate of the computer system is further increased when the performance enhancing mode of the computer system is further raised.
摘要翻译：提供了一种用于动态提高计算机系统的数据处理能力的方法。计算机系统包括处理器，存储器和芯片组。计算机系统的数据处理能力被分为预定数量的性能增强模式。检查至少一个性能增强模式转换条件以确定是否自动提高计算机系统的性能增强模式。处理器在计算机系统的性能提升模式转换期间被暂停使用处理器总线。通过增加处理器的第一工作频率，处理器总线的第二工作频率和存储器的第三工作频率来提高计算机系统的性能增强模式。当计算机系统的性能提升模式进一步提高时，计算机系统的数据处理速度进一步提高。

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