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1. 发明申请

US20070288782A1 METHOD FOR REDUCING POWER CONSUMPTION OF A COMPUTER SYSTEM IN THE WORKING STATE 有权
标题翻译：降低工作状态下计算机系统功耗的方法
公开(公告)号：US20070288782A1
公开(公告)日：2007-12-13
申请号：US11423722
申请日：2006-06-13
申请人： Nai-Shung Chang , Chia-Hsing Yu
发明人： Nai-Shung Chang , Chia-Hsing Yu
IPC分类号： G06F1/00
CPC分类号： G06F1/324 , G06F1/3225 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method for reducing power consumption of a computer system in a working state is provided. The computer system comprises a processor, a memory and a chipset, and the processor is connected with the chipset through a processor bus. The method comprises classifying the power saving level of the computer system into a predetermined number of power saving modes, checking at least one power saving mode transition condition to determine whether to automatically raise the power saving mode of the computer system, and raising the power saving mode of the computer system by lowering a first voltage supply level of the chipset and a second voltage supply level of the memory and decreasing a first working frequency of the processor bus and a second working frequency of the memory. The power consumption of the computer system is further reduced in comparison with a normal working state when the power saving mode of the computer system is further raised.
摘要翻译：提供了一种降低处于工作状态的计算机系统的功耗的方法。计算机系统包括处理器，存储器和芯片组，并且处理器通过处理器总线与芯片组连接。该方法包括将计算机系统的省电水平分为预定数量的省电模式，检查至少一个省电模式转换条件，以确定是否自动提高计算机系统的省电模式，并提高节电通过降低芯片组的第一电压供应电平和存储器的第二电压供应电平并降低处理器总线的第一工作频率和存储器的第二工作频率来实现计算机系统的模式。当计算机系统的省电模式进一步提高时，与正常工作状态相比，计算机系统的功耗进一步降低。

2. 发明授权

US06946731B2 Layout structure for providing stable power source to a main bridge chip substrate and a motherboard 有权
公开(公告)号：US06946731B2
公开(公告)日：2005-09-20
申请号：US10173231
申请日：2002-06-14
申请人： Nai-Shung Chang , Shu-Hui Chen , Tsai-Sheng Chen , Chia-Hsing Yu
发明人： Nai-Shung Chang , Shu-Hui Chen , Tsai-Sheng Chen , Chia-Hsing Yu
IPC分类号： H01L23/34 , H01L23/48 , H01L23/498 , H01L23/50 , H01L23/52 , H01L29/00 , H01L31/00 , H05K1/11 , H05K1/18
CPC分类号： H01L23/49838 , H01L23/50 , H01L24/48 , H01L2224/05599 , H01L2224/45099 , H01L2224/48227 , H01L2224/85399 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/30107 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： This invention relates to a layout structure for providing stable power supply to a four-layer motherboard and a main bridge chip substrate. In the invention, on the top signal layer and power path of the bottom solder layer for layout of the main bridge chip and on the power ring, the decoupling capacitors are connected in between the ground bonding pads/solder balls and the power bonding pads/solder balls of the power paths and power rings, so as to provide a stable power supply for the operation of the main bridge chip. In this invention, the ground bonding pad/solder ball connected with each power bonding pad/solder ball can be the closest ground bonding pad/solder ball to the power bonding pad/solder ball. In addition, in the embodiment of the main bridge chip substrate, decoupling capacitors can be disposed at four corners of the power ring or underneath the bonding wires, or can be packaged inside the molding compound.

3. 发明授权

US06944783B2 Power controller and associated multi-processor type supporting computer system 有权
标题翻译：电源控制器和相关的多处理器类型支持计算机系统
公开(公告)号：US06944783B2
公开(公告)日：2005-09-13
申请号：US10037896
申请日：2001-10-22
申请人： Chia-Hsing Yu , Nai-Shung Chang
发明人： Chia-Hsing Yu , Nai-Shung Chang
IPC分类号： G06F1/26
CPC分类号： G06F1/26
摘要： A power controller for a computer system capable of supporting multiple processor types. The power controller receives a voltage identification signal from the microprocessor and a microprocessor selection signal from a motherboard to provide a correct voltage specification signal and terminal voltage to the microprocessor. The invention also provides voltage specification signals and terminal voltages to the motherboard of a computer system that can support a multiple of processor types.
摘要翻译：一种能够支持多种处理器类型的计算机系统的电源控制器。功率控制器接收来自微处理器的电压识别信号和来自母板的微处理器选择信号，以向微处理器提供正确的电压指定信号和端电压。本发明还向可以支持多种处理器类型的计算机系统的主板提供电压指定信号和端电压。

4. 发明授权

US08335941B2 Method for reducing power consumption of a computer system in the working state 有权
标题翻译：降低工作状态下计算机系统功耗的方法
公开(公告)号：US08335941B2
公开(公告)日：2012-12-18
申请号：US12752201
申请日：2010-04-01
申请人： Nai-Shung Chang , Chia-Hsing Yu
发明人： Nai-Shung Chang , Chia-Hsing Yu
IPC分类号： G06F1/04 , G06F1/12 , G06F5/06
CPC分类号： G06F1/324 , G06F1/3225 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method for reducing power consumption of a computer system in a working state is provided. The computer system comprises a processor, a memory and a chipset, and the processor is connected with the chipset through a processor bus. The method comprises classifying the power saving level of the computer system into a predetermined number of power saving modes, checking at least one power saving mode transition condition to determine whether to automatically raise the power saving mode of the computer system, and raising the power saving mode of the computer system by lowering a first voltage supply level of the chipset and a second voltage supply level of the memory and decreasing a first working frequency of the processor bus and a second working frequency of the memory. The power consumption of the computer system is further reduced in comparison with a normal working state when the power saving mode of the computer system is further raised.
摘要翻译：提供了一种降低处于工作状态的计算机系统的功耗的方法。计算机系统包括处理器，存储器和芯片组，并且处理器通过处理器总线与芯片组连接。该方法包括将计算机系统的省电水平分为预定数量的省电模式，检查至少一个省电模式转换条件，以确定是否自动提高计算机系统的省电模式，并提高节电通过降低芯片组的第一电压供应电平和存储器的第二电压供应电平并降低处理器总线的第一工作频率和存储器的第二工作频率来实现计算机系统的模式。当计算机系统的省电模式进一步提高时，与正常工作状态相比，计算机系统的功耗进一步降低。

5. 发明申请

US20100191988A1 METHOD FOR REDUCING POWER CONSUMPTION OF A COMPUTER SYSTEM IN THE WORKING STATE 有权
标题翻译：降低工作状态下计算机系统功耗的方法
公开(公告)号：US20100191988A1
公开(公告)日：2010-07-29
申请号：US12752201
申请日：2010-04-01
申请人： Nai-Shung Chang , Chia-Hsing Yu
发明人： Nai-Shung Chang , Chia-Hsing Yu
IPC分类号： G06F1/00
CPC分类号： G06F1/324 , G06F1/3225 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method for reducing power consumption of a computer system in a working state is provided. The computer system comprises a processor, a memory and a chipset, and the processor is connected with the chipset through a processor bus. The method comprises classifying the power saving level of the computer system into a predetermined number of power saving modes, checking at least one power saving mode transition condition to determine whether to automatically raise the power saving mode of the computer system, and raising the power saving mode of the computer system by lowering a first voltage supply level of the chipset and a second voltage supply level of the memory and decreasing a first working frequency of the processor bus and a second working frequency of the memory. The power consumption of the computer system is further reduced in comparison with a normal working state when the power saving mode of the computer system is further raised.
摘要翻译：提供了一种降低处于工作状态的计算机系统的功耗的方法。计算机系统包括处理器，存储器和芯片组，并且处理器通过处理器总线与芯片组连接。该方法包括将计算机系统的省电水平分为预定数量的省电模式，检查至少一个省电模式转换条件，以确定是否自动提高计算机系统的省电模式，并提高节电通过降低芯片组的第一电压供应电平和存储器的第二电压供应电平并降低处理器总线的第一工作频率和存储器的第二工作频率来实现计算机系统的模式。当计算机系统的省电模式进一步提高时，与正常工作状态相比，计算机系统的功耗进一步降低。

6. 发明申请

US20070288769A1 METHOD FOR INCREASING THE DATA PROCESSING CAPABILITY OF A COMPUTER SYSTEM 有权
标题翻译：提高计算机系统数据处理能力的方法
公开(公告)号：US20070288769A1
公开(公告)日：2007-12-13
申请号：US11423718
申请日：2006-06-13
申请人： Nai-Shung Chang , Chia-Hsing Yu
发明人： Nai-Shung Chang , Chia-Hsing Yu
IPC分类号： G06F1/00
CPC分类号： G06F1/206 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/124 , Y02D10/126 , Y02D10/172
摘要： A method for dynamically increasing the data processing capability of a computer system is provided. The computer system comprises a processor, a memory and a chipset. The data processing capability of the computer system is classified into a predetermined number of performance enhancing modes. At least one performance enhancing mode transition condition is checked to determine whether to automatically raise the performance enhancing mode of the computer system. The processor is suspended from using the processor bus during the transition of the performance enhancing mode of the computer system. The performance enhancing mode of the computer system is raised by increasing a first working frequency of the processor, a second working frequency of the processor bus and a third working frequency of the memory. The data processing rate of the computer system is further increased when the performance enhancing mode of the computer system is further raised.
摘要翻译：提供了一种用于动态提高计算机系统的数据处理能力的方法。计算机系统包括处理器，存储器和芯片组。计算机系统的数据处理能力被分为预定数量的性能增强模式。检查至少一个性能增强模式转换条件以确定是否自动提高计算机系统的性能增强模式。处理器在计算机系统的性能提升模式转换期间被暂停使用处理器总线。通过增加处理器的第一工作频率，处理器总线的第二工作频率和存储器的第三工作频率来提高计算机系统的性能增强模式。当计算机系统的性能提升模式进一步提高时，计算机系统的数据处理速度进一步提高。

7. 发明授权

US07095415B2 Graphics display architecture and control chip set thereof 有权
标题翻译：图形显示架构及其控制芯片组
公开(公告)号：US07095415B2
公开(公告)日：2006-08-22
申请号：US10710095
申请日：2004-06-18
申请人： Nai-Shung Chang , Chia-Hsing Yu , Lin Yang
发明人： Nai-Shung Chang , Chia-Hsing Yu , Lin Yang
IPC分类号： G06F13/14 , G06F15/00 , G06F15/16
CPC分类号： G06F3/14
摘要： The graphics display architecture provided by the present invention comprises an AGP slot, a PCIE slot, and a control chip set. The control chip set comprises a plurality of multi-defined pins, which are electrically coupled to the first pins of the AGP slot and the second pins of the PCIE slot simultaneously. When the first graphics adapter is plugged in the AGP slot and the first graphics adapter complies with AGP interface specification, the multi-defined pins serve to send/receive the signal complied with AGP interface specification. When the first graphics adapter is plugged in the AGP slot and the first graphics adapter complies with the Gfx interface, the multi-defined pins serve to send/receive the signal complied with the Gfx interface. When the second graphics adapter is plugged in the PCIE slot, the multi-defined pins serve to send/receive the signal complied wit the PCIE interface specification.
摘要翻译：本发明提供的图形显示架构包括AGP槽，PCIE槽和控制芯片组。控制芯片组包括多个多限定的引脚，它们同时电耦合到AGP插槽的第一引脚和PCIE插槽的第二引脚。当第一个图形适配器插入AGP插槽并且第一个图形适配器符合AGP接口规范时，多重定义的引脚用于发送/接收符合AGP接口规范的信号。当第一个图形适配器插入AGP插槽并且第一个图形适配器符合Gfx接口时，多重定义的引脚用于发送/接收符合Gfx接口的信号。当第二个图形适配器插入PCIE插槽时，多重定义的引脚用于发送/接收符合PCIE接口规范的信号。

8. 发明申请

US20050263849A1 Layout structure for providing stable power source to a main bridge chip substrate and a motherboard 审中-公开
标题翻译：用于向主桥芯片基板和主板提供稳定电源的布局结构
公开(公告)号：US20050263849A1
公开(公告)日：2005-12-01
申请号：US11196039
申请日：2005-08-02
申请人： Nai-Shung Chang , Shu-Hui Chen , Tsai-Sheng Chen , Chia-Hsing Yu
发明人： Nai-Shung Chang , Shu-Hui Chen , Tsai-Sheng Chen , Chia-Hsing Yu
IPC分类号： H01L23/34 , H01L23/48 , H01L23/498 , H01L23/50 , H01L23/52 , H01L29/00 , H01L31/00 , H05K1/11 , H05K1/18
CPC分类号： H01L23/49838 , H01L23/50 , H01L24/48 , H01L2224/05599 , H01L2224/45099 , H01L2224/48227 , H01L2224/85399 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/30107 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： This invention relates to a layout structure for providing stable power supply to a four-layer motherboard and a main bridge chip substrate. In the invention, on the top signal layer and power path of the bottom solder layer for layout of the main bridge chip and on the power ring, the decoupling capacitors are connected in between the ground bonding pads/solder balls and the power bonding pads/solder balls of the power paths and power rings, so as to provide a stable power supply for the operation of the main bridge chip. In this invention, the ground bonding pad/solder ball connected with each power bonding pad/solder ball can be the closest ground bonding pad/solder ball to the power bonding pad/solder ball. In addition, in the embodiment of the main bridge chip substrate, decoupling capacitors can be disposed at four corners of the power ring or underneath the bonding wires, or can be packaged inside the molding compound.
摘要翻译：本发明涉及一种用于向四层母板和主桥芯片基板提供稳定电源的布局结构。在本发明中，在用于布局主桥芯片和功率环的底部焊料层的顶部信号层和功率路径上，去耦电容器连接在接地焊盘/焊球和电源接合焊盘/ 焊球的动力路径和动力环，从而为主桥芯片的运行提供稳定的电源。在本发明中，与每个电源焊盘/焊球相连的接地焊盘/焊球可以是与功率焊盘/焊球最接近的接地焊盘/焊球。此外，在主桥芯片基板的实施例中，去耦电容器可以设置在电源环的四个角落或者接合线下方，或者可以封装在模制化合物内部。

9. 发明授权

US06836848B2 Power management integrated circuit for overriding an internal frequency ID code of a processor and for providing frequency ID value to a bridge chipset 有权
标题翻译：电源管理集成电路，用于覆盖处理器的内部频率ID码，并为桥接芯片组提供频率ID值
公开(公告)号：US06836848B2
公开(公告)日：2004-12-28
申请号：US09683243
申请日：2001-12-05
申请人： Chia-Hsing Yu , Nai-Shung Chang
发明人： Chia-Hsing Yu , Nai-Shung Chang
IPC分类号： G06F126
CPC分类号： G06F1/26
摘要： An integrated circuit includes voltage identification (VID) logic and frequency identification logic (FID) for a CPU, as well as power good circuitry for indicating the suitability of electrical power supplies. A VID output signal to control a core voltage provided to the CPU is generated according to an input VID signal provided by the CPU, a sleep state signal, and a CPU mobility-type signal. FID, VID and power detection logic all level shift signals as required for external devices. A programmable table enables overriding of output FID and VID values.
摘要翻译：集成电路包括用于CPU的电压识别（VID）逻辑和频率识别逻辑（FID），以及用于指示电力供应适用性的电力良好电路。根据由CPU提供的输入VID信号，休眠状态信号和CPU移动性型信号，生成用于控制提供给CPU的核心电压的VID输出信号。 FID，VID和功率检测逻辑根据外部设备所需的所有电平移位信号。可编程表可以覆盖输出FID和VID值。

10. 发明授权

US07783905B2 Method for reducing power consumption of a computer system in the working state 有权
标题翻译：降低工作状态下计算机系统功耗的方法
公开(公告)号：US07783905B2
公开(公告)日：2010-08-24
申请号：US11423722
申请日：2006-06-13
申请人： Nai-Shung Chang , Chia-Hsing Yu
发明人： Nai-Shung Chang , Chia-Hsing Yu
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/324 , G06F1/3225 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method for reducing power consumption of a computer system in a working state is provided. The computer system comprises a processor, a memory and a chipset, and the processor is connected with the chipset through a processor bus. The method comprises classifying the power saving level of the computer system into a predetermined number of power saving modes, checking at least one power saving mode transition condition to determine whether to automatically raise the power saving mode of the computer system, and raising the power saving mode of the computer system by lowering a first voltage supply level of the chipset and a second voltage supply level of the memory and decreasing a first working frequency of the processor bus and a second working frequency of the memory. The power consumption of the computer system is further reduced in comparison with a normal working state when the power saving mode of the computer system is further raised.
摘要翻译：提供了一种降低处于工作状态的计算机系统的功耗的方法。计算机系统包括处理器，存储器和芯片组，并且处理器通过处理器总线与芯片组连接。该方法包括将计算机系统的省电水平分为预定数量的省电模式，检查至少一个省电模式转换条件，以确定是否自动提高计算机系统的省电模式，并提高节电通过降低芯片组的第一电压供应电平和存储器的第二电压供应电平并降低处理器总线的第一工作频率和存储器的第二工作频率来实现计算机系统的模式。当计算机系统的省电模式进一步提高时，与正常工作状态相比，计算机系统的功耗进一步降低。

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