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1. 发明授权

US06946731B2 Layout structure for providing stable power source to a main bridge chip substrate and a motherboard 有权
公开(公告)号：US06946731B2
公开(公告)日：2005-09-20
申请号：US10173231
申请日：2002-06-14
申请人： Nai-Shung Chang , Shu-Hui Chen , Tsai-Sheng Chen , Chia-Hsing Yu
发明人： Nai-Shung Chang , Shu-Hui Chen , Tsai-Sheng Chen , Chia-Hsing Yu
IPC分类号： H01L23/34 , H01L23/48 , H01L23/498 , H01L23/50 , H01L23/52 , H01L29/00 , H01L31/00 , H05K1/11 , H05K1/18
CPC分类号： H01L23/49838 , H01L23/50 , H01L24/48 , H01L2224/05599 , H01L2224/45099 , H01L2224/48227 , H01L2224/85399 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/30107 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： This invention relates to a layout structure for providing stable power supply to a four-layer motherboard and a main bridge chip substrate. In the invention, on the top signal layer and power path of the bottom solder layer for layout of the main bridge chip and on the power ring, the decoupling capacitors are connected in between the ground bonding pads/solder balls and the power bonding pads/solder balls of the power paths and power rings, so as to provide a stable power supply for the operation of the main bridge chip. In this invention, the ground bonding pad/solder ball connected with each power bonding pad/solder ball can be the closest ground bonding pad/solder ball to the power bonding pad/solder ball. In addition, in the embodiment of the main bridge chip substrate, decoupling capacitors can be disposed at four corners of the power ring or underneath the bonding wires, or can be packaged inside the molding compound.

2. 发明申请

US20050263849A1 Layout structure for providing stable power source to a main bridge chip substrate and a motherboard 审中-公开
标题翻译：用于向主桥芯片基板和主板提供稳定电源的布局结构
公开(公告)号：US20050263849A1
公开(公告)日：2005-12-01
申请号：US11196039
申请日：2005-08-02
申请人： Nai-Shung Chang , Shu-Hui Chen , Tsai-Sheng Chen , Chia-Hsing Yu
发明人： Nai-Shung Chang , Shu-Hui Chen , Tsai-Sheng Chen , Chia-Hsing Yu
IPC分类号： H01L23/34 , H01L23/48 , H01L23/498 , H01L23/50 , H01L23/52 , H01L29/00 , H01L31/00 , H05K1/11 , H05K1/18
CPC分类号： H01L23/49838 , H01L23/50 , H01L24/48 , H01L2224/05599 , H01L2224/45099 , H01L2224/48227 , H01L2224/85399 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/30107 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： This invention relates to a layout structure for providing stable power supply to a four-layer motherboard and a main bridge chip substrate. In the invention, on the top signal layer and power path of the bottom solder layer for layout of the main bridge chip and on the power ring, the decoupling capacitors are connected in between the ground bonding pads/solder balls and the power bonding pads/solder balls of the power paths and power rings, so as to provide a stable power supply for the operation of the main bridge chip. In this invention, the ground bonding pad/solder ball connected with each power bonding pad/solder ball can be the closest ground bonding pad/solder ball to the power bonding pad/solder ball. In addition, in the embodiment of the main bridge chip substrate, decoupling capacitors can be disposed at four corners of the power ring or underneath the bonding wires, or can be packaged inside the molding compound.
摘要翻译：本发明涉及一种用于向四层母板和主桥芯片基板提供稳定电源的布局结构。在本发明中，在用于布局主桥芯片和功率环的底部焊料层的顶部信号层和功率路径上，去耦电容器连接在接地焊盘/焊球和电源接合焊盘/ 焊球的动力路径和动力环，从而为主桥芯片的运行提供稳定的电源。在本发明中，与每个电源焊盘/焊球相连的接地焊盘/焊球可以是与功率焊盘/焊球最接近的接地焊盘/焊球。此外，在主桥芯片基板的实施例中，去耦电容器可以设置在电源环的四个角落或者接合线下方，或者可以封装在模制化合物内部。

3. 发明授权

US08335941B2 Method for reducing power consumption of a computer system in the working state 有权
标题翻译：降低工作状态下计算机系统功耗的方法
公开(公告)号：US08335941B2
公开(公告)日：2012-12-18
申请号：US12752201
申请日：2010-04-01
申请人： Nai-Shung Chang , Chia-Hsing Yu
发明人： Nai-Shung Chang , Chia-Hsing Yu
IPC分类号： G06F1/04 , G06F1/12 , G06F5/06
CPC分类号： G06F1/324 , G06F1/3225 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method for reducing power consumption of a computer system in a working state is provided. The computer system comprises a processor, a memory and a chipset, and the processor is connected with the chipset through a processor bus. The method comprises classifying the power saving level of the computer system into a predetermined number of power saving modes, checking at least one power saving mode transition condition to determine whether to automatically raise the power saving mode of the computer system, and raising the power saving mode of the computer system by lowering a first voltage supply level of the chipset and a second voltage supply level of the memory and decreasing a first working frequency of the processor bus and a second working frequency of the memory. The power consumption of the computer system is further reduced in comparison with a normal working state when the power saving mode of the computer system is further raised.
摘要翻译：提供了一种降低处于工作状态的计算机系统的功耗的方法。计算机系统包括处理器，存储器和芯片组，并且处理器通过处理器总线与芯片组连接。该方法包括将计算机系统的省电水平分为预定数量的省电模式，检查至少一个省电模式转换条件，以确定是否自动提高计算机系统的省电模式，并提高节电通过降低芯片组的第一电压供应电平和存储器的第二电压供应电平并降低处理器总线的第一工作频率和存储器的第二工作频率来实现计算机系统的模式。当计算机系统的省电模式进一步提高时，与正常工作状态相比，计算机系统的功耗进一步降低。

4. 发明申请

US20070288782A1 METHOD FOR REDUCING POWER CONSUMPTION OF A COMPUTER SYSTEM IN THE WORKING STATE 有权
标题翻译：降低工作状态下计算机系统功耗的方法
公开(公告)号：US20070288782A1
公开(公告)日：2007-12-13
申请号：US11423722
申请日：2006-06-13
申请人： Nai-Shung Chang , Chia-Hsing Yu
发明人： Nai-Shung Chang , Chia-Hsing Yu
IPC分类号： G06F1/00
CPC分类号： G06F1/324 , G06F1/3225 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method for reducing power consumption of a computer system in a working state is provided. The computer system comprises a processor, a memory and a chipset, and the processor is connected with the chipset through a processor bus. The method comprises classifying the power saving level of the computer system into a predetermined number of power saving modes, checking at least one power saving mode transition condition to determine whether to automatically raise the power saving mode of the computer system, and raising the power saving mode of the computer system by lowering a first voltage supply level of the chipset and a second voltage supply level of the memory and decreasing a first working frequency of the processor bus and a second working frequency of the memory. The power consumption of the computer system is further reduced in comparison with a normal working state when the power saving mode of the computer system is further raised.
摘要翻译：提供了一种降低处于工作状态的计算机系统的功耗的方法。计算机系统包括处理器，存储器和芯片组，并且处理器通过处理器总线与芯片组连接。该方法包括将计算机系统的省电水平分为预定数量的省电模式，检查至少一个省电模式转换条件，以确定是否自动提高计算机系统的省电模式，并提高节电通过降低芯片组的第一电压供应电平和存储器的第二电压供应电平并降低处理器总线的第一工作频率和存储器的第二工作频率来实现计算机系统的模式。当计算机系统的省电模式进一步提高时，与正常工作状态相比，计算机系统的功耗进一步降低。

5. 发明授权

US06944783B2 Power controller and associated multi-processor type supporting computer system 有权
标题翻译：电源控制器和相关的多处理器类型支持计算机系统
公开(公告)号：US06944783B2
公开(公告)日：2005-09-13
申请号：US10037896
申请日：2001-10-22
申请人： Chia-Hsing Yu , Nai-Shung Chang
发明人： Chia-Hsing Yu , Nai-Shung Chang
IPC分类号： G06F1/26
CPC分类号： G06F1/26
摘要： A power controller for a computer system capable of supporting multiple processor types. The power controller receives a voltage identification signal from the microprocessor and a microprocessor selection signal from a motherboard to provide a correct voltage specification signal and terminal voltage to the microprocessor. The invention also provides voltage specification signals and terminal voltages to the motherboard of a computer system that can support a multiple of processor types.
摘要翻译：一种能够支持多种处理器类型的计算机系统的电源控制器。功率控制器接收来自微处理器的电压识别信号和来自母板的微处理器选择信号，以向微处理器提供正确的电压指定信号和端电压。本发明还向可以支持多种处理器类型的计算机系统的主板提供电压指定信号和端电压。

6. 发明授权

US07783905B2 Method for reducing power consumption of a computer system in the working state 有权
标题翻译：降低工作状态下计算机系统功耗的方法
公开(公告)号：US07783905B2
公开(公告)日：2010-08-24
申请号：US11423722
申请日：2006-06-13
申请人： Nai-Shung Chang , Chia-Hsing Yu
发明人： Nai-Shung Chang , Chia-Hsing Yu
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/324 , G06F1/3225 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method for reducing power consumption of a computer system in a working state is provided. The computer system comprises a processor, a memory and a chipset, and the processor is connected with the chipset through a processor bus. The method comprises classifying the power saving level of the computer system into a predetermined number of power saving modes, checking at least one power saving mode transition condition to determine whether to automatically raise the power saving mode of the computer system, and raising the power saving mode of the computer system by lowering a first voltage supply level of the chipset and a second voltage supply level of the memory and decreasing a first working frequency of the processor bus and a second working frequency of the memory. The power consumption of the computer system is further reduced in comparison with a normal working state when the power saving mode of the computer system is further raised.
摘要翻译：提供了一种降低处于工作状态的计算机系统的功耗的方法。计算机系统包括处理器，存储器和芯片组，并且处理器通过处理器总线与芯片组连接。该方法包括将计算机系统的省电水平分为预定数量的省电模式，检查至少一个省电模式转换条件，以确定是否自动提高计算机系统的省电模式，并提高节电通过降低芯片组的第一电压供应电平和存储器的第二电压供应电平并降低处理器总线的第一工作频率和存储器的第二工作频率来实现计算机系统的模式。当计算机系统的省电模式进一步提高时，与正常工作状态相比，计算机系统的功耗进一步降低。

7. 发明授权

US06985987B2 Apparatus and method for supporting multi-processors and motherboard of the same 有权
标题翻译：用于支持多处理器和主板的设备和方法
公开(公告)号：US06985987B2
公开(公告)日：2006-01-10
申请号：US10036168
申请日：2001-10-22
申请人： Nai-Shung Chang , Chia-Hsing Yu
发明人： Nai-Shung Chang , Chia-Hsing Yu
IPC分类号： G06F13/00
CPC分类号： G06F13/4068
摘要： An apparatus and a method for supporting multi-processors and a motherboard using the same are provided. The apparatus receives the pins Z36 and AK36 of the Socket-370 central processing unit to determine which type the Socket-370 central processing unit is. According to the suspend status input signal transmitted from the south bridge of the motherboard, the determined result is latched, and some appropriate circuits are coupled to the Socket-370 central processing unit via a switch circuit. Meanwhile, the suspend status input signal is delayed and used to cut off the connection between the Socket-370 central processing unit and the apparatus. The delayed suspend status input signal is further delayed and then sent to an ATX power supply to activate the whole system.
摘要翻译：提供了一种用于支持多处理器的装置和方法以及使用该处理器的母板。该装置接收Socket-370中央处理单元的引脚Z 36和AK 36以确定Socket-370中央处理单元的类型。根据从主板的南桥传输的暂停状态输入信号，确定结果被锁存，并且一些适当的电路经由开关电路耦合到Socket-370中央处理单元。同时，暂停状态输入信号被延迟并用于切断Socket-370中央处理单元与设备之间的连接。延迟暂停状态输入信号进一步延迟，然后发送到ATX电源以激活整个系统。

8. 发明申请

US20050017980A1 [GRAPHICS DISPLAY ARCHITECTURE AND CONTROL CHIP SET THEREOF] 有权
标题翻译： [图形显示结构及其控制芯片]
公开(公告)号：US20050017980A1
公开(公告)日：2005-01-27
申请号：US10710095
申请日：2004-06-18
申请人： Nai-Shung Chang , Chia-Hsing Yu , Lin Yang
发明人： Nai-Shung Chang , Chia-Hsing Yu , Lin Yang
IPC分类号： G06F3/14 , G06F13/14 , G06F13/36
CPC分类号： G06F3/14
摘要： The graphics display architecture provided by the present invention comprises an AGP slot, a PCIE slot, and a control chip set. The control chip set comprises a plurality of multi-defined pins, which are electrically coupled to the first pins of the AGP slot and the second pins of the PCIE slot simultaneously. When the first graphics adapter is plugged in the AGP slot and the first graphics adapter complies with AGP interface specification, the multi-defined pins serve to send/receive the signal complied with AGP interface specification. When the first graphics adapter is plugged in the AGP slot and the first graphics adapter complies with the Gfx interface, the multi-defined pins serve to send/receive the signal complied with the Gfx interface. When the second graphics adapter is plugged in the PCIE slot, the multi-defined pins serve to send/receive the signal complied wit the PCIE interface specification.
摘要翻译：本发明提供的图形显示架构包括AGP槽，PCIE槽和控制芯片组。控制芯片组包括多个多限定的引脚，它们同时电耦合到AGP插槽的第一引脚和PCIE插槽的第二引脚。当第一个图形适配器插入AGP插槽并且第一个图形适配器符合AGP接口规范时，多重定义的引脚用于发送/接收符合AGP接口规范的信号。当第一个图形适配器插入AGP插槽并且第一个图形适配器符合Gfx接口时，多重定义的引脚用于发送/接收符合Gfx接口的信号。当第二个图形适配器插入PCIE插槽时，多重定义的引脚用于发送/接收符合PCIE接口规范的信号。

9. 发明授权

US06554195B1 Dual processor adapter card 有权
标题翻译：双处理器适配卡
公开(公告)号：US06554195B1
公开(公告)日：2003-04-29
申请号：US09422020
申请日：1999-10-20
申请人： Nai-Shung Chang , Lie-Wen Chen , Ching-Fu Chuang , Chia-Hsing Yu
发明人： Nai-Shung Chang , Lie-Wen Chen , Ching-Fu Chuang , Chia-Hsing Yu
IPC分类号： G06K1906
CPC分类号： G06F1/185 , G06F1/184 , G06F1/186 , H05K1/023 , H05K1/0262 , H05K1/117 , H05K1/141 , H05K3/368 , H05K7/1092 , H05K2201/10022 , H05K2201/10196 , H05K2201/10325 , H05K2201/10689
摘要： A dual processor adapter card with a plurality of electrical pins for inserting into a processor slot on a mainboard by which the adapter card is electrically coupled to the mainboard. There is a first and a second processor socket on the adapter card for carrying a first and a second processor respectively. The first and the second processor socket each has a plurality of corresponding pins, a portion of the pins of the first and the second processor socket corresponds to a portion of the electrical pins. Corresponding pins are coupled together. Furthermore, each of the pins that act as a terminal lead in the first and the second processor socket is connected to a pull-up resistor, and the pull-up resistor is connected to a terminal voltage. In addition, a zero-delay buffer for synchronizing clock pulse signals and a voltage regulator for regulating a power voltage into a suitable working voltage are mounted on the adapter card and coupled to the first and the second processor socket respectively.
摘要翻译：一种双处理器适配器卡，其具有多个电引脚，用于插入到主板上的处理器插槽中，通过该处理器插槽将适配器卡电耦合到主板。适配器卡上有一个第一和第二个处理器插座，分别用于承载第一和第二处理器。第一和第二处理器插座各自具有多个对应的引脚，第一和第二处理器插座的一部分引脚对应于电引脚的一部分。相应的引脚耦合在一起。此外，在第一和第二处理器插座中用作端子引线的每个引脚连接到上拉电阻器，并且上拉电阻器连接到端子电压。此外，用于将时钟脉冲信号同步的零延迟缓冲器和用于将电源电压调节到合适工作电压的电压调节器分别安装在适配器卡上并分别耦合到第一和第二处理器插槽。

10. 发明申请

US20100191988A1 METHOD FOR REDUCING POWER CONSUMPTION OF A COMPUTER SYSTEM IN THE WORKING STATE 有权
标题翻译：降低工作状态下计算机系统功耗的方法
公开(公告)号：US20100191988A1
公开(公告)日：2010-07-29
申请号：US12752201
申请日：2010-04-01
申请人： Nai-Shung Chang , Chia-Hsing Yu
发明人： Nai-Shung Chang , Chia-Hsing Yu
IPC分类号： G06F1/00
CPC分类号： G06F1/324 , G06F1/3225 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method for reducing power consumption of a computer system in a working state is provided. The computer system comprises a processor, a memory and a chipset, and the processor is connected with the chipset through a processor bus. The method comprises classifying the power saving level of the computer system into a predetermined number of power saving modes, checking at least one power saving mode transition condition to determine whether to automatically raise the power saving mode of the computer system, and raising the power saving mode of the computer system by lowering a first voltage supply level of the chipset and a second voltage supply level of the memory and decreasing a first working frequency of the processor bus and a second working frequency of the memory. The power consumption of the computer system is further reduced in comparison with a normal working state when the power saving mode of the computer system is further raised.
摘要翻译：提供了一种降低处于工作状态的计算机系统的功耗的方法。计算机系统包括处理器，存储器和芯片组，并且处理器通过处理器总线与芯片组连接。该方法包括将计算机系统的省电水平分为预定数量的省电模式，检查至少一个省电模式转换条件，以确定是否自动提高计算机系统的省电模式，并提高节电通过降低芯片组的第一电压供应电平和存储器的第二电压供应电平并降低处理器总线的第一工作频率和存储器的第二工作频率来实现计算机系统的模式。当计算机系统的省电模式进一步提高时，与正常工作状态相比，计算机系统的功耗进一步降低。

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