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1. 发明申请

US20050156238A1 Silicide gate transistors and method of manufacture 失效
标题翻译：硅化物栅极晶体管及其制造方法
公开(公告)号：US20050156238A1
公开(公告)日：2005-07-21
申请号：US10753632
申请日：2004-01-08
申请人： Cheng-Kuo Wen , Yee-Chia Yeo , Hsun-Chih Tsao
发明人： Cheng-Kuo Wen , Yee-Chia Yeo , Hsun-Chih Tsao
IPC分类号： H01L21/336 , H01L21/8238 , H01L21/84 , H01L27/12 , H01L29/45 , H01L29/49 , H01L31/0392
CPC分类号： H01L29/66772 , H01L21/823835 , H01L21/84 , H01L27/1203 , H01L29/41783 , H01L29/458 , H01L29/4908
摘要： A method in which a gate and raised source/drain (S/D) regions are fully silicided in separate steps to avoid degrading the resistance or junction leakage is described. A gate dielectric layer, gate, and spacers are formed over a semiconductor layer that is preferably Si, SiGe, or SiGeC on a buried insulator. Raised S/D regions are formed by selective epitaxy between spacers and isolation regions. The gate is protected with a mask while the raised S/D regions are covered with a first metal layer. A first anneal affords fully silicided S/D regions. A dielectric stack is deposited on the substrate and planarized to be coplanar with the top of the spacers. The mask is removed and a second metal layer is deposited. A second anneal yields a fully silicided gate electrode. The invention is also an SOI transistor with silicided raised S/D regions and a fully silicided and optionally recessed gate.
摘要翻译：描述了栅极和升高的源极/漏极（S / D）区域在分开的步骤中完全硅化以避免劣化电阻或结漏电的方法。在掩埋绝缘体上优选Si，SiGe或SiGeC的半导体层上形成栅极电介质层，栅极和间隔物。通过间隔物和隔离区域之间的选择性外延形成凸起的S / D区域。栅极用掩模保护，而凸起的S / D区域被第一金属层覆盖。第一退火提供完全硅化的S / D区域。电介质叠层沉积在衬底上并且平坦化以与间隔物的顶部共面。去除掩模并沉积第二金属层。第二次退火产生完全硅化的栅电极。本发明还是具有硅化凸起的S / D区域和完全硅化并且可选地凹入的栅极的SOI晶体管。

2. 发明申请

US20060194399A1 Silicide Gate Transistors and Method of Manufacture 有权
标题翻译：硅化物栅晶体管及其制造方法
公开(公告)号：US20060194399A1
公开(公告)日：2006-08-31
申请号：US11381649
申请日：2006-05-04
申请人： Cheng-Kuo Wen , Yee-Chia Yeo , Hsun-Chih Tsao
发明人： Cheng-Kuo Wen , Yee-Chia Yeo , Hsun-Chih Tsao
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L21/823835 , H01L21/84 , H01L27/1203 , H01L29/41783 , H01L29/458 , H01L29/4908
摘要： A method in which a gate and raised source/drain (S/D) regions are fully silicided in separate steps to avoid degrading the resistance or junction leakage is described. A gate dielectric layer, gate, and spacers are formed over a semiconductor layer that is preferably Si, SiGe, or SiGeC on a buried insulator. Raised S/D regions are formed by selective epitaxy between spacers and isolation regions. The gate is protected with a mask while the raised S/D regions are covered with a first metal layer. A first anneal affords fully silicided S/D regions. A dielectric stack is deposited on the substrate and planarized to be coplanar with the top of the spacers. The mask is removed and a second metal layer is deposited. A second anneal yields a fully silicided gate electrode. The invention is also an SOI transistor with silicided raised S/D regions and a fully silicided and optionally recessed gate.
摘要翻译：描述了栅极和升高的源极/漏极（S / D）区域在分开的步骤中完全硅化以避免劣化电阻或结漏电的方法。在掩埋绝缘体上优选Si，SiGe或SiGeC的半导体层上形成栅极电介质层，栅极和间隔物。通过间隔物和隔离区域之间的选择性外延形成凸起的S / D区域。栅极用掩模保护，而凸起的S / D区域被第一金属层覆盖。第一退火提供完全硅化的S / D区域。电介质叠层沉积在衬底上并且平坦化以与间隔物的顶部共面。去除掩模并沉积第二金属层。第二次退火产生完全硅化的栅电极。本发明还是具有硅化凸起的S / D区域和完全硅化并且可选地凹入的栅极的SOI晶体管。

3. 发明授权

US07633127B2 Silicide gate transistors and method of manufacture 有权
标题翻译：硅化物栅极晶体管及其制造方法
公开(公告)号：US07633127B2
公开(公告)日：2009-12-15
申请号：US11381649
申请日：2006-05-04
申请人： Cheng-Kuo Wen , Yee-Chia Yeo , Hsun-Chih Tsao
发明人： Cheng-Kuo Wen , Yee-Chia Yeo , Hsun-Chih Tsao
IPC分类号： H01L23/62
CPC分类号： H01L29/66772 , H01L21/823835 , H01L21/84 , H01L27/1203 , H01L29/41783 , H01L29/458 , H01L29/4908
摘要： A method in which a gate and raised source/drain (S/D) regions are fully silicided in separate steps to avoid degrading the resistance or junction leakage is described. A gate dielectric layer, gate, and spacers are formed over a semiconductor layer that is preferably Si, SiGe, or SiGeC on a buried insulator. Raised S/D regions are formed by selective epitaxy between spacers and isolation regions. The gate is protected with a mask while the raised S/D regions are covered with a first metal layer. A first anneal affords fully silicided S/D regions. A dielectric stack is deposited on the substrate and planarized to be coplanar with the top of the spacers. The mask is removed and a second metal layer is deposited. A second anneal yields a fully silicided gate electrode. The invention is also an SOI transistor with silicided raised S/D regions and a fully silicided and optionally recessed gate.
摘要翻译：描述了栅极和升高的源极/漏极（S / D）区域在分开的步骤中完全硅化以避免劣化电阻或结漏电的方法。在掩埋绝缘体上优选Si，SiGe或SiGeC的半导体层上形成栅极电介质层，栅极和间隔物。通过间隔物和隔离区域之间的选择性外延形成凸起的S / D区域。栅极用掩模保护，而凸起的S / D区域被第一金属层覆盖。第一退火提供完全硅化的S / D区域。电介质叠层沉积在衬底上并且平坦化以与间隔物的顶部共面。去除掩模并沉积第二金属层。第二次退火产生完全硅化的栅电极。本发明还是具有硅化凸起的S / D区域和完全硅化并且可选地凹入的栅极的SOI晶体管。

4. 发明授权

US07067379B2 Silicide gate transistors and method of manufacture 失效
公开(公告)号：US07067379B2
公开(公告)日：2006-06-27
申请号：US10753632
申请日：2004-01-08
申请人： Cheng-Kuo Wen , Yee-Chia Yeo , Hsun-Chih Tsao
发明人： Cheng-Kuo Wen , Yee-Chia Yeo , Hsun-Chih Tsao
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/66772 , H01L21/823835 , H01L21/84 , H01L27/1203 , H01L29/41783 , H01L29/458 , H01L29/4908
摘要： A method in which a gate and raised source/drain (S/D) regions are fully silicided in separate steps to avoid degrading the resistance or junction leakage is described. A gate dielectric layer, gate, and spacers are formed over a semiconductor layer that is preferably Si, SiGe, or SiGeC on a buried insulator. Raised S/D regions are formed by selective epitaxy between spacers and isolation regions. The gate is protected with a mask while the raised S/D regions are covered with a first metal layer. A first anneal affords fully silicided S/D regions. A dielectric stack is deposited on the substrate and planarized to be coplanar with the top of the spacers. The mask is removed and a second metal layer is deposited. A second anneal yields a fully silicided gate electrode. The invention is also an SOI transistor with silicided raised S/D regions and a fully silicided and optionally recessed gate.

5. 发明授权

US06979867B2 SOI chip with mesa isolation and recess resistant regions 有权
公开(公告)号：US06979867B2
公开(公告)日：2005-12-27
申请号：US11022730
申请日：2004-12-27
申请人： Yee-Chia Yeo , Hao-Yu Chen , Hsun-Chih Tsao , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Hao-Yu Chen , Hsun-Chih Tsao , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/762 , H01L21/84 , H01L27/12 , H01L29/786 , H01L23/58
CPC分类号： H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/78603
摘要： A semiconductor-on-insulator structure includes a substrate and a buried insulator layer overlying the substrate. A plurality of semiconductor islands overlie the buried insulator layer. The semiconductor islands are isolated from one another by trenches. A plurality of recess resistant regions overlie the buried insulator layer at a lower surface of the trenches.

6. 发明申请

US20050101111A1 SOI chip with mesa isolation and recess resistant regions 有权
公开(公告)号：US20050101111A1
公开(公告)日：2005-05-12
申请号：US11022730
申请日：2004-12-27
申请人： Yee-Chia Yeo , Hao-Yu Chen , Hsun-Chih Tsao , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Hao-Yu Chen , Hsun-Chih Tsao , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/762 , H01L21/84 , H01L27/12 , H01L29/786 , H01L21/20
CPC分类号： H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/78603
摘要： A semiconductor-on-insulator structure includes a substrate and a buried insulator layer overlying the substrate. A plurality of semiconductor islands overlie the buried insulator layer. The semiconductor islands are isolated from one another by trenches. A plurality of recess resistant regions overlie the buried insulator layer at a lower surface of the trenches.

7. 发明授权

US06864149B2 SOI chip with mesa isolation and recess resistant regions 有权
标题翻译： SOI芯片具有台面隔离和抗凹陷区域
公开(公告)号：US06864149B2
公开(公告)日：2005-03-08
申请号：US10435286
申请日：2003-05-09
申请人： Yee-Chia Yeo , Hao-Yu Chen , Hsun-Chih Tsao , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Hao-Yu Chen , Hsun-Chih Tsao , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/762 , H01L21/84 , H01L27/12 , H01L29/786 , H01L21/76
CPC分类号： H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/78603
摘要： A semiconductor-on-insulator structure includes a substrate and a buried insulator layer overlying the substrate. A plurality of semiconductor islands overlie the buried insulator layer. The semiconductor islands are isolated from one another by trenches. A plurality of recess resistant regions overlie the buried insulator layer at a lower surface of the trenches.
摘要翻译：绝缘体上半导体结构包括衬底和覆盖在衬底上的掩埋绝缘体层。多个半导体岛覆盖在埋层绝缘体层上。半导体岛通过沟槽彼此隔离。多个凹陷区域覆盖在沟槽的下表面处的掩埋绝缘体层。

8. 发明授权

US08084305B2 Isolation spacer for thin SOI devices 有权
标题翻译：用于薄SOI器件的隔离间隔
公开(公告)号：US08084305B2
公开(公告)日：2011-12-27
申请号：US12036616
申请日：2008-02-25
申请人： Chih-Hsin Ko , Wen-Chin Lee , Yee-Chia Yeo , Chung-Hu Ke
发明人： Chih-Hsin Ko , Wen-Chin Lee , Yee-Chia Yeo , Chung-Hu Ke
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/66772 , H01L27/1203 , H01L29/78618 , Y10S257/90
摘要： A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the semiconductor mesa and filling any undercut region at edges of the semiconductor mesa.
摘要翻译：半导体器件包括覆盖介电层的半导体台面，形成在半导体台面上的栅叠层，以及形成在半导体台面周围的隔离间隔物，并填充半导体台面的边缘处的任何底切区域。

9. 发明授权

US07851276B2 Methods and structures for planar and multiple-gate transistors formed on SOI 有权
标题翻译：在SOI上形成的平面和多栅极晶体管的方法和结构
公开(公告)号：US07851276B2
公开(公告)日：2010-12-14
申请号：US11676480
申请日：2007-02-19
申请人： Fu-Liang Yang , Yee-Chia Yeo , Chenming Hu
发明人： Fu-Liang Yang , Yee-Chia Yeo , Chenming Hu
IPC分类号： H01L21/00 , H01L21/48
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/66795 , H01L29/785 , H01L29/7854
摘要： A semiconductor device includes an insulator layer, a semiconductor layer, a first transistor, and a second transistor. The semiconductor layer is overlying the insulator layer. A first portion of the semiconductor layer has a first thickness. A second portion of the semiconductor layer has a second thickness. The second thickness is larger than the first thickness. The first transistor has a first active region formed from the first portion of the semiconductor layer. The second transistor has a second active region formed from the second portion of the semiconductor layer. The first transistor may be a planar transistor and the second transistor may be a multiple-gate transistor, for example.
摘要翻译：半导体器件包括绝缘体层，半导体层，第一晶体管和第二晶体管。半导体层覆盖绝缘体层。半导体层的第一部分具有第一厚度。半导体层的第二部分具有第二厚度。第二厚度大于第一厚度。第一晶体管具有由半导体层的第一部分形成的第一有源区。第二晶体管具有由半导体层的第二部分形成的第二有源区。第一晶体管可以是平面晶体管，例如，第二晶体管可以是多栅极晶体管。

10. 发明申请

US20100176424A1 Doping of Semiconductor Fin Devices 有权
标题翻译：半导体鳍片器件的掺杂
公开(公告)号：US20100176424A1
公开(公告)日：2010-07-15
申请号：US12732011
申请日：2010-03-25
申请人： Yee-Chia Yeo , Ping-Wei Wang , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Ping-Wei Wang , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L29/786 , H01L29/04
CPC分类号： H01L29/785 , H01L21/26586 , H01L29/66803
摘要： A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.
摘要翻译：半导体结构包括覆盖绝缘体层的多个半导体鳍片，覆盖所述半导体鳍片的一部分的栅极电介质和覆盖栅极电介质的栅电极。每个半导体翅片具有顶表面，第一侧壁表面和第二侧壁表面。掺杂离子相对于半导体鳍片的顶表面的法线以第一角度（例如，大于约7°）注入，以掺杂第一侧壁表面和顶表面。相对于半导体鳍片的顶表面的法线注入另外的掺杂剂离子以掺杂第二侧壁表面和顶表面。

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