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    • 1. 发明申请
    • Silicide gate transistors and method of manufacture
    • 硅化物栅极晶体管及其制造方法
    • US20050156238A1
    • 2005-07-21
    • US10753632
    • 2004-01-08
    • Cheng-Kuo WenYee-Chia YeoHsun-Chih Tsao
    • Cheng-Kuo WenYee-Chia YeoHsun-Chih Tsao
    • H01L21/336H01L21/8238H01L21/84H01L27/12H01L29/45H01L29/49H01L31/0392
    • H01L29/66772H01L21/823835H01L21/84H01L27/1203H01L29/41783H01L29/458H01L29/4908
    • A method in which a gate and raised source/drain (S/D) regions are fully silicided in separate steps to avoid degrading the resistance or junction leakage is described. A gate dielectric layer, gate, and spacers are formed over a semiconductor layer that is preferably Si, SiGe, or SiGeC on a buried insulator. Raised S/D regions are formed by selective epitaxy between spacers and isolation regions. The gate is protected with a mask while the raised S/D regions are covered with a first metal layer. A first anneal affords fully silicided S/D regions. A dielectric stack is deposited on the substrate and planarized to be coplanar with the top of the spacers. The mask is removed and a second metal layer is deposited. A second anneal yields a fully silicided gate electrode. The invention is also an SOI transistor with silicided raised S/D regions and a fully silicided and optionally recessed gate.
    • 描述了栅极和升高的源极/漏极(S / D)区域在分开的步骤中完全硅化以避免劣化电阻或结漏电的方法。 在掩埋绝缘体上优选Si,SiGe或SiGeC的半导体层上形成栅极电介质层,栅极和间隔物。 通过间隔物和隔离区域之间的选择性外延形成凸起的S / D区域。 栅极用掩模保护,而凸起的S / D区域被第一金属层覆盖。 第一退火提供完全硅化的S / D区域。 电介质叠层沉积在衬底上并且平坦化以与间隔物的顶部共面。 去除掩模并沉积第二金属层。 第二次退火产生完全硅化的栅电极。 本发明还是具有硅化凸起的S / D区域和完全硅化并且可选地凹入的栅极的SOI晶体管。
    • 2. 发明申请
    • Silicide Gate Transistors and Method of Manufacture
    • 硅化物栅晶体管及其制造方法
    • US20060194399A1
    • 2006-08-31
    • US11381649
    • 2006-05-04
    • Cheng-Kuo WenYee-Chia YeoHsun-Chih Tsao
    • Cheng-Kuo WenYee-Chia YeoHsun-Chih Tsao
    • H01L21/336
    • H01L29/66772H01L21/823835H01L21/84H01L27/1203H01L29/41783H01L29/458H01L29/4908
    • A method in which a gate and raised source/drain (S/D) regions are fully silicided in separate steps to avoid degrading the resistance or junction leakage is described. A gate dielectric layer, gate, and spacers are formed over a semiconductor layer that is preferably Si, SiGe, or SiGeC on a buried insulator. Raised S/D regions are formed by selective epitaxy between spacers and isolation regions. The gate is protected with a mask while the raised S/D regions are covered with a first metal layer. A first anneal affords fully silicided S/D regions. A dielectric stack is deposited on the substrate and planarized to be coplanar with the top of the spacers. The mask is removed and a second metal layer is deposited. A second anneal yields a fully silicided gate electrode. The invention is also an SOI transistor with silicided raised S/D regions and a fully silicided and optionally recessed gate.
    • 描述了栅极和升高的源极/漏极(S / D)区域在分开的步骤中完全硅化以避免劣化电阻或结漏电的方法。 在掩埋绝缘体上优选Si,SiGe或SiGeC的半导体层上形成栅极电介质层,栅极和间隔物。 通过间隔物和隔离区域之间的选择性外延形成凸起的S / D区域。 栅极用掩模保护,而凸起的S / D区域被第一金属层覆盖。 第一退火提供完全硅化的S / D区域。 电介质叠层沉积在衬底上并且平坦化以与间隔物的顶部共面。 去除掩模并沉积第二金属层。 第二次退火产生完全硅化的栅电极。 本发明还是具有硅化凸起的S / D区域和完全硅化并且可选地凹入的栅极的SOI晶体管。
    • 3. 发明授权
    • Silicide gate transistors and method of manufacture
    • 硅化物栅极晶体管及其制造方法
    • US07633127B2
    • 2009-12-15
    • US11381649
    • 2006-05-04
    • Cheng-Kuo WenYee-Chia YeoHsun-Chih Tsao
    • Cheng-Kuo WenYee-Chia YeoHsun-Chih Tsao
    • H01L23/62
    • H01L29/66772H01L21/823835H01L21/84H01L27/1203H01L29/41783H01L29/458H01L29/4908
    • A method in which a gate and raised source/drain (S/D) regions are fully silicided in separate steps to avoid degrading the resistance or junction leakage is described. A gate dielectric layer, gate, and spacers are formed over a semiconductor layer that is preferably Si, SiGe, or SiGeC on a buried insulator. Raised S/D regions are formed by selective epitaxy between spacers and isolation regions. The gate is protected with a mask while the raised S/D regions are covered with a first metal layer. A first anneal affords fully silicided S/D regions. A dielectric stack is deposited on the substrate and planarized to be coplanar with the top of the spacers. The mask is removed and a second metal layer is deposited. A second anneal yields a fully silicided gate electrode. The invention is also an SOI transistor with silicided raised S/D regions and a fully silicided and optionally recessed gate.
    • 描述了栅极和升高的源极/漏极(S / D)区域在分开的步骤中完全硅化以避免劣化电阻或结漏电的方法。 在掩埋绝缘体上优选Si,SiGe或SiGeC的半导体层上形成栅极电介质层,栅极和间隔物。 通过间隔物和隔离区域之间的选择性外延形成凸起的S / D区域。 栅极用掩模保护,而凸起的S / D区域被第一金属层覆盖。 第一退火提供完全硅化的S / D区域。 电介质叠层沉积在衬底上并且平坦化以与间隔物的顶部共面。 去除掩模并沉积第二金属层。 第二次退火产生完全硅化的栅电极。 本发明还是具有硅化凸起的S / D区域和完全硅化并且可选地凹入的栅极的SOI晶体管。