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1. 发明授权

US06864149B2 SOI chip with mesa isolation and recess resistant regions 有权
标题翻译： SOI芯片具有台面隔离和抗凹陷区域
公开(公告)号：US06864149B2
公开(公告)日：2005-03-08
申请号：US10435286
申请日：2003-05-09
申请人： Yee-Chia Yeo , Hao-Yu Chen , Hsun-Chih Tsao , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Hao-Yu Chen , Hsun-Chih Tsao , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/762 , H01L21/84 , H01L27/12 , H01L29/786 , H01L21/76
CPC分类号： H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/78603
摘要： A semiconductor-on-insulator structure includes a substrate and a buried insulator layer overlying the substrate. A plurality of semiconductor islands overlie the buried insulator layer. The semiconductor islands are isolated from one another by trenches. A plurality of recess resistant regions overlie the buried insulator layer at a lower surface of the trenches.
摘要翻译：绝缘体上半导体结构包括衬底和覆盖在衬底上的掩埋绝缘体层。多个半导体岛覆盖在埋层绝缘体层上。半导体岛通过沟槽彼此隔离。多个凹陷区域覆盖在沟槽的下表面处的掩埋绝缘体层。

2. 发明申请

US20050101111A1 SOI chip with mesa isolation and recess resistant regions 有权
公开(公告)号：US20050101111A1
公开(公告)日：2005-05-12
申请号：US11022730
申请日：2004-12-27
申请人： Yee-Chia Yeo , Hao-Yu Chen , Hsun-Chih Tsao , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Hao-Yu Chen , Hsun-Chih Tsao , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/762 , H01L21/84 , H01L27/12 , H01L29/786 , H01L21/20
CPC分类号： H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/78603
摘要： A semiconductor-on-insulator structure includes a substrate and a buried insulator layer overlying the substrate. A plurality of semiconductor islands overlie the buried insulator layer. The semiconductor islands are isolated from one another by trenches. A plurality of recess resistant regions overlie the buried insulator layer at a lower surface of the trenches.

3. 发明授权

US06979867B2 SOI chip with mesa isolation and recess resistant regions 有权
公开(公告)号：US06979867B2
公开(公告)日：2005-12-27
申请号：US11022730
申请日：2004-12-27
申请人： Yee-Chia Yeo , Hao-Yu Chen , Hsun-Chih Tsao , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Hao-Yu Chen , Hsun-Chih Tsao , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/762 , H01L21/84 , H01L27/12 , H01L29/786 , H01L23/58
CPC分类号： H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/78603
摘要： A semiconductor-on-insulator structure includes a substrate and a buried insulator layer overlying the substrate. A plurality of semiconductor islands overlie the buried insulator layer. The semiconductor islands are isolated from one another by trenches. A plurality of recess resistant regions overlie the buried insulator layer at a lower surface of the trenches.

4. 发明授权

US08790970B2 Doping of semiconductor fin devices 有权
标题翻译：掺杂半导体鳍片器件
公开(公告)号：US08790970B2
公开(公告)日：2014-07-29
申请号：US11446697
申请日：2006-06-05
申请人： Yee-Chia Yeo , Ping-Wei Wang , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Ping-Wei Wang , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L21/26586 , H01L29/66803
摘要： A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.
摘要翻译：半导体结构包括覆盖绝缘体层的多个半导体鳍片，覆盖所述半导体鳍片的一部分的栅极电介质和覆盖栅极电介质的栅电极。每个半导体翅片具有顶表面，第一侧壁表面和第二侧壁表面。掺杂离子相对于半导体鳍片的顶表面的法线以第一角度（例如，大于约7°）注入，以掺杂第一侧壁表面和顶表面。相对于半导体鳍片的顶表面的法线注入另外的掺杂剂离子以掺杂第二侧壁表面和顶表面。

5. 发明申请

US20070111454A1 Gate electrode for a semiconductor fin device 有权
标题翻译：用于半导体鳍片器件的栅电极
公开(公告)号：US20070111454A1
公开(公告)日：2007-05-17
申请号：US11649453
申请日：2007-01-03
申请人： Yee-Chia Yeo , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method for forming a gate electrode for a multiple gate transistor provides a doped, planarized gate electrode material which may be patterned using conventional methods to produce a gate electrode that straddles the active area of the multiple gate transistor and has a constant transistor gate length. The method includes forming a layer of gate electrode material having a non-planar top surface, over a semiconductor fin. The method further includes planarizing and doping the gate electrode material, without doping the source/drain active areas, then patterning the gate electrode material. Planarization of the gate electrode material may take place prior to the introduction and activation of dopant impurities or it may follow the introduction arid activation of dopant impurities. After the gate electrode is patterned, dopant impurities are selectively introduced to the semiconductor fin to form source/drain regions.
摘要翻译：用于形成多栅极晶体管的栅电极的方法提供掺杂的平面化栅电极材料，其可以使用常规方法进行图案化以产生跨越多栅极晶体管的有源区并具有恒定晶体管栅极长度的栅电极。该方法包括在半导体鳍上形成具有非平面顶表面的栅电极材料层。该方法还包括对栅电极材料进行平面化和掺杂，而不掺杂源极/漏极有源区，然后对栅电极材料进行构图。栅电极材料的平面化可以在引入和激活掺杂剂杂质之前进行，或者可以引入和掺杂杂质的激活。在栅电极被图案化之后，掺杂剂杂质被选择性地引入半导体鳍片以形成源极/漏极区域。

6. 发明申请

US20060220133A1 Doping of semiconductor fin devices 有权
公开(公告)号：US20060220133A1
公开(公告)日：2006-10-05
申请号：US11446890
申请日：2006-06-05
申请人： Yee-Chia Yeo , Ping-Wei Wang , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Ping-Wei Wang , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L27/12
CPC分类号： H01L29/785 , H01L21/26586 , H01L29/66803
摘要： A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.

7. 发明申请

US20100176424A1 Doping of Semiconductor Fin Devices 有权
标题翻译：半导体鳍片器件的掺杂
公开(公告)号：US20100176424A1
公开(公告)日：2010-07-15
申请号：US12732011
申请日：2010-03-25
申请人： Yee-Chia Yeo , Ping-Wei Wang , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Ping-Wei Wang , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L29/786 , H01L29/04
CPC分类号： H01L29/785 , H01L21/26586 , H01L29/66803
摘要： A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.
摘要翻译：半导体结构包括覆盖绝缘体层的多个半导体鳍片，覆盖所述半导体鳍片的一部分的栅极电介质和覆盖栅极电介质的栅电极。每个半导体翅片具有顶表面，第一侧壁表面和第二侧壁表面。掺杂离子相对于半导体鳍片的顶表面的法线以第一角度（例如，大于约7°）注入，以掺杂第一侧壁表面和顶表面。相对于半导体鳍片的顶表面的法线注入另外的掺杂剂离子以掺杂第二侧壁表面和顶表面。

8. 发明授权

US07701008B2 Doping of semiconductor fin devices 有权
标题翻译：掺杂半导体鳍片器件
公开(公告)号：US07701008B2
公开(公告)日：2010-04-20
申请号：US11446890
申请日：2006-06-05
申请人： Yee-Chia Yeo , Ping-Wei Wang , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Ping-Wei Wang , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L21/26586 , H01L29/66803
摘要： A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.
摘要翻译：半导体结构包括覆盖绝缘体层的多个半导体鳍片，覆盖所述半导体鳍片的一部分的栅极电介质和覆盖栅极电介质的栅电极。每个半导体翅片具有顶表面，第一侧壁表面和第二侧壁表面。掺杂离子相对于半导体鳍片的顶表面的法线以第一角度（例如，大于约7°）注入，以掺杂第一侧壁表面和顶表面。相对于半导体鳍片的顶表面的法线注入另外的掺杂剂离子以掺杂第二侧壁表面和顶表面。

9. 发明授权

US07423323B2 Semiconductor device with raised segment 有权
标题翻译：具有凸起部分的半导体器件
公开(公告)号：US07423323B2
公开(公告)日：2008-09-09
申请号：US11064489
申请日：2005-02-23
申请人： Hao-Yu Chen , Yee-Chia Yeo , Fu-Liang Yang , Chenming Hu
发明人： Hao-Yu Chen , Yee-Chia Yeo , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/336
CPC分类号： H01L29/78618 , H01L21/84 , H01L27/1203 , H01L29/66628 , H01L29/66772 , H01L29/78684
摘要： A device having a raised segment, and a manufacturing method for same. An SOI wafer is provided having a substrate, an insulating layer disposed over the substrate, and a layer of semiconductor material disposed over the insulating layer. The semiconductor material is patterned to form a mesa structure. The wafer is annealed to form a raised segment on the mesa structure.
摘要翻译：具有凸起部分的装置及其制造方法。提供SOI晶片，其具有衬底，设置在衬底上的绝缘层和设置在绝缘层上的半导体材料层。图案化半导体材料以形成台面结构。将晶片退火以在台面结构上形成凸起的段。

10. 发明授权

US07176092B2 Gate electrode for a semiconductor fin device 有权
标题翻译：用于半导体鳍片器件的栅电极
公开(公告)号：US07176092B2
公开(公告)日：2007-02-13
申请号：US10825872
申请日：2004-04-16
申请人： Yee-Chia Yeo , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method for forming a gate electrode for a multiple gate transistor provides a doped, planarized gate electrode material which may be patterned using conventional methods to produce a gate electrode that straddles the active area of the multiple gate transistor and has a constant transistor gate length. The method includes forming a layer of gate electrode material having a non-planar top surface, over a semiconductor fin. The method further includes planarizing and doping the gate electrode material, without doping the source/drain active areas, then patterning the gate electrode material. Planarization of the gate electrode material may take place prior to the introduction and activation of dopant impurities or it may follow the introduction and activation of dopant impurities. After the gate electrode is patterned, dopant impurities are selectively introduced to the semiconductor fin to form source/drain regions.
摘要翻译：用于形成多栅极晶体管的栅电极的方法提供掺杂的平面化栅电极材料，其可以使用常规方法进行图案化以产生跨越多栅极晶体管的有源区并具有恒定晶体管栅极长度的栅电极。该方法包括在半导体鳍上形成具有非平面顶表面的栅电极材料层。该方法还包括对栅电极材料进行平面化和掺杂，而不掺杂源极/漏极有源区，然后对栅电极材料进行构图。栅极电极材料的平面化可以在引入和激活掺杂剂杂质之前进行，或者可以跟随掺杂剂杂质的引入和激活。在栅电极被图案化之后，掺杂剂杂质被选择性地引入半导体鳍片以形成源极/漏极区域。

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