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    • 5. 发明申请
    • Gate electrode for a semiconductor fin device
    • 用于半导体鳍片器件的栅电极
    • US20070111454A1
    • 2007-05-17
    • US11649453
    • 2007-01-03
    • Yee-Chia YeoHao-Yu ChenFu-Liang YangChenming Hu
    • Yee-Chia YeoHao-Yu ChenFu-Liang YangChenming Hu
    • H01L21/336
    • H01L29/785H01L29/66795
    • A method for forming a gate electrode for a multiple gate transistor provides a doped, planarized gate electrode material which may be patterned using conventional methods to produce a gate electrode that straddles the active area of the multiple gate transistor and has a constant transistor gate length. The method includes forming a layer of gate electrode material having a non-planar top surface, over a semiconductor fin. The method further includes planarizing and doping the gate electrode material, without doping the source/drain active areas, then patterning the gate electrode material. Planarization of the gate electrode material may take place prior to the introduction and activation of dopant impurities or it may follow the introduction arid activation of dopant impurities. After the gate electrode is patterned, dopant impurities are selectively introduced to the semiconductor fin to form source/drain regions.
    • 用于形成多栅极晶体管的栅电极的方法提供掺杂的平面化栅电极材料,其可以使用常规方法进行图案化以产生跨越多栅极晶体管的有源区并具有恒定晶体管栅极长度的栅电极。 该方法包括在半导体鳍上形成具有非平面顶表面的栅电极材料层。 该方法还包括对栅电极材料进行平面化和掺杂,而不掺杂源极/漏极有源区,然后对栅电极材料进行构图。 栅电极材料的平面化可以在引入和激活掺杂剂杂质之前进行,或者可以引入和掺杂杂质的激活。 在栅电极被图案化之后,掺杂剂杂质被选择性地引入半导体鳍片以形成源极/漏极区域。
    • 10. 发明授权
    • Gate electrode for a semiconductor fin device
    • 用于半导体鳍片器件的栅电极
    • US07176092B2
    • 2007-02-13
    • US10825872
    • 2004-04-16
    • Yee-Chia YeoHao-Yu ChenFu-Liang YangChenming Hu
    • Yee-Chia YeoHao-Yu ChenFu-Liang YangChenming Hu
    • H01L21/336
    • H01L29/785H01L29/66795
    • A method for forming a gate electrode for a multiple gate transistor provides a doped, planarized gate electrode material which may be patterned using conventional methods to produce a gate electrode that straddles the active area of the multiple gate transistor and has a constant transistor gate length. The method includes forming a layer of gate electrode material having a non-planar top surface, over a semiconductor fin. The method further includes planarizing and doping the gate electrode material, without doping the source/drain active areas, then patterning the gate electrode material. Planarization of the gate electrode material may take place prior to the introduction and activation of dopant impurities or it may follow the introduction and activation of dopant impurities. After the gate electrode is patterned, dopant impurities are selectively introduced to the semiconductor fin to form source/drain regions.
    • 用于形成多栅极晶体管的栅电极的方法提供掺杂的平面化栅电极材料,其可以使用常规方法进行图案化以产生跨越多栅极晶体管的有源区并具有恒定晶体管栅极长度的栅电极。 该方法包括在半导体鳍上形成具有非平面顶表面的栅电极材料层。 该方法还包括对栅电极材料进行平面化和掺杂,而不掺杂源极/漏极有源区,然后对栅电极材料进行构图。 栅极电极材料的平面化可以在引入和激活掺杂剂杂质之前进行,或者可以跟随掺杂剂杂质的引入和激活。 在栅电极被图案化之后,掺杂剂杂质被选择性地引入半导体鳍片以形成源极/漏极区域。