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1. 发明授权

US07663185B2 FIN-FET device structure formed employing bulk semiconductor substrate 有权
标题翻译：使用体半导体衬底形成的FIN-FET器件结构
公开(公告)号：US07663185B2
公开(公告)日：2010-02-16
申请号：US11441724
申请日：2006-05-27
申请人： Kuang-Hsin Chen , Hsun-Chih Tsao , Jhi-Cherng Lu , Chuan-Ping Hou , Peng-Fu Hsu , Hung-Wei Chen , Di-Hong Lee
发明人： Kuang-Hsin Chen , Hsun-Chih Tsao , Jhi-Cherng Lu , Chuan-Ping Hou , Peng-Fu Hsu , Hung-Wei Chen , Di-Hong Lee
IPC分类号： H01L29/76
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A fin-FET device and a method for fabrication thereof both employ a bulk semiconductor substrate. A fin and an adjoining trough are formed within the bulk semiconductor substrate. The trough is partially backfilled with a deposited dielectric layer to form an exposed fin region and an unexposed fin region. A gate dielectric layer is formed upon the exposed fin region and a gate electrode is formed upon the gate dielectric layer. By employing a bulk semiconductor substrate the fin-FET device is fabricated cost effectively.
摘要翻译：翅片FET器件及其制造方法都采用体半导体衬底。在体半导体衬底内形成翅片和相邻的槽。槽部分地用沉积的介电层回填以形成暴露的翅片区域和未曝光的翅片区域。在暴露的散热片区域上形成栅极电介质层，在栅极电介质层上形成栅电极。通过采用体半导体衬底，成本有效地制造了鳍式FET器件。

2. 发明授权

US07332777B2 STI liner for SOI structure 有权
标题翻译： STI衬垫为SOI结构
公开(公告)号：US07332777B2
公开(公告)日：2008-02-19
申请号：US11221200
申请日：2005-09-07
申请人： Kuang-Hsin Chen , Hsun-Chih Tsao , Hung-Wei Chen , Di-Hong Lee , Chuan-Ping Hou , Jhi-Cherng Lu
发明人： Kuang-Hsin Chen , Hsun-Chih Tsao , Hung-Wei Chen , Di-Hong Lee , Chuan-Ping Hou , Jhi-Cherng Lu
IPC分类号： H01L31/0392
CPC分类号： H01L21/76224 , H01L21/84
摘要： In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.
摘要翻译：在制造半导体器件的方法中，提供了初始结构。初始结构包括衬底，图案化硅层和覆盖层。基板上形成有埋置的绝缘体层。图案化的硅层形成在掩埋绝缘体层上。覆盖层形成在图案化硅层上。在初始结构上形成第一层。通过蚀刻工艺去除第一层的一部分，使得图案化硅层的侧壁部分被暴露，并且使得第一层的剩余部分保留在图案化硅层与掩埋绝缘体层接合的拐角处。在暴露的侧壁部分上形成氧化物衬垫。可以在掩埋绝缘体层（在形成第一层之前）形成凹部，并且可以在图案化的硅层的部分下方延伸。

3. 发明申请

US20060278915A1 FinFET split gate EEPROM structure and method of its fabrication 有权
标题翻译： FinFET分裂门EEPROM结构及其制作方法
公开(公告)号：US20060278915A1
公开(公告)日：2006-12-14
申请号：US11148903
申请日：2005-06-09
申请人： Di-Hong Lee , Hsun-Chih Tsao , Kuang-Hsin Chen , Hung-Wei Chen
发明人： Di-Hong Lee , Hsun-Chih Tsao , Kuang-Hsin Chen , Hung-Wei Chen
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/7881 , H01L21/28273 , H01L29/42328 , H01L29/66795 , H01L29/66825 , H01L29/785
摘要： A FinFET split gate EEPROM structure includes a semiconductor substrate and an elongated semiconductor fin extending above the substrate. A control gate straddles the fin, the fin's sides and a first drain-proximate portion of a channel between a source and drain in the fin. The control gate includes a tunnel layer and a floating electrode over which are a first insulative stratum and a first conductive stratum. A select gate straddles the fin and its sides and a second, source-promixate portion of the channel. The select gate includes a second insulative stratum and a second conductive stratum. The insulative strata are portions of a continuous insulative layer covering the substrate and the fin. The conductive strata are electrically continuous portions of a continuous conductive layer formed on the insulative layer.
摘要翻译： FinFET分离栅极EEPROM结构包括半导体衬底和在衬底上延伸的细长半导体鳍片。控制栅极横跨鳍片，翅片的侧面以及翅片中的源极和漏极之间的通道的第一漏极 - 近似部分。控制门包括隧道层和浮动电极，第一绝缘层和第一导电层在其上形成。选择栅极横跨鳍片及其侧面以及通道的第二个源极扩展部分。选择门包括第二绝缘层和第二导电层。绝缘层是覆盖基板和翅片的连续绝缘层的部分。导电层是形成在绝缘层上的连续导电层的电连续部分。

4. 发明申请

US20060214226A1 Method for forming an SOI structure with improved carrier mobility and ESD protection 有权
公开(公告)号：US20060214226A1
公开(公告)日：2006-09-28
申请号：US11089405
申请日：2005-03-23
申请人： Hung-Wei Chen , Hsun-Chih Tsao , Kuang-Hsin Chen , Di-Hong Lee
发明人： Hung-Wei Chen , Hsun-Chih Tsao , Kuang-Hsin Chen , Di-Hong Lee
IPC分类号： H01L29/04 , H01L21/84
CPC分类号： H01L29/045 , H01L21/823807 , H01L21/84 , H01L27/0251 , H01L27/1203 , H01L27/1207 , H01L29/7843 , H01L29/7851 , H01L29/7854
摘要： A semiconductor device and method for forming the same including improved electrostatic discharge protection for advanced semiconductor devices, the semiconductor device including providing semiconductor substrate having a pre-selected surface orientation and crystal direction; an insulator layer overlying the semiconductor substrate; a first semiconductor active region overlying the insulator layer having a first surface orientation selected from the group consisting of and ; a second semiconductor active region extending through a thickness portion of the insulator layer having a second surface orientation selected from the group consisting of and different from the first surface orientation; wherein MOS devices including a first MOS device of a first conduction type is disposed on the first semiconductor active region and a second MOS device of a second conduction type is disposed on the second semiconductor active region.

5. 发明授权

US07026196B2 Method of forming field effect transistor and structure formed thereby 失效
标题翻译：形成场效应晶体管的方法及由此形成的结构
公开(公告)号：US07026196B2
公开(公告)日：2006-04-11
申请号：US10720775
申请日：2003-11-24
申请人： Chuan-Ping Hou , Jhi-Cherng Lu , Kuang-Hsin Chen , Hsun-Chih Tsao
发明人： Chuan-Ping Hou , Jhi-Cherng Lu , Kuang-Hsin Chen , Hsun-Chih Tsao
IPC分类号： H01L21/84
CPC分类号： H01L29/7853 , H01L21/84 , H01L27/1203 , H01L29/66795
摘要： A method for forming a field effect transistor includes: forming a conductive region on an isolation layer formed on a substrate, and a cap dielectric layer on the conductive region; forming a sacrificial dielectric layer over the isolation layer and the cap dielectric layer, and on sidewalls of the conductive region; removing a portion of the sacrificial dielectric layer on the cap dielectric layer; removing the cap dielectric layer; removing remaining portions of the sacrificial dielectric layer; forming a gate on the conductive region; and forming source/drain (S/D) regions within the conductive region and adjacent to the gate. A field effect transistor includes a conductive region over an isolation layer formed on a substrate, the conductive region being substantially without undercut at the region within the isolation layer beneath the conductive region; a gate on the conductive region; and S/D regions within the conductive region and adjacent to the gate.
摘要翻译：一种用于形成场效应晶体管的方法，包括：在形成于基板上的隔离层上形成导电区域，在导电区域上形成盖电介质层; 在所述隔离层和所述盖电介质层上以及所述导电区域的侧壁上形成牺牲介电层; 去除所述帽介电层上的牺牲介电层的一部分; 去除所述盖电介质层; 去除牺牲介电层的剩余部分; 在导电区上形成栅极; 以及在所述导电区域内并且邻近所述栅极形成源极/漏极（S / D）区域。场效应晶体管包括在衬底上形成的隔离层上的导电区域，该导电区域在导电区域下面的隔离层内的区域基本上没有底切; 导电区域上的栅极; 和导电区域内的S / D区域并且与栅极相邻。

6. 发明申请

US20050101111A1 SOI chip with mesa isolation and recess resistant regions 有权
公开(公告)号：US20050101111A1
公开(公告)日：2005-05-12
申请号：US11022730
申请日：2004-12-27
申请人： Yee-Chia Yeo , Hao-Yu Chen , Hsun-Chih Tsao , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Hao-Yu Chen , Hsun-Chih Tsao , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/762 , H01L21/84 , H01L27/12 , H01L29/786 , H01L21/20
CPC分类号： H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/78603
摘要： A semiconductor-on-insulator structure includes a substrate and a buried insulator layer overlying the substrate. A plurality of semiconductor islands overlie the buried insulator layer. The semiconductor islands are isolated from one another by trenches. A plurality of recess resistant regions overlie the buried insulator layer at a lower surface of the trenches.

7. 发明授权

US07205601B2 FinFET split gate EEPROM structure and method of its fabrication 有权
标题翻译： FinFET分裂门EEPROM结构及其制作方法
公开(公告)号：US07205601B2
公开(公告)日：2007-04-17
申请号：US11148903
申请日：2005-06-09
申请人： Di-Hong Lee , Hsun-Chih Tsao , Kuang-Hsin Chen , Hung-Wei Chen
发明人： Di-Hong Lee , Hsun-Chih Tsao , Kuang-Hsin Chen , Hung-Wei Chen
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L21/28273 , H01L29/42328 , H01L29/66795 , H01L29/66825 , H01L29/785
摘要： A FinFET split gate EEPROM structure includes a semiconductor substrate and an elongated semiconductor fin extending above the substrate. A control gate straddles the fin, the fin's sides and a first drain-proximate portion of a channel between a source and drain in the fin. The control gate includes a tunnel layer and a floating electrode over which are a first insulative stratum and a first conductive stratum. A select gate straddles the fin and its sides and a second, source-promixate portion of the channel. The select gate includes a second insulative stratum and a second conductive stratum. The insulative strata are portions of a continuous insulative layer covering the substrate and the fin. The conductive strata are electrically continuous portions of a continuous conductive layer formed on the insulative layer.
摘要翻译： FinFET分离栅极EEPROM结构包括半导体衬底和在衬底上延伸的细长半导体鳍片。控制栅极横跨鳍片，翅片的侧面以及翅片中的源极和漏极之间的通道的第一漏极 - 近似部分。控制门包括隧道层和浮动电极，第一绝缘层和第一导电层在其上形成。选择栅极横跨鳍片及其侧面以及通道的第二个源极扩展部分。选择门包括第二绝缘层和第二导电层。绝缘层是覆盖基板和翅片的连续绝缘层的部分。导电层是形成在绝缘层上的连续导电层的电连续部分。

8. 发明授权

US07183150B2 Resist protect oxide structure of sub-micron salicide process 有权
标题翻译：抗氧化保护亚微米自杀过程的氧化物结构
公开(公告)号：US07183150B2
公开(公告)日：2007-02-27
申请号：US10946406
申请日：2004-09-21
申请人： Ming-Chang Hsieh , Hsun-Chih Tsao , Hung-Chih Tsai , Pin-Shyne Chin
发明人： Ming-Chang Hsieh , Hsun-Chih Tsao , Hung-Chih Tsai , Pin-Shyne Chin
IPC分类号： H01L21/338 , H01L21/336 , H01L21/31
CPC分类号： H01L21/823835 , H01L21/31111 , H01L21/31144 , H01L21/3143 , H01L21/823814 , H01L29/7833 , Y10S438/95
摘要： In accordance with the objectives of the invention a new method is provided for the creation of a layer of a Resistance Protective Oxide (RPO) layer. A layer of ONO is deposited that is to function as the layer of RPO. The deposited layer of ONO is patterned and wet etched, removing the upper or first layer of silicon dioxide. The patterned and etch upper of first layer of silicon dioxide is used as a hardmask to remove the central layer of silicon nitride applying a wet etch. A wet etch is then applied to remove the remaining lower of second layer of silicon dioxide, completing the patterning of the layer of RPO.
摘要翻译：根据本发明的目的，提供了一种创建电阻保护氧化物（RPO）层的新方法。沉积一层ONO，作为RPO层。对ONO的沉积层进行图案化和湿蚀刻，去除二氧化硅的上层或第一层。将第一层二氧化硅的图案化和蚀刻上部用作硬掩模，以移除采用湿蚀刻的中间层氮化硅层。然后施加湿蚀刻以除去剩余的较低的第二层二氧化硅，完成RPO层的图案化。

9. 发明申请

US20060012004A1 STI liner for SOI structure 有权
标题翻译： STI衬垫为SOI结构
公开(公告)号：US20060012004A1
公开(公告)日：2006-01-19
申请号：US11221200
申请日：2005-09-07
申请人： Kuang-Hsin Chen , Hsun-Chih Tsao , Hung-Wei Chen , Di-Hong Lee , Chuan-Ping Hou , Jhi-Cherng Lu
发明人： Kuang-Hsin Chen , Hsun-Chih Tsao , Hung-Wei Chen , Di-Hong Lee , Chuan-Ping Hou , Jhi-Cherng Lu
IPC分类号： H01L29/00 , H01L21/20
CPC分类号： H01L21/76224 , H01L21/84
摘要： In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.
摘要翻译：在制造半导体器件的方法中，提供初始结构。初始结构包括衬底，图案化硅层和覆盖层。基板上形成有埋置的绝缘体层。图案化的硅层形成在掩埋绝缘体层上。覆盖层形成在图案化硅层上。在初始结构上形成第一层。通过蚀刻工艺去除第一层的一部分，使得图案化硅层的侧壁部分被暴露，并且使得第一层的剩余部分保留在图案化硅层与掩埋绝缘体层接合的拐角处。在暴露的侧壁部分上形成氧化物衬垫。可以在掩埋绝缘体层（在形成第一层之前）形成凹部，并且可以在图案化的硅层的部分下方延伸。

10. 发明授权

US06955955B2 STI liner for SOI structure 有权
标题翻译： STI衬垫为SOI结构
公开(公告)号：US06955955B2
公开(公告)日：2005-10-18
申请号：US10747494
申请日：2003-12-29
申请人： Kuang-Hsin Chen , Hsun-Chih Tsao , Hung-Wei Chen , Di-Hong Lee , Chuan-Ping Hou , Jhi-Cherng Lu
发明人： Kuang-Hsin Chen , Hsun-Chih Tsao , Hung-Wei Chen , Di-Hong Lee , Chuan-Ping Hou , Jhi-Cherng Lu
IPC分类号： H01L21/00 , H01L21/20 , H01L21/762 , H01L21/84 , H01L27/01
CPC分类号： H01L21/76224 , H01L21/84
摘要： In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.
摘要翻译：在制造半导体器件的方法中，提供了初始结构。初始结构包括衬底，图案化硅层和覆盖层。基板上形成有埋置的绝缘体层。图案化的硅层形成在掩埋绝缘体层上。覆盖层形成在图案化硅层上。在初始结构上形成第一层。通过蚀刻工艺去除第一层的一部分，使得图案化硅层的侧壁部分被暴露，并且使得第一层的剩余部分保留在图案化硅层与掩埋绝缘体层接合的拐角处。在暴露的侧壁部分上形成氧化物衬垫。可以在掩埋绝缘体层（在形成第一层之前）形成凹部，并且可以在图案化的硅层的部分下方延伸。

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