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1. 发明授权

US07694281B2 Two-pass MRET trace selection for dynamic optimization 有权
标题翻译：双向MRET跟踪选择用于动态优化
公开(公告)号：US07694281B2
公开(公告)日：2010-04-06
申请号：US11241527
申请日：2005-09-30
申请人： Cheng Wang , Bixia Zheng , Ho-seop Kim , Mauricio Breternitz, Jr. , Youfeng Wu
发明人： Cheng Wang , Bixia Zheng , Ho-seop Kim , Mauricio Breternitz, Jr. , Youfeng Wu
IPC分类号： G06F9/44
CPC分类号： G06F9/45516
摘要： A first potential hot trace of a program is determined. A second potential hot trace of the program is determined. A common path from the first potential hot trace and the second potential hot trace is selected as the selected hot trace of the program.
摘要翻译：确定程序的第一个潜在的热迹。确定程序的第二个潜在的热迹。选择第一个潜在热痕迹和第二个潜在热痕迹的常见路径作为程序的选定热痕迹。

2. 发明授权

US07757221B2 Apparatus and method for dynamic binary translator to support precise exceptions with minimal optimization constraints 有权
标题翻译：用于动态二进制转换器的装置和方法，以最小的优化约束来支持精确异常
公开(公告)号：US07757221B2
公开(公告)日：2010-07-13
申请号：US11241610
申请日：2005-09-30
申请人： Bixia Zheng , Cheng C. Wang , Ho-seop Kim , Mauricio Breternitz, Jr. , Youfeng Wu
发明人： Bixia Zheng , Cheng C. Wang , Ho-seop Kim , Mauricio Breternitz, Jr. , Youfeng Wu
IPC分类号： G06F9/45
CPC分类号： G06F9/45516 , G06F8/443
摘要： A method and apparatus for dynamic binary translator to support precise exceptions with minimal optimization constraints. In one embodiment, the method includes the translation of a source binary application generated for a source instruction set architecture (ISA) into a sequential, intermediate representation (IR) of the source binary application. In one embodiment, the sequential IR is modified to incorporate exception recovery information for each of the exception instructions identified from the source binary application to enable a dynamic binary translator (DBT) to represent exception recovery values as regular values used by IR instructions. In one embodiment, the sequential IR may be optimized with a constraint on movement of an exception instruction downward past an irreversible instruction to form a non-sequential IR. In one embodiment, the non-sequential IR is optimized to form a translated binary application for a target ISA. Other embodiments are described and claimed.
摘要翻译：一种用于动态二进制转换器的方法和装置，以最小的优化约束来支持精确的异常。在一个实施例中，该方法包括将源指令集架构（ISA）生成的源二进制应用程序转换为源二进制应用程序的顺序中间表示（IR）。在一个实施例中，顺序IR被修改为包含从源二进制应用程序识别的每个异常指令的异常恢复信息，以使动态二进制转换器（DBT）能够将异常恢复值表示为由IR指令使用的常规值。在一个实施例中，可以对异常指令向下移动通过不可逆指令以形成非顺序IR的限制来优化顺序IR。在一个实施例中，非顺序IR被优化以形成目标ISA的翻译二进制应用程序。描述和要求保护其他实施例。

3. 发明申请

US20070079293A1 Two-pass MRET trace selection for dynamic optimization 有权
标题翻译：双向MRET跟踪选择用于动态优化
公开(公告)号：US20070079293A1
公开(公告)日：2007-04-05
申请号：US11241527
申请日：2005-09-30
申请人： Cheng Wang , Bixia Zheng , Ho-seop Kim , Mauricio Breternitz , Youfeng Wu
发明人： Cheng Wang , Bixia Zheng , Ho-seop Kim , Mauricio Breternitz , Youfeng Wu
IPC分类号： G06F9/44
CPC分类号： G06F9/45516
摘要： A first potential hot trace of a program is determined. A second potential hot trace of the program is determined. A common path from the first potential hot trace and the second potential hot trace is selected as the selected hot trace of the program.
摘要翻译：确定程序的第一个潜在的热迹。确定程序的第二个潜在的热迹。选择第一个潜在热痕迹和第二个潜在热痕迹的常见路径作为程序的选定热痕迹。

4. 发明申请

US20070079304A1 Apparatus and method for dynamic binary translator to support precise exceptions with minimal optimization constraints 有权
标题翻译：用于动态二进制转换器的装置和方法，以最小的优化约束来支持精确异常
公开(公告)号：US20070079304A1
公开(公告)日：2007-04-05
申请号：US11241610
申请日：2005-09-30
申请人： Bixia Zheng , Cheng Wang , Ho-seop Kim , Mauricio Breternitz , Youfeng Wu
发明人： Bixia Zheng , Cheng Wang , Ho-seop Kim , Mauricio Breternitz , Youfeng Wu
IPC分类号： G06F9/45
CPC分类号： G06F9/45516 , G06F8/443
摘要： A method and apparatus for dynamic binary translator to support precise exceptions with minimal optimization constraints. In one embodiment, the method includes the translation of a source binary application generated for a source instruction set architecture (ISA) into a sequential, intermediate representation (IR) of the source binary application. In one embodiment, the sequential IR is modified to incorporate exception recovery information for each of the exception instructions identified from the source binary application to enable a dynamic binary translator (DBT) to represent exception recovery values as regular values used by IR instructions. In one embodiment, the sequential IR may be optimized with a constraint on movement of an exception instruction downward past an irreversible instruction to form a non-sequential IR. In one embodiment, the non-sequential IR is optimized to form a translated binary application for a target ISA. Other embodiments are described and claimed.
摘要翻译：一种用于动态二进制转换器的方法和装置，以最小的优化约束来支持精确的异常。在一个实施例中，该方法包括将源指令集架构（ISA）生成的源二进制应用程序转换为源二进制应用程序的顺序中间表示（IR）。在一个实施例中，顺序IR被修改为包含从源二进制应用程序识别的每个异常指令的异常恢复信息，以使动态二进制转换器（DBT）能够将异常恢复值表示为由IR指令使用的常规值。在一个实施例中，可以对异常指令向下移动通过不可逆指令以形成非顺序IR的限制来优化顺序IR。在一个实施例中，非顺序IR被优化以形成目标ISA的翻译二进制应用程序。描述和要求保护其他实施例。

5. 发明申请

US20080162522A1 Methods and apparatuses for compaction and/or decompaction 审中-公开
标题翻译：用于压实和/或解压缩的方法和装置
公开(公告)号：US20080162522A1
公开(公告)日：2008-07-03
申请号：US11648260
申请日：2006-12-29
申请人： Guei-Yuan Lueh , Hong Jiang , Andrew T. Riffel , Bixia Zheng , Chu-Cheow Lim , Milind Girkar , David C. Sehr , Thomas A. Piazza
发明人： Guei-Yuan Lueh , Hong Jiang , Andrew T. Riffel , Bixia Zheng , Chu-Cheow Lim , Milind Girkar , David C. Sehr , Thomas A. Piazza
IPC分类号： G06F17/30
CPC分类号： G06F8/4434 , G06F8/447 , G06F9/30036 , G06F9/30156 , G06F9/30167 , G06F9/30178 , G06F9/3853
摘要： In some embodiments, a data structure may be received in a first processing system. The data structure may represent a plurality of instructions for a second processing system. For at least one instruction of the plurality of instructions, a determination may be made as to whether the instruction can be replaced by a compact instruction for the second processing system. A compact instruction may be generated if the instruction can be replaced by a compact instruction. In some embodiments, an instruction may be received in a processing system. A determination may be made as to whether the instruction is a compact instruction. A decompacted instruction may be generated if the instruction is a compact instruction.
摘要翻译：在一些实施例中，可以在第一处理系统中接收数据结构。数据结构可以表示用于第二处理系统的多个指令。对于多个指令中的至少一个指令，可以确定该指令是否可以由第二处理系统的紧凑指令代替。如果可以用紧凑指令代替指令，则可能会产生紧凑指令。在一些实施例中，可以在处理系统中接收指令。可以确定该指令是否是紧凑指令。如果指令是紧凑指令，则可能会生成解压缩指令。

6. 发明授权

US07688232B2 Optimal selection of compression entries for compressing program instructions 有权
标题翻译：压缩程序指令压缩条目的最佳选择
公开(公告)号：US07688232B2
公开(公告)日：2010-03-30
申请号：US11691795
申请日：2007-03-27
申请人： Chu-Cheow Lim , Guei-Yuan Lueh , Bixia Zheng , Hong Jiang
发明人： Chu-Cheow Lim , Guei-Yuan Lueh , Bixia Zheng , Hong Jiang
IPC分类号： H03M7/00
CPC分类号： H03M7/30 , G06F9/30156 , G06F9/30178
摘要： A method of compressing instructions in a program may include extracting unique bit patterns from the instructions in the program and constructing a linear programming formulation or an integer programming formulation from the unique bit patterns, the instructions, and/or the size of a memory storage. The linear programming formulation or the integer programming formulation may be solved to produce a solution. The method may include compressing at least some of the instructions based on the solution by storing at least some of the unique bit patterns in a memory and placing corresponding indices to the memory in new compressed instructions.
摘要翻译：一种在程序中压缩指令的方法可以包括从程序中的指令中提取唯一位模式，并根据唯一位模式，指令和/或存储器存储器的大小构建线性规划公式或整数规划公式。可以解决线性规划公式或整数规划公式以产生解决方案。该方法可以包括通过将至少一些唯一位模式存储在存储器中并基于解决方案来将新的压缩指令中的相应索引放置到存储器来压缩至少一些指令。

7. 发明申请

US20080244245A1 OPTIMAL SELECTION OF COMPRESSION ENTRIES FOR COMPRESSING PROGRAM INSTRUCTIONS 有权
标题翻译：压缩程序压缩指令的最佳选择
公开(公告)号：US20080244245A1
公开(公告)日：2008-10-02
申请号：US11691795
申请日：2007-03-27
申请人： Chu-Cheow Lim , Guei-Yuan Lueh , Bixia Zheng , Hong Jiang
发明人： Chu-Cheow Lim , Guei-Yuan Lueh , Bixia Zheng , Hong Jiang
IPC分类号： G06F7/38
CPC分类号： H03M7/30 , G06F9/30156 , G06F9/30178
摘要： A method of compressing instructions in a program may include extracting unique bit patterns from the instructions in the program and constructing a linear programming formulation or an integer programming formulation from the unique bit patterns, the instructions, and/or the size of a memory storage. The linear programming formulation or the integer programming formulation may be solved to produce a solution. The method may include compressing at least some of the instructions based on the solution by storing at least some of the unique bit patterns in a memory and placing corresponding indices to the memory in new compressed instructions.
摘要翻译：一种在程序中压缩指令的方法可以包括从程序中的指令中提取唯一位模式，并根据唯一位模式，指令和/或存储器存储器的大小构建线性规划公式或整数规划公式。可以解决线性规划公式或整数规划公式以产生解决方案。该方法可以包括通过将至少一些唯一位模式存储在存储器中并基于解决方案来将新的压缩指令中的相应索引放置到存储器来压缩至少一些指令。

8. 发明申请

US20080082970A1 Method and apparatus for assigning subroutines 有权
标题翻译：分配子程序的方法和装置
公开(公告)号：US20080082970A1
公开(公告)日：2008-04-03
申请号：US11541083
申请日：2006-09-29
申请人： Guei-Yuan Lueh , Andrew T. Riffel , Hong Jiang , Bixia Zheng , Lian Tang
发明人： Guei-Yuan Lueh , Andrew T. Riffel , Hong Jiang , Bixia Zheng , Lian Tang
IPC分类号： G06F9/45
CPC分类号： G06F8/54
摘要： According to some embodiments, systems and methods are provided to link a first entry point of a first kernel to a dummy entry, link a second entry point of a second kernel to the dummy entry, and compile the first kernel and the second kernel.
摘要翻译：根据一些实施例，提供系统和方法来将第一内核的第一入口点连接到虚拟条目，将第二内核的第二入口点连接到虚拟条目，并且编译第一内核和第二内核。

9. 发明授权

US08799876B2 Method and apparatus for assigning subroutines 有权
标题翻译：分配子程序的方法和装置
公开(公告)号：US08799876B2
公开(公告)日：2014-08-05
申请号：US11541083
申请日：2006-09-29
申请人： Guei-Yuan Lueh , Andrew T. Riffel , Hong Jiang , Bixia Zheng , Lian Tang
发明人： Guei-Yuan Lueh , Andrew T. Riffel , Hong Jiang , Bixia Zheng , Lian Tang
IPC分类号： G06F9/45
CPC分类号： G06F8/54
摘要： According to some embodiments, systems and methods are provided to link a first entry point of a first kernel to a dummy entry, link a second entry point of a second kernel to the dummy entry, and compile the first kernel and the second kernel.
摘要翻译：根据一些实施例，提供系统和方法来将第一内核的第一入口点连接到虚拟条目，将第二内核的第二入口点连接到虚拟条目，并且编译第一内核和第二内核。

10. 发明申请

US20130125100A1 COMPUTER SYSTEM AND METHOD FOR COMPILING PROGRAM CODE AND ASSIGNING ADDRESS SPACES 审中-公开
标题翻译：用于编译程序代码和计算地址空间的计算机系统和方法
公开(公告)号：US20130125100A1
公开(公告)日：2013-05-16
申请号：US13296967
申请日：2011-11-15
申请人： Bixia Zheng , Benedict R. Gaster , Dz-Ching Ju
发明人： Bixia Zheng , Benedict R. Gaster , Dz-Ching Ju
IPC分类号： G06F9/45
CPC分类号： G06F8/427
摘要： A computer system is provided for compiling program code and a method for compiling program code by a processor. The method, for example, includes, but is not limited to, receiving, by the processor, the program code and compiling, by the processor, the program code, wherein the processor, when compiling the program code, parses the program code and assigns a default address space qualifier to each member functions without a defined address space qualifier and, when the member function is used, infers an address space for each default address qualifier based upon how the respective member function is being used.
摘要翻译：提供用于编译程序代码的计算机系统和用于由处理器编译程序代码的方法。该方法例如包括但不限于由处理器接收程序代码并由处理器编译程序代码，其中处理器在编译程序代码时解析程序代码并分配每个成员函数的默认地址空间限定符，而没有定义的地址空间限定符，并且当使用成员函数时，基于如何使用相应的成员函数推测每个默认地址限定符的地址空间。

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