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1. 发明授权

US08683468B2 Automatic kernel migration for heterogeneous cores 有权
标题翻译：异构核心的自动内核迁移
公开(公告)号：US08683468B2
公开(公告)日：2014-03-25
申请号：US13108438
申请日：2011-05-16
申请人： Mauricio Breternitz , Patryk Kaminski , Keith Lowery , Anton Chernoff , Dz-Ching Ju
发明人： Mauricio Breternitz , Patryk Kaminski , Keith Lowery , Anton Chernoff , Dz-Ching Ju
IPC分类号： G06F9/46
CPC分类号： G06F9/4856 , G06F9/5066
摘要： A system and method for automatically migrating the execution of work units between multiple heterogeneous cores. A computing system includes a first processor core with a single instruction multiple data micro-architecture and a second processor core with a general-purpose micro-architecture. A compiler predicts execution of a function call in a program migrates at a given location to a different processor core. The compiler creates a data structure to support moving live values associated with the execution of the function call at the given location. An operating system (OS) scheduler schedules at least code before the given location in program order to the first processor core. In response to receiving an indication that a condition for migration is satisfied, the OS scheduler moves the live values to a location indicated by the data structure for access by the second processor core and schedules code after the given location to the second processor core.
摘要翻译：一种用于在多个异构核心之间自动迁移工作单元执行的系统和方法。计算系统包括具有单指令多数据微架构的第一处理器核心和具有通用微架构的第二处理器核心。编译器预测程序中的函数调用的执行在给定位置迁移到不同的处理器核心。编译器创建一个数据结构，以支持在给定位置移动与执行函数调用相关联的实时值。操作系统（OS）调度器将程序顺序之前的给定位置之前的至少代码调度到第一处理器核心。响应于接收到满足迁移条件的指示，OS调度器将活动值移动到由数据结构指示的位置，以供第二处理器核心访问，并且将给定位置之后的代码调度到第二处理器核心。

2. 发明授权

US08656409B2 High performance queue implementations in multiprocessor systems 失效
标题翻译：多处理器系统中的高性能队列实现
公开(公告)号：US08656409B2
公开(公告)日：2014-02-18
申请号：US12087182
申请日：2005-12-29
申请人： Xiao-Feng Li , Dz-ching Ju
发明人： Xiao-Feng Li , Dz-ching Ju
IPC分类号： G06F9/54
CPC分类号： G06F9/526 , G06F5/12 , G06F9/546 , G06F2209/521
摘要： Systems and methods provide a single reader single writer (SRSW) queue structure having entries that can be concurrently accessed in an atomic manner with a single memory access. The SRSW queues may be combined to create more complicated queues, including multiple reader single writer (MRSW), single reader multiple writer (SRMW), and multiple reader multiple writer (MRMW) queues.
摘要翻译：系统和方法提供单个读写器单写入器（SRSW）队列结构，其具有可以以单一存储器访问以原子方式同时访问的条目。 SRSW队列可以被组合以创建更复杂的队列，包括多个读写器单写入器（MRSW），单个读取器多写入器（SRMW）和多个读取器多写入器（MRMW）队列。

3. 发明申请

US20070226740A1 Method and apparatus for global breakpoint for parallel debugging on multiprocessor systems 审中-公开
标题翻译：用于多处理器系统并行调试的全局断点的方法和装置
公开(公告)号：US20070226740A1
公开(公告)日：2007-09-27
申请号：US11364942
申请日：2006-02-28
申请人： Xiao-Feng Li , Dz-ching Ju
发明人： Xiao-Feng Li , Dz-ching Ju
IPC分类号： G06F9/46
CPC分类号： G06F11/3632
摘要： A system that concurrently executes threads of a multi-threaded application pauses the execution of one thread, then pauses the execution of another thread before the second thread alters a shared memory state. Chipsets and software to implement embodiments of the invention are also described and claimed.
摘要翻译：同时执行多线程应用程序的系统会暂停一个线程的执行，然后在第二个线程改变共享内存状态之前暂停另一个线程的执行。还描述和要求保护用于实现本发明实施例的芯片组和软件。

4. 发明申请

US20050149918A1 Inter-procedural allocation of stacked registers for a processor 有权
标题翻译：用于处理器的堆叠寄存器的程序间分配
公开(公告)号：US20050149918A1
公开(公告)日：2005-07-07
申请号：US10747426
申请日：2003-12-29
申请人： Yang Liu , Sun Chan , Guangrong Gao , Dz-Ching Ju , Guei-Yuan Lueh , Zhaoqing Zhang
发明人： Yang Liu , Sun Chan , Guangrong Gao , Dz-Ching Ju , Guei-Yuan Lueh , Zhaoqing Zhang
IPC分类号： G06F9/45
CPC分类号： G06F8/441
摘要： A method for an allocation of stacked registers for Intel's Itanium® processor includes a three step process. Step I determines an intra-procedural stacked register usage by a program having a plurality of procedures. In step II, the disclosed method performs an inter-procedural analysis to assign quota of stacked register usage to every procedure. In step III, each procedure is allocated stacked register usage based on the quota assignments of step II.
摘要翻译：英特尔安腾（R）处理器分配堆叠寄存器的方法包括三步骤过程。步骤I通过具有多个过程的程序来确定程序内堆叠的寄存器使用。在步骤II中，所公开的方法执行程序间分析以将堆叠的寄存器使用的配额分配给每个过程。在步骤III中，基于步骤II的配额分配，分配每个过程的堆叠寄存器使用。

5. 发明授权

US06782469B1 Runtime critical load/data ordering 失效
标题翻译：运行时关键负载/数据排序
公开(公告)号：US06782469B1
公开(公告)日：2004-08-24
申请号：US09675983
申请日：2000-09-29
申请人： Christopher B. Wilkerson , Srikanth T. Srinivasan , Dz-ching Ju
发明人： Christopher B. Wilkerson , Srikanth T. Srinivasan , Dz-ching Ju
IPC分类号： G06F930
CPC分类号： G06F9/3836 , G06F9/3824 , G06F9/383 , G06F9/3838 , G06F9/384
摘要： A critical load ordering unit is responsible for receiving instructions during a critical phase. Load instructions are associated with the number of instructions during the critical phase that depend on the load instructions. The instructions may then be ordered based on their dependence counts and/or marked as critical load instructions.
摘要翻译：关键负载订购单元负责在关键阶段接收指令。加载指令与依赖于加载指令的关键阶段中的指令数量相关联。然后可以基于它们的依赖计数和/或标记为临界负载指令对指令进行排序。

6. 发明授权

US08769509B2 Methods and apparatus for preserving precise exceptions in code reordering by using control speculation 有权
标题翻译：通过使用控制推测在代码重新排序中保留精确异常的方法和装置
公开(公告)号：US08769509B2
公开(公告)日：2014-07-01
申请号：US11937264
申请日：2007-11-08
申请人： Dz-ching Ju
发明人： Dz-ching Ju
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F9/3861 , G06F9/3834 , G06F9/3842
摘要： Methods and apparatus for preserving precise exceptions in code reordering by using control speculation are disclosed. A disclosed system uses a control speculation module to reorder instructions within an application program and preserve precise exceptions. Instructions, excepting and non-excepting, can be reordered by the control speculation module if the instructions meet certain conditions. When an excepting instruction is reordered, a check instruction is inserted into the program execution path and a recovery block is generated. The check instruction determines if the reordered excepting instruction actually needs to generate an exception. The recovery block contains instructions to revert the effects of code reordering. If the check instruction detects the need for an exception, the recovery block is executed to restore the architectural state of the processor and the exception is handled.
摘要翻译：公开了通过使用控制推测在代码重新排序中保持精确异常的方法和装置。所公开的系统使用控制推测模块来重新排序应用程序中的指令并保留精确的异常。如果指令符合某些条件，则控制推测模块可以重新排除除非和除外的指令。当排除指令重新排序时，将检查指令插入程序执行路径，并生成恢复块。检查指令确定重新排序的除外指令是否真的需要生成异常。恢复块包含恢复代码重新排序效果的指令。如果检查指令检测到异常的需要，则执行恢复块以恢复处理器的体系结构状态，并处理异常。

7. 发明申请

US20120297163A1 AUTOMATIC KERNEL MIGRATION FOR HETEROGENEOUS CORES 有权
标题翻译：自动KERNEL移动异构牙
公开(公告)号：US20120297163A1
公开(公告)日：2012-11-22
申请号：US13108438
申请日：2011-05-16
申请人： Mauricio Breternitz , Patryk Kaminski , Keith Lowery , Anton Chernoff , Dz-Ching Ju
发明人： Mauricio Breternitz , Patryk Kaminski , Keith Lowery , Anton Chernoff , Dz-Ching Ju
IPC分类号： G06F9/315 , G06F15/80
CPC分类号： G06F9/4856 , G06F9/5066
摘要： A system and method for automatically migrating the execution of work units between multiple heterogeneous cores. A computing system includes a first processor core with a single instruction multiple data micro-architecture and a second processor core with a general-purpose micro-architecture. A compiler predicts execution of a function call in a program migrates at a given location to a different processor core. The compiler creates a data structure to support moving live values associated with the execution of the function call at the given location. An operating system (OS) scheduler schedules at least code before the given location in program order to the first processor core. In response to receiving an indication that a condition for migration is satisfied, the OS scheduler moves the live values to a location indicated by the data structure for access by the second processor core and schedules code after the given location to the second processor core.
摘要翻译：一种用于在多个异构核心之间自动迁移工作单元执行的系统和方法。计算系统包括具有单指令多数据微架构的第一处理器核心和具有通用微架构的第二处理器核心。编译器预测程序中的函数调用的执行在给定位置迁移到不同的处理器核心。编译器创建一个数据结构，以支持在给定位置移动与执行函数调用相关联的实时值。操作系统（OS）调度器将程序顺序之前的给定位置之前的至少代码调度到第一处理器核心。响应于接收到满足迁移条件的指示，OS调度器将活动值移动到由数据结构指示的位置，以供第二处理器核心访问，并且将给定位置之后的代码调度到第二处理器核心。

8. 发明授权

US07350024B2 Automatic generation of software-controlled caching and ordered synchronization 有权
标题翻译：自动生成软件控制的缓存和有序同步
公开(公告)号：US07350024B2
公开(公告)日：2008-03-25
申请号：US11015871
申请日：2004-12-16
申请人： Michael Chen , Dz-ching Ju
发明人： Michael Chen , Dz-ching Ju
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F8/4442 , G06F12/0842
摘要： A method for applying software controlled caching and ordered thread optimizations in network applications includes collecting statistics for program variables, selecting program variable candidates for ordered synchronization and/or software controlled cache optimization, performing a safety check to ensure candidates can be properly optimized, and generating code for selected optimization candidates.
摘要翻译：在网络应用中应用软件控制的缓存和有序线程优化的方法包括收集程序变量的统计数据，选择用于有序同步的程序变量候选和/或软件控制的高速缓存优化，执行安全检查以确保候选者能够被适当优化，并产生所选优化候选人的代码。

9. 发明申请

US20080065872A1 METHODS AND APPARATUS FOR PRESERVING PRECISE EXCEPTIONS IN CODE REORDERING BY USING CONTROL SPECULATION 有权
标题翻译：通过使用控制参数在代码重新保存精确异常的方法和装置
公开(公告)号：US20080065872A1
公开(公告)日：2008-03-13
申请号：US11937264
申请日：2007-11-08
申请人： Dz-ching Ju
发明人： Dz-ching Ju
IPC分类号： G06F9/26
CPC分类号： G06F9/3861 , G06F9/3834 , G06F9/3842
摘要： Methods and apparatus for preserving precise exceptions in code reordering by using control speculation are disclosed. A disclosed system uses a control speculation module to reorder instructions within an application program and preserve precise exceptions. Instructions, excepting and non-excepting, can be reordered by the control speculation module if the instructions meet certain conditions. When an excepting instruction is reordered, a check instruction is inserted into the program execution path and a recovery block is generated. The check instruction determines if the reordered excepting instruction actually needs to generate an exception. The recovery block contains instructions to revert the effects of code reordering. If the check instruction detects the need for an exception, the recovery block is executed to restore the architectural state of the processor and the exception is handled.
摘要翻译：公开了通过使用控制推测在代码重新排序中保持精确异常的方法和装置。所公开的系统使用控制推测模块来重新排序应用程序中的指令并保留精确的异常。如果指令符合某些条件，则控制推测模块可以重新排除除非和除外的指令。当排除指令重新排序时，将检查指令插入程序执行路径，并生成恢复块。检查指令确定重新排序的除外指令是否真的需要生成异常。恢复块包含恢复代码重新排序效果的指令。如果检查指令检测到异常的需要，则执行恢复块以恢复处理器的体系结构状态，并处理异常。

10. 发明申请

US20070226720A1 System and Method for Efficiently Passing Information Between Compiler and Post-Compile-Time Software 审中-公开
标题翻译：在编译器和后期编译软件之间有效传递信息的系统和方法
公开(公告)号：US20070226720A1
公开(公告)日：2007-09-27
申请号：US11756228
申请日：2007-05-31
申请人： Ding-Kai Chen , Dz-Ching Ju
发明人： Ding-Kai Chen , Dz-Ching Ju
IPC分类号： G06F9/45
CPC分类号： G06F8/443 , G06F8/441 , G06F9/30076 , G06F9/30145
摘要： System and method are described for register optimization during code translation utilizes a technique that removes the time overhead for analyzing register usage and eliminates fixed restraints on the compiler register usage. The present invention for register optimization utilizes a compiler to produce a register usage bit vector in a NOP instruction within each basic block (i.e., subroutine, function, and/or procedure). Each bit in the bit vector represents a particular caller-saved register. A bit is set if, at the location of NOP instruction, the compiler uses the corresponding register within that basic block containing the NOP instruction to hold information to be used at a later time. During the translation, the translator examines the register usage bit vector to very quickly determine which registers are free and therefore can be used during the register optimization without the need to save and restore the register values.
摘要翻译：在代码转换中描述了用于寄存器优化的系统和方法，该技术消除了分析寄存器使用的时间开销并消除了对编译器寄存器使用的固定约束。用于寄存器优化的本发明利用编译器在每个基本块（即，子程序，功能和/或过程）中的NOP指令中产生寄存器使用位向量。位向量中的每个位表示特定的调用者保存的寄存器。如果在NOP指令的位置，编译器使用包含NOP指令的基本块内的对应寄存器来保存稍后使用的信息，则置位。在翻译期间，翻译器检查寄存器使用位向量，以快速确定哪些寄存器是空闲的，因此可以在寄存器优化期间使用，而不需要保存和恢复寄存器值。

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