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1. 发明申请

US20070008771A1 Tracking circuit for a memory device 有权
标题翻译：记忆装置的跟踪电路
公开(公告)号：US20070008771A1
公开(公告)日：2007-01-11
申请号：US11172873
申请日：2005-07-05
申请人： Cheng Lee , Simon Wang , Hung-Jen Liao
发明人： Cheng Lee , Simon Wang , Hung-Jen Liao
IPC分类号： G11C11/00 , G11C8/00 , G11C29/00 , G11C7/00
CPC分类号： G11C7/14 , G11C7/22 , G11C7/227 , G11C11/419
摘要： A memory device includes a memory array, an I/O circuit for accessing the memory array, and a tracking circuit. The tracking circuit includes a dummy bit line, a first tracking cell including a first NMOS transistor, the first tracking cell being coupled to receive a control signal and also coupled to the dummy bit line through the first NMOS transistor, and a second tracking cell including a second NMOS transistor, the second tracking cell being coupled to receive the control signal and also coupled to the dummy bit line through the second NMOS transistor, a gate of the second NMOS transistor being coupled to the dummy bit line. The memory device also includes a control circuit coupled to the dummy bit line for generating a clock signal for the I/O circuit.
摘要翻译：存储器件包括存储器阵列，用于访问存储器阵列的I / O电路和跟踪电路。跟踪电路包括虚拟位线，第一跟踪单元包括第一NMOS晶体管，第一跟踪单元被耦合以接收控制信号，并且还通过第一NMOS晶体管耦合到虚拟位线，第二跟踪单元包括第二NMOS晶体管，第二跟踪单元被耦合以接收控制信号，并且还通过第二NMOS晶体管耦合到虚拟位线，第二NMOS晶体管的栅极耦合到虚拟位线。存储器件还包括耦合到虚拟位线的控制电路，用于产生I / O电路的时钟信号。

2. 发明申请

US20070247950A1 Memory device with reduced stand-by mode power consumption 审中-公开
标题翻译：具有降低备用模式功耗的存储器件
公开(公告)号：US20070247950A1
公开(公告)日：2007-10-25
申请号：US11407593
申请日：2006-04-20
申请人： Cheng Lee , Hung-Jen Liao
发明人： Cheng Lee , Hung-Jen Liao
IPC分类号： G11C5/14
CPC分类号： G11C5/148 , G11C8/10
摘要： The present invention discloses a memory device. In one embodiment of the present invention, the memory device includes at least one memory array having a plurality of memory cells addressed by a plurality of word lines and bit lines. At least one word line decoder is coupled to the word lines for selecting the memory cell for read or write operation. The word line decoder includes at least one last stage driver having at least one PMOS transistor and at least one NMOS transistor, the PMOS transistor having a threshold voltage substantially higher than that of the NMOS transistor, thereby reducing the power consumption of the memory device in the stand-by mode.
摘要翻译：本发明公开了一种存储装置。在本发明的一个实施例中，存储器件包括至少一个存储器阵列，其具有由多个字线和位线寻址的多个存储器单元。至少一个字线解码器耦合到字线，用于选择用于读或写操作的存储单元。字线解码器包括至少一个具有至少一个PMOS晶体管和至少一个NMOS晶体管的最后一级驱动器，PMOS晶体管具有基本上高于NMOS晶体管的阈值电压的阈值电压，从而降低了存储器件的功耗备用模式。

3. 发明申请

US20070242555A1 WORD-LINE DRIVER FOR MEMORY DEVICES 有权
标题翻译：用于存储器件的字线驱动器
公开(公告)号：US20070242555A1
公开(公告)日：2007-10-18
申请号：US11406984
申请日：2006-04-18
申请人： Cheng Lee , Hung-Jen Liao
发明人： Cheng Lee , Hung-Jen Liao
IPC分类号： G11C8/00 , G11C5/14
CPC分类号： G11C8/08
摘要： A word-line driver has an input from a word-line decoder and an output to drive a word-line. The word-line driver comprises a plurality of inverters connected in series between the input and output including a first and a second inverter with a first node designating an output of the first inverter and an input of the second inverter, the first inverter having a NMOS transistor with a controllable first source, and a first pull-up circuitry coupled between a positive supply voltage and the first node and selectively activated by a first control signal, wherein when the first source is set to the positive supply voltage and the first control signal is set to a complementary supply voltage of the positive supply voltage, the first node is pulled up to the positive supply voltage to ensure an output of the second inverter is pulled down to the complementary supply voltage.
摘要翻译：字线驱动器具有来自字线解码器的输入和用于驱动字线的输出。字线驱动器包括串联连接在输入和输出之间的多个反相器，包括具有指定第一反相器的输出的第一节点和第二反相器的输入的第一和第二反相器，第一反相器具有NMOS 具有可控第一源的晶体管，以及耦合在正电源电压和第一节点之间并由第一控制信号选择性地激活的第一上拉电路，其中当第一源被设置为正电源电压和第一控制信号设定为正电源电压的互补电源电压，将第一节点上拉至正电源电压，以确保将第二逆变器的输出下拉至互补电源电压。

4. 发明授权

US08907681B2 Timing skew characterization apparatus and method 有权
标题翻译：定时偏斜表征装置及方法
公开(公告)号：US08907681B2
公开(公告)日：2014-12-09
申请号：US13046148
申请日：2011-03-11
申请人： Chao Kai Chuang , Yen-Chien Lai , Hung-Jen Liao
发明人： Chao Kai Chuang , Yen-Chien Lai , Hung-Jen Liao
IPC分类号： G04F10/00 , G01R31/317 , G01R31/319
CPC分类号： G01R31/2837 , G01R31/31725 , G01R31/31726 , G01R31/31922 , H03K5/14
摘要： A timing skew characterization apparatus comprises a coarse timing skew characterization circuit, a fine timing skew characterization circuit and a coarse delay cell calibration circuit. The coarse timing skew characterization circuit comprises a plurality of coarse delay cells whose delays can be calibrated through the coarse delay cell calibration circuit. The calibration of fine delay cells can be implemented through a trail and error process. Both coarse delay step and fine delay step can be characterized through a single measurement setup. As a result, the timing skew characterization apparatus provides a high resolution setup and hold time measurement.
摘要翻译：定时偏差表征装置包括粗时序偏差表征电路，精确定时偏斜表征电路和粗延迟单元校准电路。粗定时偏斜表征电路包括多个粗延迟单元，其延迟可以通过粗延迟单元校准电路进行校准。精细延迟单元的校准可以通过跟踪和误差过程来实现。可以通过单个测量设置来表征粗延迟步长和精细延迟步长。结果，定时偏差表征装置提供高分辨率建立和保持时间测量。

5. 发明授权

US08455354B2 Layouts of POLY cut openings overlapping active regions 有权
标题翻译： POLY切割开口与活跃区域重叠的布局
公开(公告)号：US08455354B2
公开(公告)日：2013-06-04
申请号：US13081115
申请日：2011-04-06
申请人： Jung-Hsuan Chen , Yen-Huei Chen , Li-Chun Tien , Hung-Jen Liao
发明人： Jung-Hsuan Chen , Yen-Huei Chen , Li-Chun Tien , Hung-Jen Liao
IPC分类号： H01L21/28
CPC分类号： H01L21/32139 , H01L21/76816
摘要： A method of forming integrated circuits includes forming a mask layer over a gate electrode line, wherein the gate electrode line is over a well region of a semiconductor substrate; forming an opening in the mask layer, wherein a portion of the gate electrode line and a well pickup region of the well region are exposed through the opening; and removing the portion of the gate electrode line through the opening.
摘要翻译：形成集成电路的方法包括在栅电极线上形成掩模层，其中栅电极线在半导体衬底的阱区之上; 在所述掩模层中形成开口，其中所述栅电极线的一部分和所述阱区的阱拾取区域通过所述开口露出; 并且通过所述开口去除所述栅电极线的所述部分。

6. 发明授权

US08218354B2 SRAM word-line coupling noise restriction 有权
标题翻译： SRAM字线耦合噪声限制
公开(公告)号：US08218354B2
公开(公告)日：2012-07-10
申请号：US12649806
申请日：2009-12-30
申请人： Jhon Jhy Liaw , Hung-Jen Liao
发明人： Jhon Jhy Liaw , Hung-Jen Liao
IPC分类号： G11C11/00
CPC分类号： G11C5/063 , G11C11/412 , G11C11/413
摘要： A DC mode word-line coupling noise restriction circuit for multiple-port Random Access Memory cells. This circuit may comprise a Static Random Access Memory array. The SRAM array contains a plurality of columns and a plurality of rows with an SRAM cell formed at a cross-point of the columns and rows. Each SRAM cell has a first word-line conductor and a second word-line conductor. The first word-line conductor is connected to a first coupling noise restriction circuit. The first coupling noise restriction circuit comprises an inverter and a NMOSFET. The inverter has another NMOSFET and a PMOSFET.
摘要翻译：一种用于多端口随机存取存储单元的DC模式字线耦合噪声限制电路。该电路可以包括静态随机存取存储器阵列。 SRAM阵列包括多个列和多个行，其中SRAM单元形成在列和行的交叉点。每个SRAM单元具有第一字线和第二字线。第一字线导体连接到第一耦合噪声限制电路。第一耦合噪声限制电路包括反相器和NMOSFET。反相器具有另一个NMOSFET和PMOSFET。

7. 发明申请

US20120020176A1 GENERATING AND AMPLIFYING DIFFERENTIAL SIGNALS 有权
标题翻译：生成和放大差分信号
公开(公告)号：US20120020176A1
公开(公告)日：2012-01-26
申请号：US12839575
申请日：2010-07-20
申请人： Chung-Ji Lu , Hung-Jen Liao , Cheng Hung Lee , Derek C. Tao , Annie-Li-Keow Lum , Hong-Chen Cheng
发明人： Chung-Ji Lu , Hung-Jen Liao , Cheng Hung Lee , Derek C. Tao , Annie-Li-Keow Lum , Hong-Chen Cheng
IPC分类号： G11C7/06 , H03F3/45
CPC分类号： G11C7/067 , G11C7/065
摘要： Some embodiments regard a circuit comprising: a first left transistor having a first left drain, a first left gate, and a first left source; a second left transistor having a second left drain, a second left gate, and a second left source; a third left transistor having a third left drain, a third left gate, and a third left source; a first right transistor having a first right drain, a first right gate, and a first right source; a second right transistor having a second right drain, a second right gate, and a second right source; a third right transistor having a third right drain, a third right gate, and a third right source; a left node electrically coupling the first left drain, the second left drain, the second left gate, the third right gate, and the third left drain; and a right node electrically coupling the first right drain, the second right drain, the second right gate, the third left gate, and the third right drain.
摘要翻译：一些实施例涉及一种电路，包括：具有第一左漏极，第一左栅极和第一左源的第一左晶体管; 第二左晶体管，具有第二左漏极，第二左栅极和第二左源极; 第三左晶体管，具有第三左漏极，第三左栅极和第三左源; 第一右晶体管，具有第一右漏极，第一右栅极和第一右源; 第二右晶体管，具有第二右漏极，第二右栅极和第二右源; 第三右晶体管，具有第三右漏极，第三右栅极和第三右源; 左节点，电耦合第一左排水口，第二左排水管，第二左闸门，第三右闸门和第三左排水管; 以及电连接第一右排水管，第二右排水管，第二右浇口，第三左浇口和第三右排水沟的右节点。

8. 发明申请

US20100124099A1 8T LOW LEAKAGE SRAM CELL 有权
标题翻译： 8T低漏电SRAM单元
公开(公告)号：US20100124099A1
公开(公告)日：2010-05-20
申请号：US12273959
申请日：2008-11-19
申请人： Jui-Jen Wu , Yen-Huei Chen , Shao-Yu Chou , Hung-Jen Liao
发明人： Jui-Jen Wu , Yen-Huei Chen , Shao-Yu Chou , Hung-Jen Liao
IPC分类号： G11C11/412
CPC分类号： G11C11/412
摘要： This invention discloses a static random access memory (SRAM) cell comprising a pair of cross-coupled inverters having a storage node, and a NMOS transistor having a gate terminal, a first and a second source/drain terminal connected to the storage node, a read word-line (RWL) and a read bit-line (RBL), respectively, the RWL and RBL being activated during a read operation and not being activated during any write operation.
摘要翻译：本发明公开了一种静态随机存取存储器（SRAM）单元，其包括具有存储节点的一对交叉耦合的反相器，以及具有栅极端子，连接到存储节点的第一和第二源极/漏极端子的NMOS晶体管，分别读取字线（RWL）和读位线（RBL），RWL和RBL在读操作期间被激活，并且在任何写操作期间未被激活。

9. 发明授权

US07613054B2 SRAM device with enhanced read/write operations 有权
标题翻译：具有增强的读/写操作的SRAM器件
公开(公告)号：US07613054B2
公开(公告)日：2009-11-03
申请号：US11924437
申请日：2007-10-25
申请人： Cheng-Hung Lee , Ping-Wei Wang , Ching-Wei Wu , Shu-Hsuan Lin , Feng-Ming Chang , Hung-Jen Liao
发明人： Cheng-Hung Lee , Ping-Wei Wang , Ching-Wei Wu , Shu-Hsuan Lin , Feng-Ming Chang , Hung-Jen Liao
IPC分类号： G11C7/00
CPC分类号： G11C11/412 , H01L27/1104
摘要： An SRAM device includes: a first group of memory cells connected to a first local bit line and a first local complementary bit line for accessing data nodes thereof; a second group of memory cells connected to a second local bit line and a second local complementary bit line for accessing data nodes thereof; and a global bit line and a global complementary bit line connected to the first and second local bit lines for accessing data nodes of the first and second groups of memory cells, wherein the first local bit line, the first local complementary bit line, the second local bit line, the second local complementary bit line, the global bit line and the global complementary bit line are constructed on a same metallization level in the SRAM device.
摘要翻译： SRAM器件包括：连接到第一本地位线的第一组存储器单元和用于访问其数据节点的第一局部互补位线; 连接到第二本地位线的第二组存储器单元和用于访问其数据节点的第二局部互补位线; 以及连接到第一和第二本地位线的全局位线和全局互补位线，用于访问第一和第二组存储器单元的数据节点，其中第一局部位线，第一局部互补位线，第二局部位线局部位线，第二局部互补位线，全局位线和全局互补位线构成在SRAM器件中相同的金属化电平上。

10. 发明授权

US07468903B2 Circuits for improving read and write margins in multi-port SRAMS 有权
公开(公告)号：US07468903B2
公开(公告)日：2008-12-23
申请号：US11598385
申请日：2006-11-13
申请人： Dao-Ping Wang , Hung-Jen Liao , Kun Lung Chen , Yung-Lung Lin , Jui-Jen Wu , Chen Yen-Huei
发明人： Dao-Ping Wang , Hung-Jen Liao , Kun Lung Chen , Yung-Lung Lin , Jui-Jen Wu , Chen Yen-Huei
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C8/08 , G11C11/413 , G11C11/418
摘要： A system and method for writing a SRAM cell coupled to complimentary first and second bit-lines (BLs) is disclosed, the method comprising asserting a word-line (WL) selecting the SRAM cell to a first positive voltage, providing a second positive voltage at the first BL, providing a first negative voltage at the second BL, and asserting a plurality of WLs not selecting the SRAM cell to a second negative voltage, wherein the writing margin of the SRAM cell is increased.

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