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1. 发明授权

US07535788B2 Dynamic power control for expanding SRAM write margin 有权
标题翻译：用于扩展SRAM写入余量的动态功耗控制
公开(公告)号：US07535788B2
公开(公告)日：2009-05-19
申请号：US11636173
申请日：2006-12-08
申请人： Jui-Jen Wu , Kun-Lung Chen , Hung-Jen Liao , Yung-Lung Lin , Chen Yen-Huei , Dao-Ping Wang
发明人： Jui-Jen Wu , Kun-Lung Chen , Hung-Jen Liao , Yung-Lung Lin , Chen Yen-Huei , Dao-Ping Wang
IPC分类号： G11C5/14
CPC分类号： G11C11/413
摘要： A writing dynamic power control circuit is disclosed, which comprises a BL and its complementary BLB, at least one memory cell coupled to both the BL and BLB, a first NMOS transistor having a source, a drain and a gate coupled to the BL, the Vss and a first data signal, respectively, a second NMOS transistor having a source, a drain and a gate coupled to the BLB, the Vss and a second data signal, respectively, wherein the second data signal is complementary to the first data signal, a first PMOS transistor having a source, a drain and a gate coupled to a high voltage power supply (CVDD) node, the BLB and the BL, respectively, and a second PMOS transistor having a source, a drain and a gate coupled to the CVDD node, the BL and the BLB, respectively.
摘要翻译：公开了一种写入动态功率控制电路，其包括BL及其互补BLB，耦合到BL和BLB的至少一个存储单元，具有耦合到BL的源极，漏极和栅极的第一NMOS晶体管， Vss和第一数据信号，分别具有耦合到BLB的源极，漏极和栅极的第二NMOS晶体管，Vss和第二数据信号，其中第二数据信号与第一数据信号互补，第一PMOS晶体管，具有源极，漏极和栅极，分别耦合到高电压电源（CVDD）节点，BLB和BL，以及第二PMOS晶体管，其具有源极，漏极和栅极耦合到 CVDD节点，BL和BLB。

2. 发明申请

US20080144419A1 Power switching circuit 有权
标题翻译：电源开关电路
公开(公告)号：US20080144419A1
公开(公告)日：2008-06-19
申请号：US11638187
申请日：2006-12-13
申请人： Jui-Jen Wu , Kun-Lung Chen , Hung-Jen Liao , Yung-Lung Lin , Chen Yen-Huei , Dao-Ping Wang
发明人： Jui-Jen Wu , Kun-Lung Chen , Hung-Jen Liao , Yung-Lung Lin , Chen Yen-Huei , Dao-Ping Wang
IPC分类号： G11C5/14
CPC分类号： G11C11/412 , G11C11/413
摘要： A power control circuit for an integrated circuit module includes at least one switch device coupled between a supply voltage and a power node of the integrated circuit module; and a switch control module having a first terminal coupled to the switch device, a second terminal coupled to a control signal, a third terminal coupled to a first storage node of at least one tracking cell, a fourth terminal coupled to a second storage node of the tracking cell, and a fifth terminal coupled to the power node of the integrated circuit module, for controlling the switch device to pass the supply voltage to the power node with or without a substantial voltage drop depending on an operation mode of the integrated circuit module.
摘要翻译：用于集成电路模块的功率控制电路包括耦合在电源电压和集成电路模块的功率节点之间的至少一个开关装置; 以及开关控制模块，其具有耦合到所述开关装置的第一端子，耦合到控制信号的第二端子，耦合到至少一个跟踪单元的第一存储节点的第三端子，耦合到所述至少一个跟踪单元的第二存储节点的第四端子跟踪单元和耦合到集成电路模块的功率节点的第五端子，用于根据集成电路模块的操作模式控制开关装置将电源电压传递到功率节点，具有或不具有实质的电压降。

3. 发明授权

US07468903B2 Circuits for improving read and write margins in multi-port SRAMS 有权
公开(公告)号：US07468903B2
公开(公告)日：2008-12-23
申请号：US11598385
申请日：2006-11-13
申请人： Dao-Ping Wang , Hung-Jen Liao , Kun Lung Chen , Yung-Lung Lin , Jui-Jen Wu , Chen Yen-Huei
发明人： Dao-Ping Wang , Hung-Jen Liao , Kun Lung Chen , Yung-Lung Lin , Jui-Jen Wu , Chen Yen-Huei
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C8/08 , G11C11/413 , G11C11/418
摘要： A system and method for writing a SRAM cell coupled to complimentary first and second bit-lines (BLs) is disclosed, the method comprising asserting a word-line (WL) selecting the SRAM cell to a first positive voltage, providing a second positive voltage at the first BL, providing a first negative voltage at the second BL, and asserting a plurality of WLs not selecting the SRAM cell to a second negative voltage, wherein the writing margin of the SRAM cell is increased.

4. 发明申请

US20080137449A1 Dynamic power control for expanding SRAM write margin 有权
标题翻译：用于扩展SRAM写入余量的动态功耗控制
公开(公告)号：US20080137449A1
公开(公告)日：2008-06-12
申请号：US11636173
申请日：2006-12-08
申请人： Jui-Jen Wu , Kun-Lung Chen , Hung-Jen Liao , Yung-Lung Lin , Chen Yen-Huei , Dao-Ping Wang
发明人： Jui-Jen Wu , Kun-Lung Chen , Hung-Jen Liao , Yung-Lung Lin , Chen Yen-Huei , Dao-Ping Wang
IPC分类号： G11C7/00
CPC分类号： G11C11/413
摘要： A writing dynamic power control circuit is disclosed, which comprises a BL and its complementary BLB, at least one memory cell coupled to both the BL and BLB, a first NMOS transistor having a source, a drain and a gate coupled to the BL, the Vss and a first data signal, respectively, a second NMOS transistor having a source, a drain and a gate coupled to the BLB, the Vss and a second data signal, respectively, wherein the second data signal is complementary to the first data signal, a first PMOS transistor having a source, a drain and a gate coupled to a high voltage power supply (CVDD) node, the BLB and the BL, respectively, and a second PMOS transistor having a source, a drain and a gate coupled to the CVDD node, the BL and the BLB, respectively.
摘要翻译：公开了一种写入动态功率控制电路，其包括BL及其互补BLB，耦合到BL和BLB的至少一个存储单元，具有耦合到BL的源极，漏极和栅极的第一NMOS晶体管， Vss和第一数据信号，分别具有耦合到BLB的源极，漏极和栅极的第二NMOS晶体管，Vss和第二数据信号，其中第二数据信号与第一数据信号互补，第一PMOS晶体管，具有源极，漏极和栅极，分别耦合到高电压电源（CVDD）节点，BLB和BL，以及第二PMOS晶体管，其具有源极，漏极和栅极耦合到 CVDD节点，BL和BLB。

5. 发明授权

US07577052B2 Power switching circuit 有权
标题翻译：电源开关电路
公开(公告)号：US07577052B2
公开(公告)日：2009-08-18
申请号：US11638187
申请日：2006-12-13
申请人： Jui-Jen Wu , Kun-Lung Chen , Hung-Jen Liao , Yung-Lung Lin , Chen Yen-Huei , Dao-Ping Wang
发明人： Jui-Jen Wu , Kun-Lung Chen , Hung-Jen Liao , Yung-Lung Lin , Chen Yen-Huei , Dao-Ping Wang
IPC分类号： G11C5/10
CPC分类号： G11C11/412 , G11C11/413
摘要： A power control circuit for an integrated circuit module includes at least one switch device coupled between a supply voltage and a power node of the integrated circuit module; and a switch control module having a first terminal coupled to the switch device, a second terminal coupled to a control signal, a third terminal coupled to a first storage node of at least one tracking cell, a fourth terminal coupled to a second storage node of the tracking cell, and a fifth terminal coupled to the power node of the integrated circuit module, for controlling the switch device to pass the supply voltage to the power node with or without a substantial voltage drop depending on an operation mode of the integrated circuit module.
摘要翻译：用于集成电路模块的功率控制电路包括耦合在电源电压和集成电路模块的功率节点之间的至少一个开关装置; 以及开关控制模块，其具有耦合到所述开关装置的第一端子，耦合到控制信号的第二端子，耦合到至少一个跟踪单元的第一存储节点的第三端子，耦合到所述至少一个跟踪单元的第二存储节点的第四端子跟踪单元和耦合到集成电路模块的功率节点的第五端子，用于根据集成电路模块的操作模式控制开关装置将电源电压传递到功率节点，具有或不具有实质的电压降。

6. 发明申请

US20080112212A1 Circuits for improving read and write margins in multi-port SRAMS 有权
标题翻译：用于提高多端口SRAMS中读写余量的电路
公开(公告)号：US20080112212A1
公开(公告)日：2008-05-15
申请号：US11598385
申请日：2006-11-13
申请人： Dao-Ping Wang , Hung-Jen Liao , Kun Lung Chen , Yung-Lung Lin , Jun-Jen Wu , Chen Yen-Huei
发明人： Dao-Ping Wang , Hung-Jen Liao , Kun Lung Chen , Yung-Lung Lin , Jun-Jen Wu , Chen Yen-Huei
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C8/08 , G11C11/413 , G11C11/418
摘要： A system and method for writing a SRAM cell coupled to complimentary first and second bit-lines (BLs) is disclosed, the method comprising asserting a word-line (WL) selecting the SRAM cell to a first positive voltage, providing a second positive voltage at the first BL, providing a first negative voltage at the second BL, and asserting a plurality of WLs not selecting the SRAM cell to a second negative voltage, wherein the writing margin of the SRAM cell is increased.
摘要翻译：公开了一种用于写入耦合到互补的第一和第二位线（BL）的SRAM单元的系统和方法，所述方法包括断言将SRAM单元选择为第一正电压的字线（WL），提供第二正电压在第一BL处，在第二BL处提供第一负电压，并且将不选择SRAM单元的多个WL确定为第二负电压，其中增加了SRAM单元的写入裕度。

7. 发明申请

US20080158939A1 MEMORY HAVING IMPROVED POWER DESIGN 有权
标题翻译：具有改进功率设计的记忆
公开(公告)号：US20080158939A1
公开(公告)日：2008-07-03
申请号：US11619103
申请日：2007-01-02
申请人： Yen-Huei Chen , Hung-Jen Liao , Kun-Lung Chen , Jui-Jen Wu , Yung-Lung Lin , Dao-Ping Wang
发明人： Yen-Huei Chen , Hung-Jen Liao , Kun-Lung Chen , Jui-Jen Wu , Yung-Lung Lin , Dao-Ping Wang
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C11/413
摘要： A memory includes a plurality of cells arranged in a matrix having a plurality of rows and a plurality of columns, wherein each cell is capable of storing a bit. Each cell is coupled between a first power supply node that receives a power supply voltage and a second power supply node that receives a second voltage. A plurality of word lines are associated with the memory cells and supplied by a third voltage in read or write operation. The third voltage is a suppressed power supply voltage. The second voltage is negative in read operation and positive in write operation.
摘要翻译：存储器包括以具有多个行和多个列的矩阵的形式排列的多个单元，其中每个单元能够存储位。每个单元耦合在接收电源电压的第一电源节点和接收第二电压的第二电源节点之间。多个字线与存储器单元相关联并且在读或写操作中由第三电压提供。第三电压是抑制电源电压。读操作中的第二电压为负，写操作为正。

8. 发明授权

US07701755B2 Memory having improved power design 有权
标题翻译：内存具有改进的电源设计
公开(公告)号：US07701755B2
公开(公告)日：2010-04-20
申请号：US11619103
申请日：2007-01-02
申请人： Yen-Huei Chen , Hung-Jen Liao , Kun-Lung Chen , Yung-Lung Lin , Dao-Ping Wang
发明人： Yen-Huei Chen , Hung-Jen Liao , Kun-Lung Chen , Yung-Lung Lin , Dao-Ping Wang
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C11/413
摘要： A memory includes a plurality of cells arranged in a matrix having a plurality of rows and a plurality of columns, wherein each cell is capable of storing a bit. Each cell is coupled between a first power supply node that receives a power supply voltage and a second power supply node that receives a second voltage. A plurality of word lines are associated with the memory cells and supplied by a third voltage in read or write operation. The third voltage is a suppressed power supply voltage. The second voltage is negative in read operation and positive in write operation.
摘要翻译：存储器包括以具有多个行和多个列的矩阵的形式排列的多个单元，其中每个单元能够存储位。每个单元耦合在接收电源电压的第一电源节点和接收第二电压的第二电源节点之间。多个字线与存储器单元相关联并且在读或写操作中由第三电压提供。第三电压是抑制电源电压。读操作中的第二电压为负，写操作为正。

9. 发明申请

US20080184064A1 METHOD AND APPARATUS FOR HIGH EFFICIENCY REDUNDANCY SCHEME FOR MULTI-SEGMENT SRAM 有权
标题翻译：多部分SRAM高效冗余方案的方法与装置
公开(公告)号：US20080184064A1
公开(公告)日：2008-07-31
申请号：US11669667
申请日：2007-01-31
申请人： Jui-Jen Wu , Yung-Lung Lin , Yen-Huei Chen , Dao-Ping Wang
发明人： Jui-Jen Wu , Yung-Lung Lin , Yen-Huei Chen , Dao-Ping Wang
IPC分类号： G06F11/16
CPC分类号： G11C29/808
摘要： The disclosure generally relates to a method and apparatus for a high efficiency redundancy scheme for a memory system. In one embodiment, the disclosure relates to a memory circuit having: a memory array defined by a plurality of memory cells arranged in one or more columns and one or more rows, each memory cell communicating with one of a pair of complementary bit-lines and with a word-line; a plurality of IO circuits, each IO circuit associated with one of the plurality of memory cell columns; a plurality of redundant bit-lines, each redundant bit line communicating with a redundant bit cell; a first circuit for detecting a defective memory cell in said memory circuit; a second circuit for selecting one of the plurality of redundant bit-lines for switching from the failed memory cell to the redundant memory cell; and a third circuit for directing a word-line pulse of said defective memory cell to said selected redundant memory cell.
摘要翻译：本公开一般涉及用于存储器系统的高效冗余方案的方法和装置。在一个实施例中，本公开涉及一种存储器电路，其具有：由多个存储单元限定的存储器阵列，所述多个存储器单元被布置成一列或多列和一行或多行，每个存储器单元与一对互补位线中的一个通信，用字线; 多个IO电路，与所述多个存储单元列之一相关联的每个IO电路; 多个冗余位线，每个冗余位线与冗余位单元通信; 用于检测所述存储器电路中的有缺陷的存储单元的第一电路; 用于选择所述多个冗余位线中的一个用于从所述故障存储器单元切换到所述冗余存储器单元的第二电路; 以及用于将所述有缺陷的存储器单元的字线脉冲引导到所述选择的冗余存储单元的第三电路。

10. 发明授权

US07505319B2 Method and apparatus for high efficiency redundancy scheme for multi-segment SRAM 有权
标题翻译：用于多段SRAM高效冗余方案的方法和装置
公开(公告)号：US07505319B2
公开(公告)日：2009-03-17
申请号：US11669667
申请日：2007-01-31
申请人： Jui-Jen Wu , Yung-Lung Lin , Yen-Huei Chen , Dao-Ping Wang
发明人： Jui-Jen Wu , Yung-Lung Lin , Yen-Huei Chen , Dao-Ping Wang
IPC分类号： G11C11/34
CPC分类号： G11C29/808
摘要： The disclosure generally relates to a method and apparatus for a high efficiency redundancy scheme for a memory system. In one embodiment, the disclosure relates to a memory circuit having: a memory array defined by a plurality of memory cells arranged in one or more columns and one or more rows, each memory cell communicating with one of a pair of complementary bit-lines and with a word-line; a plurality of IO circuits, each IO circuit associated with one of the plurality of memory cell columns; a plurality of redundant bit-lines, each redundant bit line communicating with a redundant bit cell; a first circuit for detecting a defective memory cell in said memory circuit; a second circuit for selecting one of the plurality of redundant bit-lines for switching from the failed memory cell to the redundant memory cell; and a third circuit for directing a word-line pulse of said defective memory cell to said selected redundant memory cell.
摘要翻译：本公开一般涉及用于存储器系统的高效冗余方案的方法和装置。在一个实施例中，本公开涉及一种存储器电路，其具有：由多个存储单元限定的存储器阵列，所述多个存储器单元被布置成一列或多列和一行或多行，每个存储器单元与一对互补位线中的一个通信，用字线; 多个IO电路，与所述多个存储单元列之一相关联的每个IO电路; 多个冗余位线，每个冗余位线与冗余位单元通信; 用于检测所述存储电路中的有缺陷的存储单元的第一电路; 用于选择所述多个冗余位线中的一个用于从所述故障存储器单元切换到所述冗余存储器单元的第二电路; 以及用于将所述有缺陷的存储器单元的字线脉冲引导到所述选择的冗余存储单元的第三电路。

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