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1. 发明授权

US06509646B1 Apparatus for reducing an electrical noise inside a ball grid array package 有权
标题翻译：用于减少球栅阵列封装内的电噪声的装置
公开(公告)号：US06509646B1
公开(公告)日：2003-01-21
申请号：US09575637
申请日：2000-05-22
申请人： Wei-Feng Lin , Chung-Ju Wu , Chen-Wen Tsai
发明人： Wei-Feng Lin , Chung-Ju Wu , Chen-Wen Tsai
IPC分类号： H01L21302
CPC分类号： H01L23/50 , H01L23/49816 , H01L23/552 , H01L2924/0002 , H01L2924/15311 , H01L2924/19106 , H05K1/0231 , H05K3/321 , H05K2201/1053 , H05K2201/10636 , H05K2201/10734 , Y02P70/611 , H01L2924/00
摘要： An apparatus for reducing an electrical noise inside a ball grid array package is disclosed. The apparatus mainly comprises a substrate, a plurality of solder balls and a plurality of inside-connected capacitors. The substrate includes a contact layer, a power plane and a ground plane. The plurality of solder balls are fixed on the contact layer. The plurality of inside-connected capacitors are fixed on the contact layer, and a conductive glue is used to electrically connect the capacitors to the power plane and ground plane to reduce the electrical noise between the power plane and ground plane.
摘要翻译：公开了一种用于减小球栅阵列封装内的电噪声的装置。该装置主要包括基板，多个焊球和多个内部连接的电容器。基板包括接触层，电源平面和接地平面。多个焊球固定在接触层上。多个内部连接的电容器固定在接触层上，并且使用导电胶将电容器电连接到电源平面和接地平面，以减小电力平面和接地面之间的电气噪声。

2. 发明授权

US06653574B2 Multi-layered substrate with a built-in capacitor design and a method of making the same 失效
公开(公告)号：US06653574B2
公开(公告)日：2003-11-25
申请号：US09935913
申请日：2001-08-23
申请人： Chen-Wen Tsai , Chung-Ju Wu , Wei-Feng Lin
发明人： Chen-Wen Tsai , Chung-Ju Wu , Wei-Feng Lin
IPC分类号： H05K116
CPC分类号： H05K1/162 , H01L23/49822 , H01L23/49827 , H01L2924/0002 , H05K3/429 , H05K3/4652 , H05K2201/0187 , H05K2201/0209 , H05K2201/0347 , Y10T29/49165 , H01L2924/00
摘要： A multi-layered substrate having built-in capacitors is disclosed. The substrate comprises at least one high permittivity of dielectric material filled in the through holes between the power plane and the ground plane so as to form capacitors. The built in capacitors are to decouple high frequency noise due to the voltage fluctuation.

3. 发明授权

US06395996B1 Multi-layered substrate with a built-in capacitor design 失效
标题翻译：具有内置电容设计的多层基板
公开(公告)号：US06395996B1
公开(公告)日：2002-05-28
申请号：US09571242
申请日：2000-05-16
申请人： Chen-Wen Tsai , Chung-Ju Wu , Wei-Feng Lin
发明人： Chen-Wen Tsai , Chung-Ju Wu , Wei-Feng Lin
IPC分类号： H05K116
CPC分类号： H05K1/162 , H01L23/49822 , H01L23/49827 , H01L2924/0002 , H05K3/429 , H05K3/4652 , H05K2201/0187 , H05K2201/0209 , H05K2201/0347 , Y10T29/49165 , H01L2924/00
摘要： A multi-layered substrate having built-in capacitors is used to decouple high frequency noise generated by voltage fluctuations between a power plane and a ground plane of a multi-layered substrate. At least one kind of dielectric material, which is filled in through holes between the power plane and the ground plane, with high dielectric constant is used to form the built-in capacitors.
摘要翻译：使用具有内置电容器的多层基板来分离由多层基板的功率平面和接地平面之间的电压波动产生的高频噪声。使用以介电常数填充在功率面和接地面之间的通孔中的至少一种介电材料来形成内置的电容器。

4. 发明授权

US06365970B1 Bond pad structure and its method of fabricating 有权
标题翻译：焊盘结构及其制造方法
公开(公告)号：US06365970B1
公开(公告)日：2002-04-02
申请号：US09458778
申请日：1999-12-10
申请人： Chen-Wen Tsai , Chung-Ju Wu , Wei-Feng Lin
发明人： Chen-Wen Tsai , Chung-Ju Wu , Wei-Feng Lin
IPC分类号： H01L2348
CPC分类号： H01L24/05 , H01L24/03 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05001 , H01L2224/05083 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05554 , H01L2224/05555 , H01L2224/05624 , H01L2224/45124 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2224/48724 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/04941 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： A bond pad structure and a method of fabricating such structure are disclosed in the invention. The bond pad structure is formed over a predetermined area defined on a semiconductor substrate. The bond pad structure includes at least two metal layers formed over the predetermined area and at least one sub-structure combination layer which each is formed over the predetermined area and formed between two corresponding first metal layers. Each sub-structure combination layer includes a dielectric layer formed over the predetermined area, formed-through via openings with special disposition on the dielectric layer, a first diffusion barrier layer formed over the dielectric layer and the sidewalls and bottom of the via openings, a metal material filled into the via openings to form via plugs, and a second diffusion barrier layer formed over the first diffusion barrier layer and via plugs. Due to special disposition of via plugs and well adhesion between metal layer and diffusion barrier layers, the bond pad structure, according to the invention, can prevent form damage possibly induced during subsequent probe test procedure and wire bonding process.
摘要翻译：本发明公开了一种焊盘结构及其制造方法。接合焊盘结构形成在限定在半导体衬底上的预定区域上。接合焊盘结构包括在预定区域上形成的至少两个金属层和至少一个子结构组合层，每个子结构组合层形成在预定区域上并形成在两个对应的第一金属层之间。每个子结构组合层包括形成在预定区域上的电介质层，形成在电介质层上的特殊布置的通孔通孔，形成在电介质层上的第一扩散阻挡层和通孔开口的侧壁和底部，填充到通孔中以形成通孔的金属材料，以及形成在第一扩散阻挡层和经由插塞上的第二扩散阻挡层。由于通孔的特殊布置以及金属层与扩散阻挡层之间的良好的粘合性，根据本发明的接合焊盘结构可以防止在随后的探针测试程序和引线接合过程中可能引起的形式损坏。

5. 发明授权

US6116427A Tray for ball grid array devices 有权
标题翻译：球栅阵列装置托盘
公开(公告)号：US6116427A
公开(公告)日：2000-09-12
申请号：US494891
申请日：2000-01-31
申请人： Chung-Ju Wu , Wei-Feng Lin , Chen-Wen Tsai
发明人： Chung-Ju Wu , Wei-Feng Lin , Chen-Wen Tsai
IPC分类号： H01L21/673 , H05K13/00 , B65D73/02
CPC分类号： H01L21/67333 , H05K13/0084
摘要： A tray is adapted to receive a plurality of ball grid array devices therein, and includes a base plate having a device-receiving portion and a peripheral portion around the device-receiving portion. The device-receiving portion has a top side formed with a device-receiving recess. The top side of the device-receiving portion is further formed with a partition unit in the device-receiving recess for dividing the device-receiving recess into a plurality of cavities adapted for receiving the ball grid array devices respectively therein. The device-receiving portion further has a bottom side formed with a plurality of openings. Each of the openings is aligned with a corresponding one of the cavities and is adapted to receive an array of ball contacts formed on a bottom side of the ball grid array device that is disposed in the corresponding one of the cavities therein. The openings are grouped into a set of first openings remote from the peripheral portion and a set of second openings surrounding the first openings and adjacent to the peripheral portion. Guard strips are formed on the bottom side of the device-receiving portion and are disposed solely and respectively in the second openings.
摘要翻译：托盘适于在其中容纳多个球栅阵列器件，并且包括具有器件接收部分和围绕器件接收部分的周边部分的基板。装置接收部分具有形成有装置容纳凹部的顶侧。装置接收部分的顶侧还在装置容纳凹槽中形成有分隔单元，用于将装置容纳凹槽分成适于分别容纳球栅阵列装置的多个空腔。装置接收部还具有形成有多个开口的底侧。每个开口与相应的一个空腔对准，并且适于接收形成在球栅阵列器件的底侧上的球形触点阵列，其布置在其中的相应的一个空腔中。开口被分组成远离周边部分的一组第一开口和围绕第一开口并且邻近周边部分的一组第二开口。保护条形成在装置接收部分的底侧上，并且分别单独设置在第二开口中。

6. 发明授权

US06838756B2 Chip-packaging substrate 失效
标题翻译：芯片封装基板
公开(公告)号：US06838756B2
公开(公告)日：2005-01-04
申请号：US10227266
申请日：2002-08-26
申请人： Wei-Feng Lin , Chung-Ju Wu , Chen-Wen Tsai
发明人： Wei-Feng Lin , Chung-Ju Wu , Chen-Wen Tsai
IPC分类号： H01L23/13 , H01L23/495
CPC分类号： H01L23/13 , H01L2924/0002 , H01L2924/00
摘要： A chip-packaging substrate. The substrate is capable of reducing damage during packaging, shrinking its connecting portions so that the length of any of the gap slots between the packaging portion and the frame portion of the substrate is increased. Furthermore, a dummy layer is provided to one surface of the frame portion to flush the surface on the frame portion with that of the packaging portion as much as possible.
摘要翻译：芯片封装基板。该基板能够减少封装期间的损坏，使其连接部分收缩，使得封装部分和基板的框架部分之间的任何间隙的长度增加。此外，在框架部分的一个表面上设置虚拟层，以尽可能多地将框架部分的表面与包装部分的表面齐平。

7. 发明授权

US06524942B2 Bond pad structure and its method of fabricating 失效
公开(公告)号：US06524942B2
公开(公告)日：2003-02-25
申请号：US10056004
申请日：2002-01-28
申请人： Chen-Wen Tsai , Chung-Ju Wu , Wei-Feng Lin
发明人： Chen-Wen Tsai , Chung-Ju Wu , Wei-Feng Lin
IPC分类号： H01L2144
CPC分类号： H01L24/05 , H01L24/03 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05001 , H01L2224/05083 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05554 , H01L2224/05555 , H01L2224/05624 , H01L2224/45124 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2224/48724 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/04941 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： A bond pad structure and a method of fabricating such structure are disclosed in the invention. The bond pad structure is formed over a predetermined area defined on a semiconductor substrate. The bond pad structure includes at least two metal layers formed over the predetermined area and at least one sub-structure combination layer which each is formed over the predetermined area and formed between two corresponding first metal layers. Each sub-structure combination layer includes a dielectric layer formed over the predetermined area, formed-through via openings with special disposition on the dielectric layer, a first diffusion barrier layer formed over the dielectric layer and the sidewalls and bottom of the via openings, a metal material filled into the via openings to form via plugs, and a second diffusion barrier layer formed over the first diffusion barrier layer and via plugs. Due to special disposition of via plugs and well adhesion between metal layer and diffusion barrier layers, the bond pad structure, according to the invention, can prevent form damage possibly induced during subsequent probe test procedure and wire bonding process.

8. 发明申请

US20050093136A1 Thermal dissipating element of a chip 审中-公开
标题翻译：芯片的散热元件
公开(公告)号：US20050093136A1
公开(公告)日：2005-05-05
申请号：US10698476
申请日：2003-11-03
申请人： Wei-Chi Liu , Wei-Feng Lin , Chung-Ju Wu
发明人： Wei-Chi Liu , Wei-Feng Lin , Chung-Ju Wu
IPC分类号： H01L23/10 , H01L23/433
CPC分类号： H01L23/4334 , H01L2224/49175 , H01L2924/16152 , H01L2924/181 , H01L2924/00012
摘要： The present invention relates to a thermal dissipating element of a chip to dissipate heat producing by operating the chip. The thermal dissipating element includes a cover and a lump. The cover includes a top plate and a side plate, wherein the top plate curves and extendedly connects to the side plate. The lump is fastened between the chip and the top plate of the cover.
摘要翻译：本发明涉及一种芯片的散热元件，用于散发通过操作芯片产生的热量。散热元件包括盖和块。该盖包括顶板和侧板，其中顶板弯曲并且延伸地连接到侧板。该块被固定在芯片和盖板的顶板之间。

9. 发明授权

US06744128B2 Integrated circuit package capable of improving signal quality 有权
标题翻译：集成电路封装，能够提高信号质量
公开(公告)号：US06744128B2
公开(公告)日：2004-06-01
申请号：US10262958
申请日：2002-10-03
申请人： Chung-Ju Wu , Kuei-Chen Liang , Wei-Feng Lin
发明人： Chung-Ju Wu , Kuei-Chen Liang , Wei-Feng Lin
IPC分类号： H01L2302
CPC分类号： H01L23/49833 , H01L23/642 , H01L2924/0002 , H01L2924/15311 , H01L2924/19105 , H01L2924/00
摘要： An integrated circuit package capable of improving signal quality is disclosed. The integrated circuit package comprises a first substrate, an integrated circuit chip attached on the first surface of the first substrate. This integrated circuit package further comprises a plurality of external terminals mounted on the first substrate and a plurality of first bonding pads mounted on the edge portion of the first surface of the first substrate and respectively connected to the corresponding external terminals. Also, the integrated circuit package further comprises a second substrate and a plurality of second bonding pads mounted on the second surface of the second substrate and connected to the first bonding pads formed on the first substrate. Furthermore, this integrated circuit package further comprises a plurality of passive components disposed on the second substrate.
摘要翻译：公开了能够提高信号质量的集成电路封装。集成电路封装包括第一衬底，附接在第一衬底的第一表面上的集成电路芯片。该集成电路封装还包括安装在第一基板上的多个外部端子和安装在第一基板的第一表面的边缘部分上并分别连接到相应的外部端子的多个第一接合焊盘。此外，集成电路封装还包括第二衬底和安装在第二衬底的第二表面上并连接到形成在第一衬底上的第一焊盘的多个第二焊盘。此外，该集成电路封装还包括设置在第二基板上的多个无源部件。

10. 发明申请

US20050117296A1 Ball grid array package with heat sink device 有权
标题翻译：具有散热装置的球栅阵列封装
公开(公告)号：US20050117296A1
公开(公告)日：2005-06-02
申请号：US10724891
申请日：2003-12-02
申请人： Chung-Ju Wu , Wei-Feng Lin
发明人： Chung-Ju Wu , Wei-Feng Lin
IPC分类号： H01L23/40 , H05K7/20
CPC分类号： H01L23/4093 , H01L2924/15311 , H01L2924/16152
摘要： The present invention provides the heat sink device for the ball grid array package to improve the heat dissipation. The heat sink device includes a first part of heat sink assembly that comprises a heat dissipating element above the heat sink body and is used to increase the heat dissipating area; and at least two conductive pillars on the backsides of the heat sink body, which is used to fix the heat sink assembly with PC board and also conducting the heat flux from thermal source to heat dissipation element; a conductive protruding block on the backside of the heat sink body, wherein the conductive protruding block used to associate with the cavity of the ball grid array package to increase the heat conductivity. In addition, the second part of the heat sink assembly comprises a bottom plate that used to contact with the backside of the PC board, so as to increase the heat dissipation to remove the heat that is generated from the PC board, and to join the at least two conductive pillars of the heat sink body to fix the heat sink assembly on the PC board.
摘要翻译：本发明提供了一种用于球栅阵列封装的散热装置，以改善散热。散热装置包括散热器组件的第一部分，其包括散热体上方的散热元件，并用于增加散热面积; 以及用于将散热器组件与PC板固定并且还将热源从热源传导到散热元件的散热体本体的背面上的至少两个导电柱; 在散热体本体背面的导电突出块，其中用于与球栅阵列封装的空腔相关联的导电突出块以增加热导率。此外，散热器组件的第二部分包括用于与PC板的背面接触的底板，以便增加散热以去除由PC板产生的热量，并且加入至少两个散热体主体的导电柱，以将散热器组件固定在PC板上。

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