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1. 发明授权

US08241823B2 Method of fabrication of a semiconductor device having reduced pitch 有权
标题翻译：具有减小的间距的半导体器件的制造方法
公开(公告)号：US08241823B2
公开(公告)日：2012-08-14
申请号：US13248932
申请日：2011-09-29
申请人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Shao-Ming Yu , Chang-Yun Chang , Jeff J. Xu , Clement Hsingjen Wann
发明人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Shao-Ming Yu , Chang-Yun Chang , Jeff J. Xu , Clement Hsingjen Wann
IPC分类号： G03G5/00 , H01L21/302 , H01L21/461
CPC分类号： H01L27/0203 , G03F1/00 , G03F1/36 , H01L21/3086 , H01L21/823431 , H01L29/66795
摘要： Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region.
摘要翻译：提供了一种包括光掩模的光刻设备。光掩模包括具有多个特征的图案，在示例中为虚线特征。该图案包括呈局部网格阵列形式的第一区域和其中至少一个特征具有增加的宽度的第二区域。该装置可以包括可以限定有源区域的第二光掩模。具有增加的宽度的特征可以与所定义的有效区域相邻并且在外部。

2. 发明授权

US08039179B2 Integrated circuit layout design 有权
标题翻译：集成电路布局设计
公开(公告)号：US08039179B2
公开(公告)日：2011-10-18
申请号：US12980764
申请日：2010-12-29
申请人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Shao-Ming Yu , Chang-Yun Chang , Jeff J. Xu , Clement Hsingjen Wann
发明人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Shao-Ming Yu , Chang-Yun Chang , Jeff J. Xu , Clement Hsingjen Wann
IPC分类号： G03C5/00 , G03F9/00
CPC分类号： H01L27/0203 , G03F1/00 , G03F1/36 , H01L21/3086 , H01L21/823431 , H01L29/66795
摘要： Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality, of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region.
摘要翻译：提供了一种包括光掩模的光刻设备。光掩模包括具有多个特征的图案，在示例中为假线特征。该图案包括呈局部网格阵列形式的第一区域和其中至少一个特征具有增加的宽度的第二区域。该装置可以包括可以限定有源区域的第二光掩模。具有增加的宽度的特征可以与所定义的有效区域相邻并且在外部。

3. 发明申请

US20110151359A1 INTEGRATED CIRCUIT LAYOUT DESIGN 有权
标题翻译：集成电路布局设计
公开(公告)号：US20110151359A1
公开(公告)日：2011-06-23
申请号：US12980764
申请日：2010-12-29
申请人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Shao-Ming Yu , Chang-Yun Chang , Jeff J. Xu , Clement Hsingjen Wann
发明人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Shao-Ming Yu , Chang-Yun Chang , Jeff J. Xu , Clement Hsingjen Wann
IPC分类号： G03F1/00 , G03F7/20 , G06F17/50
CPC分类号： H01L27/0203 , G03F1/00 , G03F1/36 , H01L21/3086 , H01L21/823431 , H01L29/66795
摘要： Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality, of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region.
摘要翻译：提供了一种包括光掩模的光刻设备。光掩模包括具有多个特征的图案，在示例中为假线特征。该图案包括呈局部网格阵列形式的第一区域和其中至少一个特征具有增加的宽度的第二区域。该装置可以包括可以限定有源区域的第二光掩模。具有增加的宽度的特征可以与所定义的有效区域相邻并且在外部。

4. 发明授权

US07862962B2 Integrated circuit layout design 有权
标题翻译：集成电路布局设计
公开(公告)号：US07862962B2
公开(公告)日：2011-01-04
申请号：US12356405
申请日：2009-01-20
申请人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Shao-Ming Yu , Chang-Yun Chang , Jeff J. Xu , Clement Hsingjen Wann
发明人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Shao-Ming Yu , Chang-Yun Chang , Jeff J. Xu , Clement Hsingjen Wann
IPC分类号： G03F9/00 , G03C5/00
CPC分类号： H01L27/0203 , G03F1/00 , G03F1/36 , H01L21/3086 , H01L21/823431 , H01L29/66795
摘要： Provided is a method including layout design of an integrated circuit. A first pattern is provided. The first pattern includes an array of dummy line features and a plurality of spacer elements abutting the dummy line features. A second pattern is provided. The second pattern defines an active region of an integrated circuit device. An edge spacer element of the active region is determined. A dummy line feature of the array of dummy line features is biased (e.g., increased in width), the dummy line feature is adjacent an edge spacer element.
摘要翻译：提供了一种包括集成电路的布局设计的方法。提供了第一种模式。第一图案包括虚线特征的阵列和与虚线特征相邻的多个间隔元件。提供了第二种模式。第二图案定义了集成电路器件的有源区。确定有源区的边缘间隔元件。假线特征阵列的虚线特征被偏置（例如，宽度增加），虚线特征与边缘间隔元件相邻。

5. 发明申请

US20120021589A1 METHOD OF FABRICATION OF A SEMICONDUCTOR DEVICE HAVING REDUCED PITCH 有权
标题翻译：具有减少电极的半导体器件的制造方法
公开(公告)号：US20120021589A1
公开(公告)日：2012-01-26
申请号：US13248932
申请日：2011-09-29
申请人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Shao-Ming Yu , Chang-Yun Chang , Jeff J. Xu , Clement Hsingjen Wann
发明人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Shao-Ming Yu , Chang-Yun Chang , Jeff J. Xu , Clement Hsingjen Wann
IPC分类号： H01L21/311 , H01L21/30
CPC分类号： H01L27/0203 , G03F1/00 , G03F1/36 , H01L21/3086 , H01L21/823431 , H01L29/66795
摘要： Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region.
摘要翻译：提供了一种包括光掩模的光刻设备。光掩模包括具有多个特征的图案，在示例中为虚线特征。该图案包括呈局部网格阵列形式的第一区域和其中至少一个特征具有增加的宽度的第二区域。该装置可以包括可以限定有源区域的第二光掩模。具有增加的宽度的特征可以与所定义的有效区域相邻并且在外部。

6. 发明申请

US20100183961A1 INTEGRATED CIRCUIT LAYOUT DESIGN 有权
标题翻译：集成电路布局设计
公开(公告)号：US20100183961A1
公开(公告)日：2010-07-22
申请号：US12356405
申请日：2009-01-20
申请人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Shao-Ming Yu , Chang-Yun Chang , Jeff J. Xu , Clement Hsingjen Wann
发明人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Shao-Ming Yu , Chang-Yun Chang , Jeff J. Xu , Clement Hsingjen Wann
IPC分类号： G03F7/20 , G06F17/50 , G03F1/00 , G03F7/40
CPC分类号： H01L27/0203 , G03F1/00 , G03F1/36 , H01L21/3086 , H01L21/823431 , H01L29/66795
摘要： Provided is a method including layout design of an integrated circuit. A first pattern is provided. The first pattern includes an array of dummy line features and a plurality of spacer elements abutting the dummy line features. A second pattern is provided. The second pattern defines an active region of an integrated circuit device. An edge spacer element of the active region is determined. A dummy line feature of the array of dummy line features is biased (e.g., increased in width), the dummy line feature is adjacent an edge spacer element.
摘要翻译：提供了一种包括集成电路的布局设计的方法。提供了第一种模式。第一图案包括虚线特征的阵列和与虚线特征相邻的多个间隔元件。提供了第二种模式。第二图案定义了集成电路器件的有源区。确定有源区的边缘间隔元件。假线特征阵列的虚线特征被偏置（例如，宽度增加），虚线特征与边缘间隔元件相邻。

7. 发明授权

US09324866B2 Structure and method for transistor with line end extension 有权
标题翻译：具有线端延伸的晶体管的结构和方法
公开(公告)号：US09324866B2
公开(公告)日：2016-04-26
申请号：US13356235
申请日：2012-01-23
申请人： Shao-Ming Yu , Chang-Yun Chang , Chih-Hao Chang , Hsin-Chih Chen , Kai-Tai Chang , Ming-Feng Shieh , Kuei-Liang Lu , Yi-Tang Lin
发明人： Shao-Ming Yu , Chang-Yun Chang , Chih-Hao Chang , Hsin-Chih Chen , Kai-Tai Chang , Ming-Feng Shieh , Kuei-Liang Lu , Yi-Tang Lin
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/78 , H01L29/417 , H01L29/66
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L29/0653 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/41783 , H01L29/41791 , H01L29/66545 , H01L29/66636 , H01L29/66795 , H01L29/785
摘要： The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate; an isolation feature formed in the semiconductor substrate; a first active region and a second active region formed in the semiconductor substrate, wherein the first and second active regions extend in a first direction and are separated from each other by the isolation feature; and a dummy gate disposed on the isolation feature, wherein the dummy gate extends in the first direction to the first active region from one side and to the second active region from another side.
摘要翻译：本公开提供了一种半导体结构。半导体结构包括半导体衬底; 形成在半导体衬底中的隔离特征; 形成在所述半导体衬底中的第一有源区和第二有源区，其中所述第一和第二有源区在第一方向上延伸并且通过隔离特征彼此分离; 以及设置在所述隔离特征上的伪栅极，其中所述伪栅极在第一方向上从另一侧的一侧延伸到所述第一有源区域并且从另一侧向所述第二有源区域延伸。

8. 发明申请

US20130187237A1 STRUCTURE AND METHOD FOR TRANSISTOR WITH LINE END EXTENSION 有权
标题翻译：具有线端延伸的晶体管的结构和方法
公开(公告)号：US20130187237A1
公开(公告)日：2013-07-25
申请号：US13356235
申请日：2012-01-23
申请人： Shao-Ming Yu , Chang-Yun Chang , Chih-Hao Chang , Hsin-Chih Chen , Kai-Tai Chang , Ming-Feng Shieh , Kuei-Liang Lu , Yi-Tang Lin
发明人： Shao-Ming Yu , Chang-Yun Chang , Chih-Hao Chang , Hsin-Chih Chen , Kai-Tai Chang , Ming-Feng Shieh , Kuei-Liang Lu , Yi-Tang Lin
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L29/0653 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/41783 , H01L29/41791 , H01L29/66545 , H01L29/66636 , H01L29/66795 , H01L29/785
摘要： The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate; an isolation feature formed in the semiconductor substrate; a first active region and a second active region formed in the semiconductor substrate, wherein the first and second active regions extend in a first direction and are separated from each other by the isolation feature; and a dummy gate disposed on the isolation feature, wherein the dummy gate extends in the first direction to the first active region from one side and to the second active region from another side.
摘要翻译：本公开提供了一种半导体结构。半导体结构包括半导体衬底; 形成在半导体衬底中的隔离特征; 形成在所述半导体衬底中的第一有源区和第二有源区，其中所述第一和第二有源区在第一方向上延伸并且通过隔离特征彼此分离; 以及设置在所述隔离特征上的伪栅极，其中所述伪栅极在第一方向上从另一侧的一侧延伸到所述第一有源区域并且从另一侧向所述第二有源区域延伸。

9. 发明申请

US20120009690A1 IN-SITU SPECTROMETRY 审中-公开
标题翻译：现场光谱
公开(公告)号：US20120009690A1
公开(公告)日：2012-01-12
申请号：US12834617
申请日：2010-07-12
申请人： Clement Hsingjen Wann , Hung-Ming Chen , Chang-Yun Chang , Sey-Ping Sun
发明人： Clement Hsingjen Wann , Hung-Ming Chen , Chang-Yun Chang , Sey-Ping Sun
IPC分类号： H01L21/66 , B08B3/04
CPC分类号： H01L21/67075 , H01L21/67276 , H01L22/12
摘要： The present disclosure provides a system for in-situ spectrometry. The system includes a wafer-cleaning machine that cleans a surface of a semiconductor wafer using a cleaning solution. The system also includes a spectrometry machine that is coupled to the wafer-cleaning machine. The spectrometry machine receives a portion of the cleaning solution from the wafer-cleaning machine. The portion of the cleaning solution collects particles from the wafer during the cleaning. The spectrometry machine is operable to analyze a particle composition of a portion of the wafer based on the portion of the cleaning solution, while the wafer remains in the wafer-cleaning machine during the particle composition analysis.
摘要翻译：本公开提供了一种用于原位光谱法的系统。该系统包括使用清洁溶液清洁半导体晶片的表面的晶片清洁机。该系统还包括耦合到晶片清洁机的光谱测定机。光谱测定机从晶片清洁机接收清洁溶液的一部分。在清洁期间，清洁溶液的一部分从晶片收集颗粒。光谱测定仪可操作以基于清洁溶液的一部分分析晶片的一部分的颗粒组成，同时在颗粒组成分析期间晶片保留在晶片清洁机中。

10. 发明授权

US09484462B2 Fin structure of fin field effect transistor 有权
标题翻译：翅片场效应晶体管的鳍结构
公开(公告)号：US09484462B2
公开(公告)日：2016-11-01
申请号：US12766233
申请日：2010-04-23
申请人： Feng Yuan , Hung-Ming Chen , Tsung-Lin Lee , Chang-Yun Chang , Clement Hsingjen Wann
发明人： Feng Yuan , Hung-Ming Chen , Tsung-Lin Lee , Chang-Yun Chang , Clement Hsingjen Wann
IPC分类号： H01L29/06 , H01L29/78 , H01L29/66
CPC分类号： H01L29/66795 , H01L21/308 , H01L29/7851 , H01L29/7853
摘要： An exemplary structure for the fin field effect transistor comprises a substrate comprising a major surface; a plurality of fin structures protruding from the major surface of the substrate, wherein each fin structure comprises an upper portion and a lower portion separated at a transition location at where the sidewall of the fin structure is at an angle of 85 degrees to the major surface of the substrate, wherein the upper portion has sidewalls that are substantially perpendicular to the major surface of the substrate and a top surface having a first width, wherein the lower portion has tapered sidewalls on opposite sides of the upper portion and a base having a second width larger than the first width; and a plurality of isolation structures between the fin structures, wherein each isolation structure extends from the major surface of the substrate to a point above the transition location.
摘要翻译：鳍状场效应晶体管的示例性结构包括：包括主表面的衬底; 多个翅片结构，从所述基底的主表面突出，其中每个翅片结构包括在翅片结构的侧壁与主表面成85度角的过渡位置处分离的上部和下部，其中所述上部具有基本上垂直于所述基底的主表面的侧壁和具有第一宽度的顶表面，其中所述下部具有在所述上部的相对侧上的锥形侧壁和具有第二宽度的基部宽度大于第一宽度; 以及在翅片结构之间的多个隔离结构，其中每个隔离结构从基板的主表面延伸到过渡位置上方的点。

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