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1. 发明授权

US06937075B2 Method and apparatus for reducing lock time in dual charge-pump phase-locked loops 有权
标题翻译：减少双电荷泵锁相环锁定时间的方法和装置
公开(公告)号：US06937075B2
公开(公告)日：2005-08-30
申请号：US10447697
申请日：2003-05-29
申请人： Chee How Lim , Keng L. Wong , Rachael Parker
发明人： Chee How Lim , Keng L. Wong , Rachael Parker
IPC分类号： H03L7/089 , H03L7/093 , H03L7/107 , H03L7/06
CPC分类号： H03L7/107 , H03L7/0893 , H03L7/093 , H03L7/1072 , H03L2207/06
摘要： A phase-locked loop includes a phase detector to measure a phase offset between a reference clock signal and a feedback clock signal, and to generate first and second output control signals having a pulse width corresponding to the phase offset. The phase locked loop further includes a first pulse width control circuit coupled to the phase detector to reduce the pulse width of the first output control signal producing a first modified output control signal, a second pulse width control circuit coupled to the phase detector to reduce the pulse width of the second output control signal producing a second modified output control signal, a first charge pump coupled to the phase detector to provide a first charge signal responsive to the first and second output control signals, and a second charge pump coupled to the first and second pulse width control circuits to provide a second charge signal responsive to the first and second modified output control signals.
摘要翻译：锁相环包括用于测量参考时钟信号和反馈时钟信号之间的相位偏移的相位检测器，并且产生具有对应于相位偏移的脉冲宽度的第一和第二输出控制信号。锁相环还包括耦合到相位检测器的第一脉冲宽度控制电路，以减小产生第一修改输出控制信号的第一输出控制信号的脉冲宽度，耦合到相位检测器的第二脉宽控制电路，第二输出控制信号的脉冲宽度产生第二修改输出控制信号，第一电荷泵耦合到相位检测器以响应于第一和第二输出控制信号提供第一电荷信号，以及耦合到第一输出控制信号的第二电荷泵和第二脉冲宽度控制电路，以响应于第一和第二修改的输出控制信号提供第二充电信号。

2. 发明授权

US07813507B2 Method and system for creating random cryptographic keys in hardware 有权
标题翻译：用于在硬件中创建随机加密密钥的方法和系统
公开(公告)号：US07813507B2
公开(公告)日：2010-10-12
申请号：US11112817
申请日：2005-04-21
申请人： Ernie Brickell , Rachael Parker
发明人： Ernie Brickell , Rachael Parker
IPC分类号： H04L9/00 , H04K1/00
CPC分类号： H04L9/0662 , H04L9/0869
摘要： A method and system for creating random cryptographic keys in hardware is described. One or more bits are generated via one or more random bit circuits. Each random bit circuit includes a sensing device coupled to a first device and a second device to compare the first device against the second device and to generate a random bit from a random state value. The generated bits from the random bit circuits are read, and a cryptographic key may then be computed based on the generated bits.
摘要翻译：描述了一种用于在硬件中创建随机加密密钥的方法和系统。经由一个或多个随机位电路产生一个或多个位。每个随机位电路包括耦合到第一设备的感测设备和用于将第一设备与第二设备进行比较并从随机状态值生成随机位的第二设备。读取来自随机位电路的生成位，然后可以基于所生成的位来计算加密密钥。

3. 发明申请

US20050212584A1 Fuse sense circuit 有权
公开(公告)号：US20050212584A1
公开(公告)日：2005-09-29
申请号：US11127365
申请日：2005-05-11
申请人： Rachael Parker , Martin Denham
发明人： Rachael Parker , Martin Denham
IPC分类号： G01R19/00 , G11C17/18 , H03F3/45
CPC分类号： G11C17/18
摘要： A fuse sense circuit has a sense amplifier and a post amplifier (gain stage). The sense amplifier has a reference branch and one or more sense (or fuse) branches. The fuse sense circuit determines the state of the fuses using safe currents and provides much higher gain than prior art. The post amplifier is a scaled replica of the reference branch or one of the sense branches in that the devices in the post amplifier maintain the same ratio as similar devices in the reference branch, and components in the post amplifier each matches components in the reference branch. The sense amplifier output is interpreted by the post amplifier's matched gain stage and has a trip point that sufficiently tracks the reference voltage. The result is reduced process and voltage sensitivity, which allows lower differential fuse resistance to be accurately detected with a non-ideal sense amplifier. Multiple gain stages may be added to multiple sense branches for redundancy and single-ended sensing.

4. 发明申请

US20050200386A1 Fuse sense circuit 有权
公开(公告)号：US20050200386A1
公开(公告)日：2005-09-15
申请号：US11127750
申请日：2005-05-11
申请人： Rachael Parker , Martin Denham
发明人： Rachael Parker , Martin Denham
IPC分类号： G01R19/00 , G11C17/18 , H03F3/45
CPC分类号： G11C17/18
摘要： A fuse sense circuit has a sense amplifier and a post amplifier (gain stage). The sense amplifier has a reference branch and one or more sense (or fuse) branches. The fuse sense circuit determines the state of the fuses using safe currents and provides much higher gain than prior art. The post amplifier is a scaled replica of the reference branch or one of the sense branches in that the devices in the post amplifier maintain the same ratio as similar devices in the reference branch, and components in the post amplifier each matches components in the reference branch. The sense amplifier output is interpreted by the post amplifier's matched gain stage and has a trip point that sufficiently tracks the reference voltage. The result is reduced process and voltage sensitivity, which allows lower differential fuse resistance to be accurately detected with a non-ideal sense amplifier. Multiple gain stages may be added to multiple sense branches for redundancy and single-ended sensing.

5. 发明申请

US20060239461A1 Method and system for creating random cryptographic keys in hardware 有权
标题翻译：用于在硬件中创建随机加密密钥的方法和系统
公开(公告)号：US20060239461A1
公开(公告)日：2006-10-26
申请号：US11112817
申请日：2005-04-21
申请人： Ernie Brickell , Rachael Parker
发明人： Ernie Brickell , Rachael Parker
IPC分类号： H04L9/00
CPC分类号： H04L9/0662 , H04L9/0869
摘要： A method and system for creating random cryptographic keys in hardware is described. One or more bits are generated via one or more random bit circuits. Each random bit circuit includes a sensing device coupled to a first device and a second device to compare the first device against the second device and to generate a random bit from a random state value. The generated bits from the random bit circuits are read, and a cryptographic key may then be computed based on the generated bits.
摘要翻译：描述了一种用于在硬件中创建随机加密密钥的方法和系统。经由一个或多个随机位电路产生一个或多个位。每个随机位电路包括耦合到第一设备的感测设备和用于将第一设备与第二设备进行比较并从随机状态值生成随机位的第二设备。读取来自随机位电路的生成位，然后可以基于所生成的位来计算加密密钥。

6. 发明申请

US20050242852A1 Methods and apparatuses for detecting clock loss in a phase-locked loop 失效
标题翻译：在锁相环中检测时钟损耗的方法和装置
公开(公告)号：US20050242852A1
公开(公告)日：2005-11-03
申请号：US10836645
申请日：2004-04-30
申请人： Rachael Parker , Hon-Mo Law , Timothy Low
发明人： Rachael Parker , Hon-Mo Law , Timothy Low
IPC分类号： H03L7/00 , H03L7/08 , H03L7/089
CPC分类号： H03L7/08 , H03L7/0891
摘要： Embodiments of the present invention describe methods and apparatuses for detecting signal loss in circuits such as a phase-locked loop (PLL). In one embodiment a PLL is equipped with detection logic to detect loss of a reference clock provided to the PLL and a feedback clock generated by the PLL.
摘要翻译：本发明的实施例描述了用于检测诸如锁相环（PLL）的电路中的信号丢失的方法和装置。在一个实施例中，PLL配备有检测逻辑以检测提供给PLL的参考时钟的损耗和由PLL产生的反馈时钟。

7. 发明申请

US20070075753A1 Duty cycle measurement circuit 审中-公开
标题翻译：占空比测量电路
公开(公告)号：US20070075753A1
公开(公告)日：2007-04-05
申请号：US11240761
申请日：2005-09-30
申请人： Rachael Parker , Mark Neidengard , Shamsul Abedin
发明人： Rachael Parker , Mark Neidengard , Shamsul Abedin
IPC分类号： H03B19/00
CPC分类号： G01R29/02
摘要： A duty cycle measurement circuit and method of operation is described that is particularly well adapted for use in microelectronics devices. In one embodiment, the circuit the includes a clock signal selector to alternately select the high or the low phase of an input clock signal, a sweep circuit to sweep a timing parameter through a range, and a latch to compare the clock signal to the timing parameter and generate a result.
摘要翻译：描述了一种占空比测量电路和操作方法，其特别适用于微电子器件。在一个实施例中，电路包括时钟信号选择器，用于交替地选择输入时钟信号的高相位或低相位，扫描电路以扫描定时参数通过一个范围，以及锁存器，以将时钟信号与定时参数并生成结果。

8. 发明申请

US20050200385A1 Fuse sense circuit 有权
标题翻译：保险丝检测电路
公开(公告)号：US20050200385A1
公开(公告)日：2005-09-15
申请号：US11127501
申请日：2005-05-11
申请人： Rachael Parker , Martin Denham
发明人： Rachael Parker , Martin Denham
IPC分类号： G01R19/00 , G11C17/18 , H03F3/45
CPC分类号： G11C17/18
摘要： A fuse sense circuit has a sense amplifier and a post amplifier (gain stage). The sense amplifier has a reference branch and one or more sense (or fuse) branches. The fuse sense circuit determines the state of the fuses using safe currents and provides much higher gain than prior art. The post amplifier is a scaled replica of the reference branch or one of the sense branches in that the devices in the post amplifier maintain the same ratio as similar devices in the reference branch, and components in the post amplifier each matches components in the reference branch. The sense amplifier output is interpreted by the post amplifier's matched gain stage and has a trip point that sufficiently tracks the reference voltage. The result is reduced process and voltage sensitivity, which allows lower differential fuse resistance to be accurately detected with a non-ideal sense amplifier. Multiple gain stages may be added to multiple sense branches for redundancy and single-ended sensing.
摘要翻译：熔丝检测电路具有读出放大器和后置放大器（增益级）。读出放大器具有参考分支和一个或多个感测（或熔丝）分支。熔丝检测电路使用安全电流确定熔丝的状态，并提供比现有技术高得多的增益。后置放大器是参考支路或感测支路之一的经缩放的副本，因为后置放大器中的器件与参考支路中的类似器件保持相同的比率，后置放大器中的元件均与参考支路中的元件匹配。读出放大器输出由后置放大器的匹配增益级解释，并具有足够跟踪参考电压的跳变点。结果是降低了工艺和电压灵敏度，这允许使用非理想读出放大器精确检测较低的差分保险丝电阻。多个增益级可以被添加到多个检测分支用于冗余和单端感测。

9. 发明申请

US20050195000A1 Power-on detect circuit for use with multiple voltage domains 有权
标题翻译：上电检测电路用于多个电压域
公开(公告)号：US20050195000A1
公开(公告)日：2005-09-08
申请号：US10794497
申请日：2004-03-05
申请人： Rachael Parker , Mark Neidengard , Patrick Ott , Gregory Taylor
发明人： Rachael Parker , Mark Neidengard , Patrick Ott , Gregory Taylor
IPC分类号： H03L7/00
CPC分类号： H03K17/223
摘要： Embodiments of the present invention include a circuit, a method, and a system for power-on detect circuitry for use with multiple voltage domains.
摘要翻译：本发明的实施例包括用于与多个电压域一起使用的上电检测电路的电路，方法和系统。

10. 发明公开

US20230163761A1 HOT CARRIER INJECTION HARDENED PHYSICALLY UNCLONABLE FUNCTION CIRCUIT 审中-公开
公开(公告)号：US20230163761A1
公开(公告)日：2023-05-25
申请号：US17990575
申请日：2022-11-18
申请人： Rachael Parker , Jyothi Bhaskarr Velamala
发明人： Rachael Parker , Jyothi Bhaskarr Velamala
IPC分类号： H03K17/687 , H03K19/20
CPC分类号： H03K17/6872 , H03K19/20 , G11C11/412
摘要： Various embodiments provide apparatuses, systems, and methods for a hot carrier injection (HCI) physically unclonable function (PUF) circuit. For example, described herein is a HCI PUF circuit with n-type metal oxide semiconductor (NMOS) transistors and a Pi-shaped reset structure. Other embodiments may be described and claimed.

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