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1. 发明申请

US20050242852A1 Methods and apparatuses for detecting clock loss in a phase-locked loop 失效
标题翻译：在锁相环中检测时钟损耗的方法和装置
公开(公告)号：US20050242852A1
公开(公告)日：2005-11-03
申请号：US10836645
申请日：2004-04-30
申请人： Rachael Parker , Hon-Mo Law , Timothy Low
发明人： Rachael Parker , Hon-Mo Law , Timothy Low
IPC分类号： H03L7/00 , H03L7/08 , H03L7/089
CPC分类号： H03L7/08 , H03L7/0891
摘要： Embodiments of the present invention describe methods and apparatuses for detecting signal loss in circuits such as a phase-locked loop (PLL). In one embodiment a PLL is equipped with detection logic to detect loss of a reference clock provided to the PLL and a feedback clock generated by the PLL.
摘要翻译：本发明的实施例描述了用于检测诸如锁相环（PLL）的电路中的信号丢失的方法和装置。在一个实施例中，PLL配备有检测逻辑以检测提供给PLL的参考时钟的损耗和由PLL产生的反馈时钟。

2. 发明申请

US20070164797A1 Method and apparatus to eliminate clock phase error in a multi-phase clock circuit 审中-公开
标题翻译：消除多相时钟电路中的时钟相位误差的方法和装置
公开(公告)号：US20070164797A1
公开(公告)日：2007-07-19
申请号：US11314038
申请日：2005-12-20
申请人： Hon-Mo Law , Ying Zhou
发明人： Hon-Mo Law , Ying Zhou
IPC分类号： H03L7/06
CPC分类号： H03L7/07 , H03L7/0812 , H03L7/0814
摘要： A multi-phase clock circuit may include a delay line with an input terminal for receiving a periodic signal, a phase detector for detecting a phase difference between the periodic signal and a delay-line output signal generated in response to the periodic signal, and a bias control circuit for adjusting at least one bias voltage applied to the delay line in response to a signal related to the detected phase difference. A method for generating a multi-phase clock is also provided. This method includes applying a reference clock signal to a delay line, comparing the phase of a delay line output signal generated in response to the reference clock with the reference clock, and adjusting at least one bias voltage of the delay line in response to the phase comparison of the two signals.
摘要翻译：多相时钟电路可以包括具有用于接收周期信号的输入端的延迟线，用于检测周期信号与响应周期信号产生的延迟线输出信号之间的相位差的相位检测器，以及偏置控制电路，用于响应于与检测到的相位差相关的信号，调整施加到延迟线的至少一个偏置电压。还提供了一种用于产生多相时钟的方法。该方法包括将参考时钟信号施加到延迟线，将响应于参考时钟产生的延迟线输出信号的相位与参考时钟进行比较，以及响应于相位调整延迟线的至少一个偏置电压比较两个信号。

3. 发明申请

US20070149142A1 Clock deskewing method, apparatus, and system 有权
标题翻译：时钟歪斜方式，装置和系统
公开(公告)号：US20070149142A1
公开(公告)日：2007-06-28
申请号：US11318118
申请日：2005-12-23
申请人： Hon-Mo Law , Mamun Rashid , Aaron Martin
发明人： Hon-Mo Law , Mamun Rashid , Aaron Martin
IPC分类号： H04B1/40 , H04B7/00 , H04B1/06
CPC分类号： G11C7/22 , G11C7/02 , G11C7/1051 , G11C7/1066 , G11C7/222 , H03L7/0805 , H03L7/081
摘要： An integrated circuit includes clock deskew circuitry. The deskew circuitry includes a loop circuit to align an input clock signal with an output clock signal, and also aligns transmitted data with the output clock signal.
摘要翻译：集成电路包括时钟偏移电路。该偏斜电路包括一个环路电路，用于将输入时钟信号与输出时钟信号对准，并且还将所发送的数据与输出时钟信号对准。

4. 发明申请

US20070146035A1 Receive clock deskewing method, apparatus, and system 有权
标题翻译：接收时钟去歪斜方法，仪器和系统
公开(公告)号：US20070146035A1
公开(公告)日：2007-06-28
申请号：US11319689
申请日：2005-12-28
申请人： Hon-Mo Law , Mamun Rashid , Aaron Martin
发明人： Hon-Mo Law , Mamun Rashid , Aaron Martin
IPC分类号： H03K5/13
CPC分类号： H04L7/033 , H03L7/07 , H03L7/0814 , H04L7/0337
摘要： An integrated circuit includes clock deskew circuitry. The deskew circuitry includes multiple loop circuits to align a received clock with a data eye, and to reduce the effects of clock drift caused by voltage and temperature variations.
摘要翻译：集成电路包括时钟偏移电路。该偏斜电路包括多个回路电路，以使接收的时钟与数据眼对齐，并且减少由电压和温度变化引起的时钟漂移的影响。

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