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1. 发明申请

US20060221984A1 Modular interconnect structure 有权
标题翻译：模块化互连结构
公开(公告)号：US20060221984A1
公开(公告)日：2006-10-05
申请号：US11095241
申请日：2005-03-31
申请人： Martin Denham
发明人： Martin Denham
IPC分类号： H04L12/28
CPC分类号： H04L49/15 , H04L49/101 , H04L49/30
摘要： Some embodiments of the invention include an interconnect structure to transfer data among a plurality of devices. The interconnect structure includes a crossbar and a number of interconnect branches coupled to the crossbar. Each of the interconnect branches includes a number of connector circuits coupled in series to transfer data in a group of devices of the plurality of devices. The crossbar includes a number of connector circuits coupled in series to allow one group of devices from one interconnect branch to exchange data with another group of devices from another interconnect branch. Other embodiments are described and claimed.
摘要翻译：本发明的一些实施例包括用于在多个设备之间传送数据的互连结构。互连结构包括交叉开关和耦合到横杆的多个互连分支。每个互连分支包括串联耦合的多个连接器电路以在多个器件的一组器件中传送数据。横杆包括串联耦合的许多连接器电路，以允许来自一个互连分支的一组设备从另一互连分支与另一组设备交换数据。描述和要求保护其他实施例。

2. 发明申请

US20050212584A1 Fuse sense circuit 有权
公开(公告)号：US20050212584A1
公开(公告)日：2005-09-29
申请号：US11127365
申请日：2005-05-11
申请人： Rachael Parker , Martin Denham
发明人： Rachael Parker , Martin Denham
IPC分类号： G01R19/00 , G11C17/18 , H03F3/45
CPC分类号： G11C17/18
摘要： A fuse sense circuit has a sense amplifier and a post amplifier (gain stage). The sense amplifier has a reference branch and one or more sense (or fuse) branches. The fuse sense circuit determines the state of the fuses using safe currents and provides much higher gain than prior art. The post amplifier is a scaled replica of the reference branch or one of the sense branches in that the devices in the post amplifier maintain the same ratio as similar devices in the reference branch, and components in the post amplifier each matches components in the reference branch. The sense amplifier output is interpreted by the post amplifier's matched gain stage and has a trip point that sufficiently tracks the reference voltage. The result is reduced process and voltage sensitivity, which allows lower differential fuse resistance to be accurately detected with a non-ideal sense amplifier. Multiple gain stages may be added to multiple sense branches for redundancy and single-ended sensing.

3. 发明申请

US20050200386A1 Fuse sense circuit 有权
公开(公告)号：US20050200386A1
公开(公告)日：2005-09-15
申请号：US11127750
申请日：2005-05-11
申请人： Rachael Parker , Martin Denham
发明人： Rachael Parker , Martin Denham
IPC分类号： G01R19/00 , G11C17/18 , H03F3/45
CPC分类号： G11C17/18
摘要： A fuse sense circuit has a sense amplifier and a post amplifier (gain stage). The sense amplifier has a reference branch and one or more sense (or fuse) branches. The fuse sense circuit determines the state of the fuses using safe currents and provides much higher gain than prior art. The post amplifier is a scaled replica of the reference branch or one of the sense branches in that the devices in the post amplifier maintain the same ratio as similar devices in the reference branch, and components in the post amplifier each matches components in the reference branch. The sense amplifier output is interpreted by the post amplifier's matched gain stage and has a trip point that sufficiently tracks the reference voltage. The result is reduced process and voltage sensitivity, which allows lower differential fuse resistance to be accurately detected with a non-ideal sense amplifier. Multiple gain stages may be added to multiple sense branches for redundancy and single-ended sensing.

4. 发明申请

US20060224912A1 Clock distribution for interconnect structures 有权
标题翻译：互连结构的时钟分布
公开(公告)号：US20060224912A1
公开(公告)日：2006-10-05
申请号：US11095289
申请日：2005-03-31
申请人： Martin Denham
发明人： Martin Denham
IPC分类号： G06F5/06
CPC分类号： G06F7/00 , G06F1/10
摘要： Some embodiments of the invention include an interconnect structure having a plurality of connector circuits to transfer messages among a number of devices. Each of the connector circuits includes a data transfer unit to transfer messages and a clock unit to provide timing to transfer the messages. The interconnect structure propagates a master clock signal serially through the clock units of the connector circuits to generate a number of different input clock signals. The timing provided by each of the clock units is based on the timing of one of the input clock signals. Other embodiments are described and claimed.
摘要翻译：本发明的一些实施例包括具有多个连接器电路以在多个装置之间传送消息的互连结构。每个连接器电路包括用于传送消息的数据传送单元和时钟单元，以提供传送消息的定时。互连结构通过连接器电路的时钟单元串行地传播主时钟信号，以产生多个不同的输入时钟信号。每个时钟单元提供的定时是基于输入时钟信号之一的定时。描述和要求保护其他实施例。

5. 发明申请

US20050200385A1 Fuse sense circuit 有权
标题翻译：保险丝检测电路
公开(公告)号：US20050200385A1
公开(公告)日：2005-09-15
申请号：US11127501
申请日：2005-05-11
申请人： Rachael Parker , Martin Denham
发明人： Rachael Parker , Martin Denham
IPC分类号： G01R19/00 , G11C17/18 , H03F3/45
CPC分类号： G11C17/18
摘要： A fuse sense circuit has a sense amplifier and a post amplifier (gain stage). The sense amplifier has a reference branch and one or more sense (or fuse) branches. The fuse sense circuit determines the state of the fuses using safe currents and provides much higher gain than prior art. The post amplifier is a scaled replica of the reference branch or one of the sense branches in that the devices in the post amplifier maintain the same ratio as similar devices in the reference branch, and components in the post amplifier each matches components in the reference branch. The sense amplifier output is interpreted by the post amplifier's matched gain stage and has a trip point that sufficiently tracks the reference voltage. The result is reduced process and voltage sensitivity, which allows lower differential fuse resistance to be accurately detected with a non-ideal sense amplifier. Multiple gain stages may be added to multiple sense branches for redundancy and single-ended sensing.
摘要翻译：熔丝检测电路具有读出放大器和后置放大器（增益级）。读出放大器具有参考分支和一个或多个感测（或熔丝）分支。熔丝检测电路使用安全电流确定熔丝的状态，并提供比现有技术高得多的增益。后置放大器是参考支路或感测支路之一的经缩放的副本，因为后置放大器中的器件与参考支路中的类似器件保持相同的比率，后置放大器中的元件均与参考支路中的元件匹配。读出放大器输出由后置放大器的匹配增益级解释，并具有足够跟踪参考电压的跳变点。结果是降低了工艺和电压灵敏度，这允许使用非理想读出放大器精确检测较低的差分保险丝电阻。多个增益级可以被添加到多个检测分支用于冗余和单端感测。

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