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1. 发明申请

US20030022450A1 Method to form elevated source/drain using poly spacer 失效
标题翻译：使用聚间隔物形成升高的源极/漏极的方法
公开(公告)号：US20030022450A1
公开(公告)日：2003-01-30
申请号：US09912607
申请日：2001-07-25
申请人： Chartered Semiconductor manufacturing Ltd.
发明人： Yang Pan , James Lee Yong Meng , Leung Ying Keung , Yelehanka Ramachandramurthy Predeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundarensan
IPC分类号： H01L021/336 , H01L021/3205
CPC分类号： H01L29/6659 , H01L21/2257 , H01L29/41775 , H01L29/41783 , H01L29/665 , H01L29/6656
摘要： A method for forming a sub-quarter micron MOSFET having an elevated source/drain structure is described. A gate electrode is formed over a gate dielectric on a semiconductor substrate. Ions are implanted into the semiconductor substrate to form lightly doped regions using the gate electrode as a mask. Thereafter, dielectric spacers are formed on sidewalls of the gate electrode. A polysilicon layer is deposited overlying the semiconductor substrate, gate electrode, and dielectric spacers wherein the polysilicon layer is heavily doped. The polysilicon layer is etched back to leave polysilicon spacers on the dielectric spacers. Dopant is diffused from the polysilicon spacers into the semiconductor substrate to form source and drain regions underlying the polysilicon spacers. The polysilicon spacer on an end of the gate electrode is removed to separate the polysilicon spacers into a source polysilicon spacer and a drain polysilicon spacer thereby completing formation of a MOSFET having an elevated source/drain structure in the fabrication of an integrated circuit device.
摘要翻译：描述了一种形成具有升高的源极/漏极结构的二分之一微米MOSFET的方法。在半导体衬底上的栅极电介质上形成栅电极。使用栅电极作为掩模将离子注入到半导体衬底中以形成轻掺杂区域。此后，在栅电极的侧壁上形成电介质间隔物。沉积覆盖半导体衬底，栅电极和电介质间隔物的多晶硅层，其中多晶硅层被重掺杂。蚀刻多晶硅层以在电介质间隔物上留下多晶硅间隔物。掺杂剂从多晶硅间隔物扩散到半导体衬底中以在多晶硅间隔物下面形成源极和漏极区域。去除栅电极端部上的多晶硅间隔物以将多晶硅间隔物分离成源多晶硅间隔物和漏极多晶硅间隔物，从而在集成电路器件的制造中完成形成具有升高的源极/漏极结构的MOSFET。

2. 发明申请

US20030017710A1 Method to improve latchup by forming selective sloped staircase STI structure to use in the I/0 or latchup sensitive area 审中-公开
标题翻译：通过形成用于I / O或闭锁敏感区域的选择性倾斜楼梯STI结构来提高闩锁的方法
公开(公告)号：US20030017710A1
公开(公告)日：2003-01-23
申请号：US09907649
申请日：2001-07-19
申请人： Chartered Semiconductor Manufacturing Ltd.
发明人： Pan Yang , James Lee Yong Meng , Leung Ying Keung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan
IPC分类号： C23F001/00 , C03C015/00 , H01L021/461
CPC分类号： H01L21/823878 , H01L21/76232 , H01L27/0921
摘要： A method of forming a sloped staircase STI structure, comprising the following steps. a) A substrate having an upper surface is provided. b) A patterned masking layer is formed over the substrate to define an STI region. The patterned masking layer having exposed sidewalls. c) The substrate is etched a first time through the masking layer to form a first step trench within the STI region. The first step trench having exposed sidewalls. d) Continuous side wall spacers are formed on the exposed patterned masking layer and first step trench sidewalls. e) The substrate is etched a second time using the masking layer and the continuous sidewall spacers as masks to form a second step trench within the STI region. The second step trench having exposed sidewalls. f) Second side wall spacers are formed on the second step trench sidewalls. g) Steps e) and f) are repeated x more times to create xnull2 total step trenches and xnull2 total side wall spacers on xnull2 total step trench sidewalls. h) A planarized STI is formed within the STI region substantially level with the substrate upper surface and over the xnull2 total step trenches.
摘要翻译：一种形成倾斜楼梯STI结构的方法，包括以下步骤。 a）提供具有上表面的基板。 b）在衬底上形成图案化掩模层以限定STI区域。图案化掩模层具有暴露的侧壁。 c）首先通过掩模层蚀刻衬底，以在STI区域内形成第一阶跃沟槽。第一级沟槽具有暴露的侧壁。 d）连续的侧壁间隔物形成在暴露的图案化掩模层和第一阶梯沟侧壁上。 e）使用掩模层和连续的侧壁间隔物作为掩模第二次蚀刻基板，以在STI区域内形成第二阶跃沟槽。第二级沟槽具有暴露的侧壁。 f）第二侧壁间隔物形成在第二台阶沟槽侧壁上。 g）步骤e）和f）重复x次以在x + 2个总阶梯形沟槽侧壁上产生x + 2个总台阶沟槽和x + 2个总侧壁间隔物。 h）在STI区域内形成平坦化STI，其基本上与衬底上表面平齐，并且在x + 2个总步进沟槽上。

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