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1. 发明申请

US20020048950A1 Application of vapor phase HFACAC-based compound for use in copper decontamination and cleaning processes 审中-公开
标题翻译：应用气相HFACAC基化合物用于铜去污和清洗过程
公开(公告)号：US20020048950A1
公开(公告)日：2002-04-25
申请号：US09882677
申请日：2001-06-18
申请人： CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
发明人： Yakub Aliyu , Simon Chooi , Mei Sheng Zhou , John Leonard Sudijono , Subhash Gupta , Sudipto Ranendra Roy , Paul Kwok Keung Ho , Yi Xu
IPC分类号： H01L021/44
CPC分类号： H01L21/02046 , C23F1/12 , H01L21/02079 , Y10S438/906
摘要： An effective copper decontamination method in the fabrication of integrated circuits is achieved. An organic-based HFACAC decontamination compound in vapor phase is sprayed over elemental copper found on equipment or tools or as a spill wherein the compound reacts with all of the elemental copper and forms a volatile compound that can be flushed away thereby completing copper decontamination.
摘要翻译：实现了集成电路制造中有效的铜去污方法。蒸气相中的基于有机的HFACAC去污化合物喷洒在设备或工具上发现的元素铜上，或作为溢出物喷洒，其中化合物与所有元素铜反应并形成可被冲洗掉的挥发性化合物，从而完成铜去污。

2. 发明申请

US20010012687A1 Gap filling process in integrated circuits using low dielectric constant materials 审中-公开
标题翻译：使用低介电常数材料的集成电路中的间隙填充过程
公开(公告)号：US20010012687A1
公开(公告)日：2001-08-09
申请号：US09817473
申请日：2001-03-26
申请人： CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
发明人： Yi Xu , Jia Zhen Zheng , Jane C.M. Hui , Charles Lin , Yih Shung Lin
IPC分类号： H01L021/4763
CPC分类号： H01L21/0217 , H01L21/02118 , H01L21/02126 , H01L21/0214 , H01L21/02164 , H01L21/02167 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/02282 , H01L21/02337 , H01L21/0332 , H01L21/31053 , H01L21/31058 , H01L21/31144 , H01L21/312 , H01L21/3185 , H01L21/32139 , H01L21/76819 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76837
摘要： It is the general object of the present invention to provide an improved method of fabricating semiconductor integrated circuit devices, specifically by describing an improved process of fabricating multilevel metal structures using low dielectric constant materials. The present invention relates to an improved processing method for stable and planar intermetal dielectrics, with low dielectric constants. The first embodiment uses a stabilizing adhesion layer between the bottom, low dielectric constant layer and the top dielectric layer. The advantages are: (i) improved adhesion and stability of the low dielectric layer and the top dielectric oxide (ii) over all layer thickness of the dielectric layers can be reduced, hence lowering the parasitic capacitance of these layers. In the second embodiment, the method uses a multi-layered nullhard masknull on metal interconnect lines with a silicon oxynitride DARC, dielectric anti-reflective coating on top of metal. A double coating scheme of low dielectric constant insulators are used in this application. The third embodiment uses a hard mask stack over the interconnect metal lines, with a silicon oxynitride DARC coating on top of metal, and an adhesion layer between the low dielectric material and the top dielectric layer.
摘要翻译：本发明的总体目的是提供一种制造半导体集成电路器件的改进方法，特别是通过描述使用低介电常数材料制造多层金属结构的改进方法。本发明涉及一种具有低介电常数的稳定和平坦的金属间电介质的改进的处理方法。第一实施例使用底部，低介电常数层和顶部介电层之间的稳定粘合层。优点是：（i）可以降低介电层的所有层厚度上的低介电层和顶部电介质氧化物（ii）的粘附性和稳定性，因此降低这些层的寄生电容。在第二实施例中，该方法在具有氮氧化硅DARC的金属互连线上使用多层“硬掩模”，金属顶部具有介电抗反射涂层。本申请中使用低介电常数绝缘体的双重涂层方案。第三实施例在互连金属线上使用硬掩模叠层，在金属顶部具有氮氧化硅DARC涂层，以及在低介电材料和顶部电介质层之间的粘合层。

3. 发明申请

US20030003745A1 New method for improving oxide erosion of tungsten CMP operations 有权
标题翻译：改善钨CMP操作的氧化物侵蚀的新方法
公开(公告)号：US20030003745A1
公开(公告)日：2003-01-02
申请号：US09893080
申请日：2001-06-28
申请人： Chartered Semiconductor Manufacturing Ltd.
发明人： Xian Bin Wang , Yi Xu , Subramanian Balakumar , Cuiyang Wang
IPC分类号： H01L021/302 , H01L021/461
CPC分类号： H01L21/7684 , H01L21/3212
摘要： A new method to prevent oxide erosion in a metal plug process by employing a silicon nitride layer over the oxide is described. An oxide layer is deposited overlying a semiconductor substrate. A silicon nitride layer is deposited overlying the oxide layer. An opening is etched through the silicon nitride layer and into the oxide layer. A barrier metal layer is deposited overlying the silicon nitride layer and into the opening. A metal layer is deposited overlying the barrier metal layer. The metal layer and barrier metal layer are polished away using chemical mechanical polishing (CMP) with a polish stop at the silicon nitride layer. The metal layer forms a metal plug. The silicon nitride layer prevents erosion of the oxide layer during the polishing step to complete formation of a metal plug in the fabrication of an integrated circuit device.
摘要翻译：描述了通过在氧化物上使用氮化硅层来防止金属塞过程中的氧化物侵蚀的新方法。沉积在半导体衬底上的氧化物层。沉积氮化硅层覆盖氧化物层。通过氮化硅层蚀刻开口并进入氧化物层。在氮化硅层上沉积阻挡金属层并进入开口。沉积在阻挡金属层上的金属层。使用化学机械抛光（CMP）在氮化硅层上抛光停止来抛光金属层和阻挡金属层。金属层形成金属塞。氮化硅层在抛光步骤期间防止氧化物层的侵蚀，以在集成电路器件的制造中完成金属插塞的形成。

4. 发明申请

US20030192943A1 Method of using hydrogen plasma to pre-clean copper surfaces during Cu/Cu or Cu/metal bonding 有权
标题翻译：在Cu / Cu或Cu /金属接合期间使用氢等离子体预清洁铜表面的方法
公开(公告)号：US20030192943A1
公开(公告)日：2003-10-16
申请号：US10120836
申请日：2002-04-11
申请人： Chartered Semiconductor Manufacturing Ltd.
发明人： John Leonard Sudijono , Yakub Aliyu , Mei Sheng Zhou , Simon Chooi , Subhash Gupta , Sudipto Ranendra Roy , Paul Kwok Keung Ho , Yi Xu
IPC分类号： B23K031/00 , B23K031/02 , H01L021/44
CPC分类号： H01L24/05 , C23G5/00 , H01L21/02046 , H01L21/32136 , H01L23/4824 , H01L24/03 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/85 , H01L2224/04042 , H01L2224/05001 , H01L2224/05073 , H01L2224/05118 , H01L2224/05124 , H01L2224/05155 , H01L2224/05166 , H01L2224/05556 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/4813 , H01L2224/4846 , H01L2224/48463 , H01L2224/4847 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2224/48824 , H01L2224/48844 , H01L2224/48847 , H01L2224/49111 , H01L2224/85013 , H01L2224/85201 , H01L2224/85203 , H01L2224/85205 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/05042 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/19042 , H01L2924/19043 , H01L2924/00014 , H01L2924/00 , H01L2224/48744 , H01L2924/00015
摘要： A method of bonding a wire to a metal bonding pad, comprising the following steps. A semiconductor die structure having an exposed metal bonding pad within a chamber is provided. The bonding pad has an upper surface. A hydrogen-plasma is produced within the chamber from a plasma source. The metal bonding pad is pre-cleaned and passivated with the hydrogen-plasma to remove any metal oxide formed on the metal bonding pad upper surface. A wire is then bonded to the passivated metal bonding pad.
摘要翻译：一种将金属丝焊接到金属焊盘上的方法，包括以下步骤。提供一种在室内具有暴露的金属接合焊盘的半导体管芯结构。接合垫具有上表面。在等离子体源室内产生氢等离子体。用氢 - 等离子体对金属接合垫进行预清洁和钝化以去除在金属焊盘上表面上形成的任何金属氧化物。然后将线接合到钝化金属接合焊盘。

5. 发明申请

US20020100794A1 Method of application of conductive cap-layer in flip-chip, cob, and micro metal bonding 有权
标题翻译：导电盖层在倒装芯片，芯棒和微金属接合中的应用方法
公开(公告)号：US20020100794A1
公开(公告)日：2002-08-01
申请号：US10099283
申请日：2002-03-15
申请人： CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
发明人： Kwok Keung Paul Ho , Simon Chooi , Yi Xu , Yakub Aliyu , Mei Sheng Zhou , John Leonard Sudijono , Subhash Gupta , Sudipto Ranendra Roy
IPC分类号： B23K031/02
CPC分类号： H01L24/85 , B23K20/007 , H01L24/03 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05073 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05184 , H01L2224/05187 , H01L2224/05624 , H01L2224/05647 , H01L2224/45124 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2224/85 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/04953 , H01L2224/78 , H01L2924/00
摘要： A method of bonding a bonding element to a metal bonding pad comprises the following steps. A semiconductor structure having an exposed, recessed metal bonding pad within a layer opening is provided. The layer has an upper surface. A conductive cap having a predetermined thickness is formed over the metal bonding pad. A bonding element is bonded to the conductive cap to form an electrical connection with the metal bonding pad.
摘要翻译：将接合元件接合到金属接合焊盘的方法包括以下步骤。提供了一种在层开口内具有暴露的凹陷金属接合焊盘的半导体结构。该层具有上表面。在金属焊盘上形成具有预定厚度的导电盖。接合元件结合到导电盖以与金属接合焊盘形成电连接。

6. 发明申请

US20020076918A1 Use of boron carbide as an etch-stop and barrier layer for copper dual damascene metallization 有权
公开(公告)号：US20020076918A1
公开(公告)日：2002-06-20
申请号：US10050697
申请日：2002-01-18
申请人： CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
发明人： Licheng M. Han , Yi Xu , Joseph Zhiefeng Xie , Mei Sheng Zhou , Simon Chooi
IPC分类号： H01L021/4763
CPC分类号： H01L21/76834 , H01L21/76807 , H01L21/76829 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a boron carbide layer for use as a barrier and an etch-stop layer in a copper dual damascene structure, and the structure itself are disclosed. In addition to providing a good barrier to copper diffusion, good insulating properties, high etch selectivity with respect to dielectric insulators, boron carbide also provides good electrical characteristics because of its low dielectric constant of less than 5. The amorphous boron carbide is formed in a PECVD chamber by introducing a boron source gas such as B2H6, B5H9null, and carbon source gas such as CH4 and C2H6 at a deposition temperature of about 400null C. Any one, or any combination of the passivation, etch-stop, cap layers of the damascene structure can comprise boron carbide.

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