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1. 发明授权

US06650191B2 Low jitter ring oscillator architecture 有权
标题翻译：低抖动环形振荡器架构
公开(公告)号：US06650191B2
公开(公告)日：2003-11-18
申请号：US10213859
申请日：2002-08-07
申请人： Charles M. Branch , Lieyi Fang , Daramana Gata , James R. Hochschild
发明人： Charles M. Branch , Lieyi Fang , Daramana Gata , James R. Hochschild
IPC分类号： H03B100
CPC分类号： H03K3/0322 , H03K3/012
摘要： A low power and low jitter CMOS ring oscillator having a novel architecture that includes fully symmetrical differential current steering delay cells. This novel ring oscillator includes a first capacitor coupled between the first power supply rail and a bias voltage input. At least one stage couples across the first capacitor. Each stage includes a first transistor, a second capacitor, and a fully symmetrical differential delay cell. In an embodiment, the first transistor may be a PMOS transistor, where the drain of the first PMOS transistor connects to the first power supply rail and the gate of the first PMOS transistor couple to the bias voltage input. The second capacitor couples between the source of the first transistor and ground and acts as a low pass filter. As a result, the second capacitor minimizes the effects of the thermal and flicker noise of the devices which provide the tail current. The fully symmetrical differential delay cell includes a control input, a differential input and a differential output. The control input couples to the source of the first PMOS transistor. When one stage is present, the differential input couples to the differential output. When more than one stage is present, the differential outputs couple to the differential inputs of the concurrent delay cell. In addition, the delay cell in the last stage couples to the differential input of the delay cell in the first stage.
摘要翻译：具有新颖架构的低功率和低抖动CMOS环形振荡器，其包括完全对称的差动电流转向延迟单元。该新颖的环形振荡器包括耦合在第一电源轨和偏置电压输入之间的第一电容器。至少一级耦合在第一个电容上。每个级包括第一晶体管，第二电容器和完全对称的差分延迟单元。在一个实施例中，第一晶体管可以是PMOS晶体管，其中第一PMOS晶体管的漏极连接到第一电源轨，并且第一PMOS晶体管的栅极耦合到偏置电压输入。第二电容器耦合在第一晶体管的源极和地之间并用作低通滤波器。结果，第二电容器最小化提供尾电流的器件的热和闪烁噪声的影响。完全对称的差分延迟单元包括控制输入，差分输入和差分输出。控制输入耦合到第一PMOS晶体管的源极。当存在一个级时，差分输入耦合到差分输出。当存在多个级时，差分输出耦合到并行延迟单元的差分输入。此外，最后级中的延迟单元耦合到第一级中的延迟单元的差分输入。

2. 发明授权

US5355036A Timed make-before-break circuit for analog switch control 失效
标题翻译：用于模拟开关控制的定时断开电路
公开(公告)号：US5355036A
公开(公告)日：1994-10-11
申请号：US975025
申请日：1992-11-12
申请人： Daramana Gata
发明人： Daramana Gata
IPC分类号： H03K17/00 , H03K17/16
CPC分类号： H03K17/16 , H03K17/002
摘要： A timed make-before-break circuit for analog switch control is provided. The invention contains one or more delay circuit and more than one logic gate. Each logic gate has one logic gate input line connected to a delay circuit input line and another logic gate input line connected to a delay circuit output line. The logic gate input lines are connected to the delay circuit input line and the delay circuit output line from the same delay circuit. The invention also has more than one switch. Each switch has an input control line connected to a logic gate output line.
摘要翻译：提供了一种用于模拟开关控制的定时断开电路。本发明包含一个或多个延迟电路和多于一个的逻辑门。每个逻辑门具有连接到延迟电路输入线的一个逻辑门输入线和连接到延迟电路输出线的另一个逻辑门输入线。逻辑门输入线连接到延迟电路输入线和来自相同延迟电路的延迟电路输出线。本发明还具有多个开关。每个开关具有连接到逻辑门输出线的输入控制线。

3. 发明授权

US5376892A Sigma delta saturation detector and soft resetting circuit 失效
标题翻译： Sigma delta饱和检测器和软复位电路
公开(公告)号：US5376892A
公开(公告)日：1994-12-27
申请号：US97418
申请日：1993-07-26
申请人： Daramana Gata
发明人： Daramana Gata
IPC分类号： H03M3/02
CPC分类号： H03M3/364 , H03M3/43
摘要： A circuit having a first integrator 46 and a sensor 20 for sensing a difference between an output voltage of the first integrator and a trip voltage provides a signal indicative of whether the output voltage is greater than the trip voltage. Resetting circuitry 40, 42 and 44 is coupled to the sensor 20 for softly bringing the output voltage lower than the trip voltage when the signal from the sensor 20 indicates that the output voltage is greater than the trip voltage.
摘要翻译：具有用于感测第一积分器的输出电压和跳闸电压之间的差的第一积分器46和传感器20的电路提供指示输出电压是否大于跳闸电压的信号。当来自传感器20的信号指示输出电压大于跳闸电压时，复位电路40,42和44耦合到传感器20，用于将输出电压轻微地低于跳闸电压。

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