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1. 发明申请

US20050118802A1 Method for implementing poly pre-doping in deep sub-micron process 审中-公开
标题翻译：在深亚微米工艺中实施多种预掺杂的方法
公开(公告)号：US20050118802A1
公开(公告)日：2005-06-02
申请号：US10991839
申请日：2004-11-18
申请人： Chang-Sheng Tsao , Yi-Hang Chen , Jung-Hui Kao , Yen-Ming Chen , Pu-Fang Chen , Lin-June Wu
发明人： Chang-Sheng Tsao , Yi-Hang Chen , Jung-Hui Kao , Yen-Ming Chen , Pu-Fang Chen , Lin-June Wu
IPC分类号： H01L21/265 , H01L21/28 , H01L21/324 , H01L21/331 , H01L29/78
CPC分类号： H01L21/28035 , H01L21/265 , H01L21/324 , H01L29/78
摘要： Method for reducing dopant contamination during the fabrication of semiconductor devices is provided. The method includes doping a first layer, such as a polysilicon layer. During a subsequent annealing process, a gas, such as nitrogen, oxygen, a combination thereof, or the like, is introduced. The gas causes a cap layer to be formed over the first layer, preventing or reducing out-diffusing of the dopants and contamination of the process chamber. In a preferred embodiment, the gas is introduced during the ramp-up stage of the annealing process. The cap layer may be removed prior to etching the first layer.
摘要翻译：提供了在制造半导体器件期间减少掺杂剂污染的方法。该方法包括掺杂第一层，例如多晶硅层。在随后的退火过程中，引入气体，例如氮气，氧气，其组合等。气体导致在第一层上形成覆盖层，防止或减少掺杂物的扩散和处理室的污染。在优选实施例中，在退火过程的加速阶段期间引入气体。在蚀刻第一层之前可以去除覆盖层。

2. 发明申请

US20130337631A1 Semiconductor Structure and Method 有权
标题翻译：半导体结构与方法
公开(公告)号：US20130337631A1
公开(公告)日：2013-12-19
申请号：US13525041
申请日：2012-06-15
申请人： Sen-Hong Syue , Pu-Fang Chen , Shiang-Bau Wang
发明人： Sen-Hong Syue , Pu-Fang Chen , Shiang-Bau Wang
IPC分类号： H01L21/762 , C30B15/04
CPC分类号： C30B15/04 , C30B15/00 , C30B15/203 , C30B15/206 , C30B15/22 , C30B29/06 , C30B31/02 , C30B31/04 , C30B31/165 , C30B33/00 , H01L21/0201 , H01L21/31053 , H01L21/311 , H01L21/3225 , H01L21/76224 , H01L29/365 , H01L29/78
摘要： A system and method for providing support to semiconductor wafer is provided. An embodiment comprises introducing a vacancy enhancing material during the formation of a semiconductor ingot prior to the semiconductor wafer being separated from the semiconductor ingot. The vacancy enhancing material forms vacancies at a high density within the semiconductor ingot, and the vacancies form bulk micro defects within the semiconductor wafer during high temperature processes such as annealing. These bulk micro defects help to provide support and strengthen the semiconductor wafer during subsequent processing and helps to reduce or eliminate a fingerprint overlay that may otherwise occur.
摘要翻译：提供了一种用于向半导体晶片提供支撑的系统和方法。一个实施例包括在半导体晶片与半导体晶锭分离之前，在形成半导体晶锭期间引入空位增强材料。空位增强材料在半导体晶锭内以高密度形成空位，并且在诸如退火的高温过程中，空位形成半导体晶片内的体微小缺陷。这些大量微缺陷有助于在后续处理过程中提供支撑并加强半导体晶片，并有助于减少或消除否则会发生的指纹叠加。

3. 发明授权

US08008158B2 Dopant implantation method using multi-step implants 有权
标题翻译：使用多步植入物的掺杂剂植入法
公开(公告)号：US08008158B2
公开(公告)日：2011-08-30
申请号：US12170656
申请日：2008-07-10
申请人： Tse-En Chang , Chih-Fu Chang , Bone-Fong Wu , Chieh Chih Ting , Shao Hua Wang , Pu-Fang Chen , Yen Chuang
发明人： Tse-En Chang , Chih-Fu Chang , Bone-Fong Wu , Chieh Chih Ting , Shao Hua Wang , Pu-Fang Chen , Yen Chuang
IPC分类号： H01L21/336 , H01L21/8236
CPC分类号： H01L21/26513 , H01L29/1083 , H01L29/6659 , H01L29/7833
摘要： A method of forming a dopant implant region in a MOS transistor device having a dopant profile having a target dopant concentration includes implanting a first concentration of dopants into a region of a substrate, where the first concentration of dopants is less than the target dopant concentration, and without annealing the substrate after the implanting step, performing at least one second implanting step to implant at least one second concentration of dopants into the region of the substrate to bring the dopant concentration in the region to the target dopant concentration.
摘要翻译：在具有目标掺杂剂浓度的掺杂剂分布的MOS晶体管器件中形成掺杂剂注入区域的方法包括：将第一浓度的掺杂剂注入到衬底的区域中，其中掺杂剂的第一浓度小于目标掺杂剂浓度，并且在植入步骤之后不退火衬底，执行至少一个第二注入步骤以将至少一个第二浓度的掺杂剂注入到衬底的区域中，以使该区域中的掺杂剂浓度达到目标掺杂剂浓度。

4. 发明授权

US09945048B2 Semiconductor structure and method 有权
公开(公告)号：US09945048B2
公开(公告)日：2018-04-17
申请号：US13525041
申请日：2012-06-15
申请人： Sen-Hong Syue , Pu-Fang Chen , Shiang-Bau Wang
发明人： Sen-Hong Syue , Pu-Fang Chen , Shiang-Bau Wang
IPC分类号： C30B15/04 , H01L21/02 , C30B15/20 , C30B31/02 , C30B31/04 , H01L21/311 , C30B15/22 , H01L29/36 , H01L21/762 , C30B31/16 , H01L21/3105 , C30B29/06 , H01L21/322 , C30B15/00 , C30B33/00 , H01L29/78
CPC分类号： C30B15/04 , C30B15/00 , C30B15/203 , C30B15/206 , C30B15/22 , C30B29/06 , C30B31/02 , C30B31/04 , C30B31/165 , C30B33/00 , H01L21/0201 , H01L21/31053 , H01L21/311 , H01L21/3225 , H01L21/76224 , H01L29/365 , H01L29/78
摘要： A system and method for providing support to semiconductor wafer is provided. An embodiment comprises introducing a vacancy enhancing material during the formation of a semiconductor ingot prior to the semiconductor wafer being separated from the semiconductor ingot. The vacancy enhancing material forms vacancies at a high density within the semiconductor ingot, and the vacancies form bulk micro defects within the semiconductor wafer during high temperature processes such as annealing. These bulk micro defects help to provide support and strengthen the semiconductor wafer during subsequent processing and helps to reduce or eliminate a fingerprint overlay that may otherwise occur.

5. 发明申请

US20100009506A1 DOPANT IMPLANTATION METHOD AND INTEGRATED CIRCUITS FORMED THEREBY 有权
标题翻译： D ANT。。。。。。。。。。。。。。。。。。。
公开(公告)号：US20100009506A1
公开(公告)日：2010-01-14
申请号：US12170656
申请日：2008-07-10
申请人： Tse-En Chang , Chih-Fu Chang , Bone-Fong Wu , Chieh Chih Ting , Shao Hua Wang , Pu-Fang Chen , Yen Chuang
发明人： Tse-En Chang , Chih-Fu Chang , Bone-Fong Wu , Chieh Chih Ting , Shao Hua Wang , Pu-Fang Chen , Yen Chuang
IPC分类号： H01L21/8236
CPC分类号： H01L21/26513 , H01L29/1083 , H01L29/6659 , H01L29/7833
摘要： A method of forming a dopant implant region in a MOS transistor device having a dopant profile having a target dopant concentration includes implanting a first concentration of dopants into a region of a substrate, where the first concentration of dopants is less than the target dopant concentration, and without annealing the substrate after the implanting step, performing at least one second implanting step to implant at least one second concentration of dopants into the region of the substrate to bring the dopant concentration in the region to the target dopant concentration.
摘要翻译：在具有目标掺杂剂浓度的掺杂剂分布的MOS晶体管器件中形成掺杂剂注入区域的方法包括：将第一浓度的掺杂剂注入到衬底的区域中，其中掺杂剂的第一浓度小于目标掺杂剂浓度，并且在植入步骤之后不退火衬底，执行至少一个第二注入步骤以将至少一个第二浓度的掺杂剂注入到衬底的区域中，以使该区域中的掺杂剂浓度达到目标掺杂剂浓度。

6. 发明申请

US20080041758A1 Wafer carrier 审中-公开
标题翻译：晶圆载体
公开(公告)号：US20080041758A1
公开(公告)日：2008-02-21
申请号：US11504594
申请日：2006-08-16
申请人： Yen-Fei Lin , Hui-Wen Chou , Wen-Yu Ku , Pu-Fang Chen , Tung-Li Lee , Jih-Hwa Wang
发明人： Yen-Fei Lin , Hui-Wen Chou , Wen-Yu Ku , Pu-Fang Chen , Tung-Li Lee , Jih-Hwa Wang
IPC分类号： B65D85/00
CPC分类号： H01L21/67366 , H01L21/67393
摘要： A wafer carrier. The wafer carrier includes a container and a plate, wherein the container has an inner wall and the plate is disposed in the vicinity of the inner wall of an upper portion of the container.
摘要翻译：晶圆载体。晶片载体包括容器和板，其中所述容器具有内壁，并且所述板设置在所述容器的上部的内壁附近。

7. 发明授权

US07518129B2 Preventing dosage drift with duplicate dose integrators 有权
标题翻译：用重复剂量积分器预防剂量漂移
公开(公告)号：US07518129B2
公开(公告)日：2009-04-14
申请号：US11416874
申请日：2006-05-03
申请人： Jih-Hwa Wang , Otto Chen , Fang-Chi Chien , Tung-Li Lee , Pu-Fang Chen
发明人： Jih-Hwa Wang , Otto Chen , Fang-Chi Chien , Tung-Li Lee , Pu-Fang Chen
IPC分类号： G21K5/00
CPC分类号： H01J37/3171 , H01J37/304 , H01J2237/30433 , H01J2237/30455 , H01J2237/31703
摘要： A method for identifying a drifted dose integrator in an implantation system and an implantation system are provided. The implantation system includes a first dose integrator and a second dose integrator. The first dose integrator includes a first input configured to receive a first current generated from charges carried by implanted ions in a wafer, and a first output configured to output a first accumulated dosage value. The second dose integrator includes a second dose integrator including a second input configured to receive a second current generated from the charges carried by the implanted ions in the wafer, and a second output configured to output a second accumulated dosage value. The implantation system further includes a processing unit comparing the first accumulated dosage value and the second accumulated dosage value to detect a drift in one of the first and the second dose integrators.
摘要翻译：提供了一种用于在植入系统和植入系统中识别漂移剂量积分器的方法。植入系统包括第一剂量积分器和第二剂量积分器。第一剂量积分器包括被配置为接收由晶片中的注入离子携带的电荷产生的第一电流的第一输入和被配置为输出第一累积剂量值的第一输出。所述第二剂量积分器包括第二剂量积分器，所述第二剂量积分器包括被配置为接收从由所述晶片中的所述注入离子携带的电荷产生的第二电流的第二输入，以及被配置为输出第二累积剂量值的第二输出。植入系统还包括处理单元，比较第一累积剂量值和第二累积剂量值，以检测第一和第二剂量积分器之一中的漂移。

8. 发明申请

US20070257210A1 Preventing dosage drift with duplicate dose integrators 有权
标题翻译：用重复剂量积分器预防剂量漂移
公开(公告)号：US20070257210A1
公开(公告)日：2007-11-08
申请号：US11416874
申请日：2006-05-03
申请人： Jih-Hwa Wang , Otto Chen , Fang-Chi Chien , Tung-Li Lee , Pu-Fang Chen
发明人： Jih-Hwa Wang , Otto Chen , Fang-Chi Chien , Tung-Li Lee , Pu-Fang Chen
IPC分类号： H01J37/317
CPC分类号： H01J37/3171 , H01J37/304 , H01J2237/30433 , H01J2237/30455 , H01J2237/31703
摘要： A method for identifying a drifted dose integrator in an implantation system and an implantation system are provided. The implantation system includes a first dose integrator and a second dose integrator. The first dose integrator includes a first input configured to receive a first current generated from charges carried by implanted ions in a wafer, and a first output configured to output a first accumulated dosage value. The second dose integrator includes a second dose integrator including a second input configured to receive a second current generated from the charges carried by the implanted ions in the wafer, and a second output configured to output a second accumulated dosage value. The implantation system further includes a processing unit comparing the first accumulated dosage value and the second accumulated dosage value to detect a drift in one of the first and the second dose integrators.
摘要翻译：提供了一种用于在植入系统和植入系统中识别漂移剂量积分器的方法。植入系统包括第一剂量积分器和第二剂量积分器。第一剂量积分器包括被配置为接收由晶片中的注入离子携带的电荷产生的第一电流的第一输入和被配置为输出第一累积剂量值的第一输出。所述第二剂量积分器包括第二剂量积分器，所述第二剂量积分器包括被配置为接收从由所述晶片中的所述注入离子携带的电荷产生的第二电流的第二输入，以及被配置为输出第二累积剂量值的第二输出。植入系统还包括处理单元，比较第一累积剂量值和第二累积剂量值，以检测第一和第二剂量积分器之一中的漂移。

9. 发明授权

US08932945B2 Wafer alignment system and method 有权
标题翻译：晶圆对准系统及方法
公开(公告)号：US08932945B2
公开(公告)日：2015-01-13
申请号：US13544467
申请日：2012-07-09
申请人： Sen-Hong Syue , Chung-Chun Ho , Pu-Fang Chen , Shiang-Bau Wang
发明人： Sen-Hong Syue , Chung-Chun Ho , Pu-Fang Chen , Shiang-Bau Wang
IPC分类号： H01L21/02 , H01L21/762 , G11B20/18 , H01L29/78 , H01L29/68 , G03F1/00 , G03F1/36 , G03F7/20
CPC分类号： H01L21/02337 , G03F1/144 , G03F1/36 , G03F7/70425 , G11B20/18 , G11B20/1833 , G11B2020/183 , G11B2020/1836 , H01L21/68 , H01L21/762 , H01L21/76224 , H01L29/68 , H01L29/7833
摘要： A system and method for mitigating annealing fingerprints in semiconductor wafers is provided. An embodiment comprises aligning the semiconductor wafers prior to each annealing step. This alignment generates similar or identical fingerprints in each of the semiconductor wafers manufactured. With the fingerprint known, a single compensation model for a subsequent photoresist may be utilized to compensate for the fingerprint in each of the semiconductor wafers.
摘要翻译：提供了一种减轻半导体晶片退火指纹的系统和方法。一个实施例包括在每个退火步骤之前对准半导体晶片。该对准在制造的每个半导体晶片中产生类似或相同的指纹。利用指纹已知，用于后续光致抗蚀剂的单个补偿模型可用于补偿每个半导体晶片中的指纹。

10. 发明申请

US20140011348A1 Wafer Alignment System and Method 有权
标题翻译：晶圆对准系统和方法
公开(公告)号：US20140011348A1
公开(公告)日：2014-01-09
申请号：US13544467
申请日：2012-07-09
申请人： Sen-Hong Syue , Chung-Chun Ho , Pu-Fang Chen , Shiang-Bau Wang
发明人： Sen-Hong Syue , Chung-Chun Ho , Pu-Fang Chen , Shiang-Bau Wang
IPC分类号： H01L21/306 , H01L21/26
CPC分类号： H01L21/02337 , G03F1/144 , G03F1/36 , G03F7/70425 , G11B20/18 , G11B20/1833 , G11B2020/183 , G11B2020/1836 , H01L21/68 , H01L21/762 , H01L21/76224 , H01L29/68 , H01L29/7833
摘要： A system and method for mitigating annealing fingerprints in semiconductor wafers is provided. An embodiment comprises aligning the semiconductor wafers prior to each annealing step. This alignment generates similar or identical fingerprints in each of the semiconductor wafers manufactured. With the fingerprint known, a single compensation model for a subsequent photoresist may be utilized to compensate for the fingerprint in each of the semiconductor wafers.
摘要翻译：提供了一种减轻半导体晶片退火指纹的系统和方法。一个实施例包括在每个退火步骤之前对准半导体晶片。该对准在制造的每个半导体晶片中产生类似或相同的指纹。利用指纹已知，用于后续光致抗蚀剂的单个补偿模型可用于补偿每个半导体晶片中的指纹。

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