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1. 发明授权

US06169009A Methods of etching platinum group metal film and forming lower electrode of capacitor 有权
标题翻译：蚀刻铂族金属膜并形成电容器的下电极的方法
公开(公告)号：US06169009A
公开(公告)日：2001-01-02
申请号：US09203337
申请日：1998-12-02
申请人： Byong-sun Ju , Hyoun-woo Kim , Chang-jin Kang , Joo-tae Moon , Byeong-yun Nam
发明人： Byong-sun Ju , Hyoun-woo Kim , Chang-jin Kang , Joo-tae Moon , Byeong-yun Nam
IPC分类号： H01L2120
CPC分类号： C23F4/00 , H01L21/32136 , H01L28/60
摘要： A method of etching a platinum group metal film uses a gas mixture containing argon (Ar), oxygen (O2) and halogen gases and a method of forming a lower electrode of a capacitor uses the etching method. The gas mixture contains O2, Ar, and a third component, preferably a halogen, e.g., chlorine (Cl2) or hydrogen bromide (HBr). In the method of forming a lower electrode, a conductive film containing a metal belonging to a platinum (Pt) group is formed on a semiconductor substrate, a hard mask partially exposing the conductive film is then formed on the conductive film. Then, the exposed conductive film is dry-etched using the hard mask as an etching mask and a three-component gas mixture containing argon (Ar) and oxygen (O2), to form a conductive film pattern beneath the hard mask, and the hard mask is then removed.
摘要翻译：蚀刻铂族金属膜的方法使用包含氩（Ar），氧（O 2）和卤素气体的气体混合物，并且形成电容器的下电极的方法使用蚀刻方法。气体混合物含有O 2，Ar和第三组分，优选卤素，例如氯（Cl 2）或溴化氢（HBr）。在形成下电极的方法中，在半导体衬底上形成含有属于铂（Pt）基团的金属的导电膜，然后在导电膜上形成部分地暴露导电膜的硬掩模。然后，使用硬掩模作为蚀刻掩模和含有氩（Ar）和氧（O 2）的三组分气体混合物来干燥暴露的导电膜，以在硬掩模下形成导电膜图案，并且硬然后取下面具。

2. 发明授权

US07098135B2 Semiconductor device including bit line formed using damascene technique and method of fabricating the same 有权
标题翻译：包括使用镶嵌技术形成的位线的半导体器件及其制造方法
公开(公告)号：US07098135B2
公开(公告)日：2006-08-29
申请号：US10703328
申请日：2003-11-07
申请人： Seung-pil Chung , Chang-jin Kang , Jeong-sic Jeon , Kyeong-koo Chi , Seung-young Son , Sang-yong Kim
发明人： Seung-pil Chung , Chang-jin Kang , Jeong-sic Jeon , Kyeong-koo Chi , Seung-young Son , Sang-yong Kim
IPC分类号： H01L21/311
CPC分类号： H01L27/10885 , H01L21/31116 , H01L21/76816 , H01L21/76831 , H01L27/10888 , H01L27/10891
摘要： A semiconductor device including a bit line formed using a damascene technique and a method of fabricating the same. The method includes forming an insulating layer on a substrate, forming a groove by etching the insulating layer to a partial depth, and forming spacers on the inner walls of the groove. An opening is formed by etching the insulating layer disposed under the groove using the spacers as an etch mask. A conductive layer is formed to fill the opening. A capping layer is formed to fill the groove.
摘要翻译：一种包括使用镶嵌技术形成的位线的半导体器件及其制造方法。该方法包括在基板上形成绝缘层，通过将绝缘层蚀刻到局部深度形成沟槽，并在槽的内壁上形成间隔物。通过使用间隔物作为蚀刻掩模蚀刻设置在凹槽下方的绝缘层来形成开口。形成导电层以填充开口。形成覆盖层以填充凹槽。

3. 发明授权

US07709389B2 Method of fabricating a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07709389B2
公开(公告)日：2010-05-04
申请号：US11480545
申请日：2006-07-05
申请人： Dong-chan Kim , Chang-jin Kang , Kyeong-koo Chi
发明人： Dong-chan Kim , Chang-jin Kang , Kyeong-koo Chi
IPC分类号： H01L21/302
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/76816 , H01L21/76897 , Y10S438/947
摘要： A method of fabricating a semiconductor device comprising a method of forming an etching mask used for etching a semiconductor base material is disclosed. The method of fabricating a semiconductor device comprises forming hard mask patterns on a semiconductor base material; forming material layers covering the lateral and top surfaces of the hard mask patterns to form openings between adjacent hard mask patterns, wherein the width of each opening is smaller than the distance between adjacent hard mask patterns; and etching the semiconductor base material using the hard mask patterns and material layers as an etching mask.
摘要翻译：公开了一种制造半导体器件的方法，包括形成用于蚀刻半导体基底材料的蚀刻掩模的方法。制造半导体器件的方法包括在半导体基底材料上形成硬掩模图案; 形成覆盖硬掩模图案的侧表面和顶表面的材料层，以在相邻的硬掩模图案之间形成开口，其中每个开口的宽度小于相邻硬掩模图案之间的距离; 并使用硬掩模图案和材料层作为蚀刻掩模蚀刻半导体基底材料。

4. 发明申请

US20080113511A1 Method of forming fine patterns using double patterning process 有权
标题翻译：使用双重图案化工艺形成精细图案的方法
公开(公告)号：US20080113511A1
公开(公告)日：2008-05-15
申请号：US11730264
申请日：2007-03-30
申请人： Sang-joon Park , Yong-hyun Kwon , Jun Seo , Sung-il Cho , Chang-jin Kang , Jae-kyu Ha
发明人： Sang-joon Park , Yong-hyun Kwon , Jun Seo , Sung-il Cho , Chang-jin Kang , Jae-kyu Ha
IPC分类号： H01L21/311
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76816 , H01L21/76897
摘要： A double pattern method of forming a plurality of contact holes in a material layer formed on a substrate is disclosed. The method forms a parallel plurality of first hard mask patterns separated by a first pitch in a first direction on the material layer, a self-aligned parallel plurality of second hard mask patterns interleaved with the first hard mask patterns and separated from the first hard mask patterns by a buffer layer to form composite mask patterns, and a plurality of upper mask patterns in a second direction intersecting the first direction to mask selected portions of the buffer layer in conjunction with the composite mask patterns. The method then etches non-selected portions of the buffer layer using the composite hard mask patterns and the upper mask patterns as an etch mask to form a plurality of hard mask holes exposing selected portions of the material layer, and then etches the selected portions of the material layer to form the plurality of contact holes.
摘要翻译：公开了一种在形成在基板上的材料层中形成多个接触孔的双重图案方法。该方法形成在材料层上沿第一方向以第一间距分开的平行多个第一硬掩模图案，与第一硬掩模图案交错并与第一硬掩模分离的自对准并行多个第二硬掩模图案通过缓冲层形成图案以形成复合掩模图案，以及与第一方向相交的第二方向的多个上掩模图案，以与复合掩模图案一起掩蔽缓冲层的选定部分。然后，该方法使用复合硬掩模图案和上掩模图案作为蚀刻掩模蚀刻缓冲层的未选择部分，以形成暴露材料层的选定部分的多个硬掩模孔，然后蚀刻所选择的部分所述材料层形成所述多个接触孔。

5. 发明授权

US07052952B2 Method for forming wire line by damascene process using hard mask formed from contacts 失效
标题翻译：通过使用由接触形成的硬掩模的镶嵌工艺形成金属丝线的方法
公开(公告)号：US07052952B2
公开(公告)日：2006-05-30
申请号：US10779494
申请日：2004-02-13
申请人： In-deog Bae , Chang-jin Kang , Jeong-sic Jeon , Kyeong-koo Chi
发明人： In-deog Bae , Chang-jin Kang , Jeong-sic Jeon , Kyeong-koo Chi
IPC分类号： H01L21/8242
CPC分类号： H01L27/10885 , H01L21/76804 , H01L21/76831 , H01L21/76877 , H01L21/76897 , H01L27/0214 , H01L27/10855 , Y10S438/978
摘要： A method for forming a wire line by a damascene process includes forming a first insulating layer on a semiconductor substrate, etching the first insulating layer to form a contact hole, and forming a first conductive layer over the first insulating layer that fills the contact hole. The first conductive layer is patterned, and a storage node contact is formed that fills the contact hole and is electrically connected to the semiconductor substrate. A hard mask is formed over the storage node contact and the first insulating layer is etched using the hard mask as an etch mask to form a trench in the first insulating layer. A bit line is formed in the trench that is electrically connected to the semiconductor substrate. A second insulating layer is formed that covers the bit line. The second insulating layer and the hard mask are planarized and a storage node of a capacitor is formed on the storage node contact.
摘要翻译：通过镶嵌工艺形成导线的方法包括在半导体衬底上形成第一绝缘层，蚀刻第一绝缘层以形成接触孔，并在填充接触孔的第一绝缘层上形成第一导电层。图案化第一导电层，并且形成填充接触孔并与半导体衬底电连接的存储节点接触。在存储节点接触件上形成硬掩模，并且使用硬掩模作为蚀刻掩模蚀刻第一绝缘层，以在第一绝缘层中形成沟槽。在与半导体衬底电连接的沟槽中形成位线。形成覆盖位线的第二绝缘层。第二绝缘层和硬掩模被平坦化，并且在存储节点接触件上形成电容器的存储节点。

6. 发明授权

US07531449B2 Method of forming fine patterns using double patterning process 有权
标题翻译：使用双重图案化工艺形成精细图案的方法
公开(公告)号：US07531449B2
公开(公告)日：2009-05-12
申请号：US11730264
申请日：2007-03-30
申请人： Sang-joon Park , Yong-hyun Kwon , Jun Seo , Sung-il Cho , Chang-jin Kang , Jae-kyu Ha
发明人： Sang-joon Park , Yong-hyun Kwon , Jun Seo , Sung-il Cho , Chang-jin Kang , Jae-kyu Ha
IPC分类号： H01L21/4763
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76816 , H01L21/76897
摘要： A double pattern method of forming a plurality of contact holes in a material layer formed on a substrate is disclosed. The method forms a parallel plurality of first hard mask patterns separated by a first pitch in a first direction on the material layer, a self-aligned parallel plurality of second hard mask patterns interleaved with the first hard mask patterns and separated from the first hard mask patterns by a buffer layer to form composite mask patterns, and a plurality of upper mask patterns in a second direction intersecting the first direction to mask selected portions of the buffer layer in conjunction with the composite mask patterns. The method then etches non-selected portions of the buffer layer using the composite hard mask patterns and the upper mask patterns as an etch mask to form a plurality of hard mask holes exposing selected portions of the material layer, and then etches the selected portions of the material layer to form the plurality of contact holes.
摘要翻译：公开了一种在形成在基板上的材料层中形成多个接触孔的双重图案方法。该方法形成在材料层上沿第一方向以第一间距分开的平行多个第一硬掩模图案，与第一硬掩模图案交错并与第一硬掩模分离的自对准并行多个第二硬掩模图案通过缓冲层形成图案以形成复合掩模图案，以及与第一方向相交的第二方向的多个上掩模图案，以与复合掩模图案一起掩蔽缓冲层的选定部分。然后，该方法使用复合硬掩模图案和上掩模图案作为蚀刻掩模蚀刻缓冲层的未选择部分，以形成暴露材料层的选定部分的多个硬掩模孔，然后蚀刻所选择的部分所述材料层形成所述多个接触孔。

7. 发明申请

US20070287299A1 Method of forming a semiconductor device 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US20070287299A1
公开(公告)日：2007-12-13
申请号：US11711781
申请日：2007-02-28
申请人： Doo-youl Lee , Suk-joo Lee , Yool Kang , Han-ku Cho , Chang-jin Kang , Jae-ok Yoo , Sung-chan Park
发明人： Doo-youl Lee , Suk-joo Lee , Yool Kang , Han-ku Cho , Chang-jin Kang , Jae-ok Yoo , Sung-chan Park
IPC分类号： H01L21/266
CPC分类号： H01L21/0337
摘要： A method of forming a semiconductor device includes forming a first mask pattern on a target layer, the first mask pattern exposing a first portion of the target layer, forming an intermediate material layer, including depositing an intermediate material layer film on a side of the first mask pattern and the first portion of the target layer, and thinning the intermediate material layer film to form the intermediate material layer, forming a second mask pattern that exposes a second portion of the intermediate material layer, removing the exposed second portion of the intermediate material layer to expose the target layer, and patterning the target layer using the first and second mask patterns as patterning masks.
摘要翻译：形成半导体器件的方法包括：在目标层上形成第一掩模图案，第一掩模图案暴露目标层的第一部分，形成中间材料层，包括在第一掩模图案的一侧上沉积中间材料层膜掩模图案和目标层的第一部分，并且使中间材料层膜变薄以形成中间材料层，形成暴露中间材料层的第二部分的第二掩模图案，去除中间材料的暴露的第二部分层以露出目标层，以及使用第一和第二掩模图案作为图案掩模来图案化目标层。

8. 发明申请

US20060246666A1 Method of fabricating flash memory with u-shape floating gate 审中-公开
标题翻译：用u形浮栅制造闪速存储器的方法
公开(公告)号：US20060246666A1
公开(公告)日：2006-11-02
申请号：US11410837
申请日：2006-04-26
申请人： Jeong-nam Han , Dong-chan Kim , Chang-jin Kang , Kyeong-koo Chi , Woo-gwan Shim , Hyo-san Lee , Chang-ki Hong , Sang-jun Choi
发明人： Jeong-nam Han , Dong-chan Kim , Chang-jin Kang , Kyeong-koo Chi , Woo-gwan Shim , Hyo-san Lee , Chang-ki Hong , Sang-jun Choi
IPC分类号： H01L21/336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11543
摘要： A method of fabricating a flash memory having a U-shape floating gate is provided. The method includes forming adjacent isolation layers separated by a gap and forming a tunnel oxide layer in the gap. After a conductive layer is formed on the tunnel oxide layer to a thickness not to fill the gap, a polishing sacrificial layer is formed on the conductive layer. The sacrificial layer and the conductive layer on the isolation layers are removed, thereby forming a U-shape floating gate self-aligned in the gap, and concurrently forming a sacrificial layer pattern within an inner portion of the floating gate. Selected isolation layers are then recessed to expose sidewalls of the floating gate. The sacrificial layer pattern is then removed from the floating gate to expose an upper surface of the floating gate.
摘要翻译：提供一种制造具有U形浮动栅极的闪速存储器的方法。该方法包括形成由间隙隔开并在间隙中形成隧道氧化物层的相邻隔离层。在隧道氧化物层上形成导电层至不填充间隙的厚度之后，在导电层上形成抛光牺牲层。除去隔离层上的牺牲层和导电层，从而在间隙中形成自对准的U形浮动栅极，同时在浮栅的内部部分内形成牺牲层图案。然后将选定的隔离层凹入以露出浮动栅极的侧壁。然后从浮动栅极去除牺牲层图案以暴露浮动栅极的上表面。

9. 发明授权

US6143654A Method of forming tungsten pattern for a semiconductor device 有权
标题翻译：形成半导体器件的钨图案的方法
公开(公告)号：US6143654A
公开(公告)日：2000-11-07
申请号：US229337
申请日：1999-01-13
申请人： Jin-hwan Hahm , Chang-jin Kang
发明人： Jin-hwan Hahm , Chang-jin Kang
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/3213 , H01L23/52 , H01L21/44
CPC分类号： H01L21/32135 , H01L21/32139
摘要： A capping film having a lower etch rate than a tungsten film is formed thereon and a photoresist layer is formed on the capping film. Preferably, the capping film is a titanium-based layer or an aluminum-based layer. After a photoresist pattern is formed by exposing and developing the photoresist film, the tungsten film is patterned by a dry etch method. During the etching of the tungsten film, the capping film reacts with the etching material to form a polymer which serves as a hard mask for the tungsten film. Preferably, the capping film also has a lower reflectivity at the exposing wavelength for the photoresist than the tungsten film, so the exposure of the photoresist may be controlled. Alternatively, or additionally, an anti-reflective film is provided between the capping film and the photoresist to further reduce the effect of the reflection of the tungsten film. Thus, patterning failures can be prevented. Such a method is particularly advantageous when the tungsten film pattern formed thereby is to be used as a bit line in a semiconductor device, particularly a pattern having a design rule of 0.34 .mu.m or less.
摘要翻译：在其上形成具有比钨膜蚀刻速率更低的覆盖膜，并且在封盖膜上形成光致抗蚀剂层。优选地，封盖膜是钛基层或铝基层。在通过曝光和显影光致抗蚀剂膜形成光致抗蚀剂图案之后，通过干蚀刻方法对钨膜进行图案化。在钨膜的蚀刻期间，封盖膜与蚀刻材料反应形成用作钨膜的硬掩模的聚合物。优选地，封盖膜在光致抗蚀剂的曝光波长处还具有比钨膜更低的反射率，因此可以控制光致抗蚀剂的曝光。或者或另外，在覆盖膜和光致抗蚀剂之间提供抗反射膜，以进一步降低钨膜的反射效果。因此，可以防止图案化故障。当由此形成的钨膜图形用作半导体器件中的位线时，特别是设计规则为0.34μm或更小的图案，这种方法是特别有利的。

10. 发明授权

US07803517B2 Method of forming fine contact hole and method of fabricating semiconductor device using block copolymers 有权
标题翻译：形成微细接触孔的方法和使用嵌段共聚物制造半导体器件的方法
公开(公告)号：US07803517B2
公开(公告)日：2010-09-28
申请号：US11590663
申请日：2006-10-31
申请人： Sung-chan Park , Chang-jin Kang
发明人： Sung-chan Park , Chang-jin Kang
IPC分类号： G03F1/00 , B28B19/00
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： A method of forming a contact hole includes forming a plurality of lower patterns on a substrate. An insulation layer is formed on the lower patterns. A self-assemble induction layer is formed on the insulation layer. A recess is formed in the self-assemble induction layer in alignment with the lower patterns. A block copolymer layer is formed in the recess to form a polymer domain at a distance from a sidewall of the recess and a polymer matrix surrounding the polymer domain. The polymer domain is removed. The self-assemble induction layer is etched using the polymer matrix as a mask to form an opening through the self-assemble induction layer to expose the insulation layer. The insulation layer exposed by the opening is etched using the self-assemble induction layer as a mask so as to form a contact hole.
摘要翻译：形成接触孔的方法包括在基板上形成多个下部图案。在下部图案上形成绝缘层。在绝缘层上形成自组装感应层。在自组装感应层中形成与下部图形对准的凹部。在凹部中形成嵌段共聚物层，以形成与凹陷的侧壁相距一定距离的聚合物结构域和围绕聚合物结构域的聚合物基体。去除聚合物结构域。使用聚合物基质作为掩模蚀刻自组装感应层，以通过自组装感应层形成开口以暴露绝缘层。使用自组装感应层作为掩模蚀刻由开口暴露的绝缘层，以形成接触孔。

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