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1. 发明授权

US07883942B2 Contact structure of semiconductor device, manufacturing method thereof, thin film transistor array panel including contact structure, and manufacturing method thereof 有权
标题翻译：半导体器件的接触结构，其制造方法，包括接触结构的薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07883942B2
公开(公告)日：2011-02-08
申请号：US11875199
申请日：2007-10-19
申请人： Bum-Gee Baek , Kwon-Young Choi , Young-Joon Rhee , Bong-Joo Kang , Seung-Taek Lim , Hyang-Shik Kong , Won-Joo Kim
发明人： Bum-Gee Baek , Kwon-Young Choi , Young-Joon Rhee , Bong-Joo Kang , Seung-Taek Lim , Hyang-Shik Kong , Won-Joo Kim
IPC分类号： H01L21/00
CPC分类号： G02F1/13458 , G02F1/13439 , G02F1/136227 , G02F1/136286 , G02F2001/136236 , G02F2001/13629 , H01L27/12 , H01L27/124 , H01L27/1288 , H01L29/41733 , H01L29/42384 , H01L29/4908
摘要： Gate lines are formed on a substrate. A gate insulating layer, an intrinsic a-Si layer, an extrinsic a-Si layer, a lower film of Cr and an upper film of Al containing metal are sequentially deposited. A photoresist having thicker first portions on wire areas and thinner second portions on channel areas is formed on the upper film. The upper film on remaining areas are wet-etched, and the lower film and the a-Si layers on the remaining areas are dry-etched along with the second portions of the photoresist. The upper film, the lower film, and the extrinsic a-Si layer on the channel areas are removed. The removal of the upper film and the lower film on the channel areas are performed by wet etching, and the first portions of the photoresist are removed after the removal of the upper film on the channel areas.
摘要翻译：栅极线形成在基板上。依次沉积栅极绝缘层，本征a-Si层，外部a-Si层，下部Cr膜和含Al金属的上部膜。在上部膜上形成具有较粗的第一部分在导线区域上的光刻胶和在沟道区域上较薄的第二部分的光致抗蚀剂。在其余区域上的上部膜被湿式蚀刻，并且其余区域上的下部膜和a-Si层与光致抗蚀剂的第二部分一起被干蚀刻。除去沟道区上的上膜，下膜和非本征a-Si层。通过湿蚀刻来进行通道区域上的上膜和下膜的去除，并且在去除沟道区上的上膜之后去除光致抗蚀剂的第一部分。

2. 发明授权

US07294855B2 Contact structure of semiconductor device, manufacturing method thereof, thin film transistor array panel including contact structure, and manufacturing method thereof 失效
标题翻译：半导体器件的接触结构，其制造方法，包括接触结构的薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07294855B2
公开(公告)日：2007-11-13
申请号：US10653556
申请日：2003-09-02
申请人： Bum-Gee Baek , Kwon-Young Choi , Young-Joon Rhee , Bong-Joo Kang , Seung-Taek Lim , Hyang-Shik Kong , Won-Joo Kim
发明人： Bum-Gee Baek , Kwon-Young Choi , Young-Joon Rhee , Bong-Joo Kang , Seung-Taek Lim , Hyang-Shik Kong , Won-Joo Kim
IPC分类号： H01L29/04
CPC分类号： G02F1/13458 , G02F1/13439 , G02F1/136227 , G02F1/136286 , G02F2001/136236 , G02F2001/13629 , H01L27/12 , H01L27/124 , H01L27/1288 , H01L29/41733 , H01L29/42384 , H01L29/4908
摘要： Gate lines are formed on a substrate. A gate insulating layer, an intrinsic a-Si layer, an extrinsic a-Si layer, a lower film of Cr and an upper film of Al containing metal are sequentially deposited. A photoresist having thicker first portions on wire areas and thinner second portions on channel areas is formed on the upper film. The upper film on remaining areas are wet-etched, and the lower film and the a-Si layers on the remaining areas are dry-etched along with the second portions of the photoresist. The upper film, the lower film, and the extrinsic a-Si layer on the channel areas are removed. The removal of the upper film and the lower film on the channel areas are performed by wet etching, and the first portions of the photoresist are removed after the removal of the upper film on the channel areas.
摘要翻译：栅极线形成在基板上。依次沉积栅极绝缘层，本征a-Si层，外部a-Si层，下部Cr膜和含Al金属的上部膜。在上部膜上形成具有较粗的第一部分在导线区域上的光刻胶和在沟道区域上较薄的第二部分的光致抗蚀剂。在其余区域上的上部膜被湿式蚀刻，并且其余区域上的下部膜和a-Si层与光致抗蚀剂的第二部分一起被干蚀刻。除去沟道区上的上膜，下膜和非本征a-Si层。通过湿蚀刻来进行通道区域上的上膜和下膜的去除，并且在去除沟道区上的上膜之后去除光致抗蚀剂的第一部分。

3. 发明申请

US20080090404A1 CONTACT STRUCTURE OF A WIRES AND METHOD MANUFACTURING THE SAME, AND THIN FILM TRANSISTOR SUBSTRATE INCLUDING THE CONTACT STRUCTURE AND METHOD MANUFACTURING THE SAME 审中-公开
标题翻译：一种线的接触结构及其制造方法，以及包括接触结构的薄膜晶体管基板及其制造方法
公开(公告)号：US20080090404A1
公开(公告)日：2008-04-17
申请号：US11947204
申请日：2007-11-29
申请人： Seung-Taek Lim , Mun-Pyo Hong , Nam-Seok Roh , Young-Joo Song , Sang-Ki Kwak , Kwon-Young Choi , Keun-kyu Song
发明人： Seung-Taek Lim , Mun-Pyo Hong , Nam-Seok Roh , Young-Joo Song , Sang-Ki Kwak , Kwon-Young Choi , Keun-kyu Song
IPC分类号： H01L21/4763
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , G02F2001/13629 , H01L21/76805 , H01L21/76816 , H01L23/53223 , H01L27/124 , H01L2924/0002 , H01L2924/00
摘要： In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes, and gate pads. A gate insulating layer is deposited onto the insulating substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. A data line assembly is formed on the ohmic contact layer with a chrome-based under-layer and an aluminum alloy-based over-layer. The data line assembly has data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads. The sidewall of the under-layers for the gate line assembly and the data line assembly is exposed through the contact holes. An IZO-based layer is deposited onto the substrate, and patterned to thereby form pixel electrodes, subsidiary gate pads, and subsidiary data pads. The pixel electrodes are connected to the sidewall of the drain electrodes, and the subsidiary gate and data pads are connected to the sidewall of the gate and the data pads.
摘要翻译：在制造用于液晶显示器的薄膜晶体管阵列基板的方法中，栅极线组件在沿水平方向前进的基底上形成有铬基底层和基于铝合金的超层。栅极线组件具有栅极线，栅电极和栅极焊盘。栅极绝缘层沉积在绝缘基板上，使得栅极绝缘层覆盖栅极线组件。在栅极绝缘层上依次形成半导体层和欧姆接触层。数据线组件在欧姆接触层上形成有铬基底层和基于铝合金的超层。数据线组件具有跨越栅极线，源电极，漏电极和数据焊盘的数据线。保护层沉积到衬底上，并被图案化，从而形成露出漏电极，栅极焊盘和数据焊盘的接触孔。用于栅极线组件和数据线组件的下层的侧壁通过接触孔暴露。将基于IZO的层沉积到衬底上并构图，从而形成像素电极，辅助栅极焊盘和辅助数据焊盘。像素电极连接到漏电极的侧壁，辅助栅极和数据焊盘连接到栅极和数据焊盘的侧壁。

4. 发明授权

US07659625B2 Contact structure of a wires and method manufacturing the same, and thin film transistor substrate including the contact structure and method manufacturing the same 有权
标题翻译：电线的接触结构及其制造方法，以及包括接触结构的薄膜晶体管基板及其制造方法
公开(公告)号：US07659625B2
公开(公告)日：2010-02-09
申请号：US12333973
申请日：2008-12-12
申请人： Seung-Taek Lim , Mun-Pyo Hong , Nam-Seok Roh , Young-Joo Song , Sang-Ki Kwak , Kwon-Young Choi , Keun-Kyu Song
发明人： Seung-Taek Lim , Mun-Pyo Hong , Nam-Seok Roh , Young-Joo Song , Sang-Ki Kwak , Kwon-Young Choi , Keun-Kyu Song
IPC分类号： H01L23/48
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , G02F2001/13629 , H01L21/76805 , H01L21/76816 , H01L23/53223 , H01L27/124 , H01L2924/0002 , H01L2924/00
摘要： In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes, and gate pads. A gate insulating layer is deposited onto the insulating substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. A data line assembly is formed on the ohmic contact layer with a chrome-based under-layer and an aluminum alloy-based over-layer. The data line assembly has data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads. The sidewall of the under-layers for the gate line assembly and the data line assembly is exposed through the contact holes. An IZO-based layer is deposited onto the substrate, and patterned to thereby form pixel electrodes, subsidiary gate pads, and subsidiary data pads. The pixel electrodes are connected to the sidewall of the drain electrodes, and the subsidiary gate and data pads are connected to the sidewall of the gate and the data pads.
摘要翻译：在制造用于液晶显示器的薄膜晶体管阵列基板的方法中，栅极线组件在沿水平方向前进的基底上形成有铬基底层和基于铝合金的超层。栅极线组件具有栅极线，栅电极和栅极焊盘。栅极绝缘层沉积在绝缘基板上，使得栅极绝缘层覆盖栅极线组件。在栅极绝缘层上依次形成半导体层和欧姆接触层。数据线组件在欧姆接触层上形成有铬基底层和基于铝合金的超层。数据线组件具有跨越栅极线，源电极，漏电极和数据焊盘的数据线。保护层沉积到衬底上，并被图案化，从而形成露出漏电极，栅极焊盘和数据焊盘的接触孔。用于栅极线组件和数据线组件的下层的侧壁通过接触孔暴露。将基于IZO的层沉积到衬底上并构图，从而形成像素电极，辅助栅极焊盘和辅助数据焊盘。像素电极连接到漏电极的侧壁，辅助栅极和数据焊盘连接到栅极和数据焊盘的侧壁。

5. 发明授权

US07303987B2 Contact structure of a wires and method manufacturing the same, and thin film transistor substrate including the contact structure and method manufacturing the same 有权
标题翻译：电线的接触结构及其制造方法，以及包括接触结构的薄膜晶体管基板及其制造方法
公开(公告)号：US07303987B2
公开(公告)日：2007-12-04
申请号：US10475903
申请日：2002-04-02
申请人： Seung-Taek Lim , Mun-Pyo Hong , Nam-Seok Roh , Young-Joo Song , Sang-Ki Kwak , Kwon-Young Choi , Keun-Kyu Song
发明人： Seung-Taek Lim , Mun-Pyo Hong , Nam-Seok Roh , Young-Joo Song , Sang-Ki Kwak , Kwon-Young Choi , Keun-Kyu Song
IPC分类号： H01L21/4763
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , G02F2001/13629 , H01L21/76805 , H01L21/76816 , H01L23/53223 , H01L27/124 , H01L2924/0002 , H01L2924/00
摘要： In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes, and gate pads. A gate insulating layer is deposited onto the insulating substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. A data line assembly is formed on the ohmic contact layer with a chrome-based under-layer and an aluminum alloy-based over-layer. The data line assembly has data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads. The sidewall of the under-layers for the gate line assembly and the data line assembly is exposed through the contact holes. An IZO-based layer is deposited onto the substrate, and patterned to thereby form pixel electrodes, subsidiary gate pads, and subsidiary data pads. The pixel electrodes are connected to the sidewall of the drain electrodes, and the subsidiary gate and data pads are connected to the sidewall of the gate and the data pads.
摘要翻译：在制造用于液晶显示器的薄膜晶体管阵列基板的方法中，栅极线组件在沿水平方向前进的基底上形成有铬基底层和基于铝合金的超层。栅极线组件具有栅极线，栅电极和栅极焊盘。栅极绝缘层沉积在绝缘基板上，使得栅极绝缘层覆盖栅极线组件。在栅极绝缘层上依次形成半导体层和欧姆接触层。数据线组件在欧姆接触层上形成有铬基底层和基于铝合金的超层。数据线组件具有跨越栅极线，源电极，漏电极和数据焊盘的数据线。保护层沉积到衬底上，并被图案化，从而形成露出漏电极，栅极焊盘和数据焊盘的接触孔。用于栅极线组件和数据线组件的下层的侧壁通过接触孔暴露。将基于IZO的层沉积到衬底上并构图，从而形成像素电极，辅助栅极焊盘和辅助数据焊盘。像素电极连接到漏电极的侧壁，辅助栅极和数据焊盘连接到栅极和数据焊盘的侧壁。

6. 发明授权

US07709304B2 Thin film transistor array panel, manufacturing method thereof, and mask therefor 失效
标题翻译：薄膜晶体管阵列面板及其制造方法及其掩模
公开(公告)号：US07709304B2
公开(公告)日：2010-05-04
申请号：US11824879
申请日：2007-07-02
申请人： Woon-Yong Park , Won-Hee Lee , Il-Gon Kim , Seung-Taek Lim , You-Lee Song , Sahng-Ik Jun
发明人： Woon-Yong Park , Won-Hee Lee , Il-Gon Kim , Seung-Taek Lim , You-Lee Song , Sahng-Ik Jun
IPC分类号： H01L21/00
CPC分类号： G02F1/136227 , G02F2001/136236 , G03F1/00
摘要： A passivation layer is deposited and a photoresist is formed. The photoresist includes first to third portions with decreased thickness, the second portions located on portions of drain electrodes and data lines and the third portions located on portions of gate lines. A mask for forming the photoresist has rectilinear slits with width and distance of about 0.8-2.0 microns on an area corresponding to the second portions. The passivation layer and an underlying semiconductor layer as well as the photoresist are etched to expose portions of the gate insulating layer under the third portions of the photoresist as well as portions of the passivation layer under the second portions of the photoresist. The exposed portions of the passivation layer and the gate insulating layer are removed to expose the drain electrodes, the gate lines and the data lines as well as portions of the semiconductor layer, which are subsequently removed.
摘要翻译：沉积钝化层并形成光致抗蚀剂。光致抗蚀剂包括具有减小的厚度的第一至第三部分，第二部分位于漏电极和数据线的部分上，第三部分位于栅极线的部分上。用于形成光致抗蚀剂的掩模具有在对应于第二部分的区域上具有约0.8-2.0微米的宽度和距离的直线狭缝。蚀刻钝化层和底层半导体层以及光致抗蚀剂以暴露在光致抗蚀剂的第三部分之下的栅绝缘层的部分以及在光致抗蚀剂的第二部分下的钝化层的部分。去除钝化层和栅极绝缘层的暴露部分，以暴露出漏电极，栅极线和数据线以及随后被去除的部分半导体层。

7. 发明申请

US20070259289A1 Thin film transistor array panel, manufacturing method thereof, and mask therefor 失效
标题翻译：薄膜晶体管阵列面板及其制造方法及其掩模
公开(公告)号：US20070259289A1
公开(公告)日：2007-11-08
申请号：US11824879
申请日：2007-07-02
申请人： Woon-Yong Park , Won-Hee Lee , Il-Gon Kim , Seung-Taek Lim , You-Lee Song , Sahng-Ik Jun
发明人： Woon-Yong Park , Won-Hee Lee , Il-Gon Kim , Seung-Taek Lim , You-Lee Song , Sahng-Ik Jun
IPC分类号： G03C5/00
CPC分类号： G02F1/136227 , G02F2001/136236 , G03F1/00
摘要： A passivation layer is deposited and a photoresist is formed. The photoresist includes first to third portions with decreased thickness, the second portions located on portions of drain electrodes and data lines and the third portions located on portions of gate lines. A mask for forming the photoresist has rectilinear slits with width and distance of about 0.8-2.0 microns on an area corresponding to the second portions. The passivation layer and an underlying semiconductor layer as well as the photoresist are etched to expose portions of the gate insulating layer under the third portions of the photoresist as well as portions of the passivation layer under the second portions of the photoresist. The exposed portions of the passivation layer and the gate insulating layer are removed to expose the drain electrodes, the gate lines and the data lines as well as portions of the semiconductor layer, which are subsequently removed.
摘要翻译：沉积钝化层并形成光致抗蚀剂。光致抗蚀剂包括具有减小的厚度的第一至第三部分，第二部分位于漏电极和数据线的部分上，第三部分位于栅极线的部分上。用于形成光致抗蚀剂的掩模具有在对应于第二部分的区域上具有约0.8-2.0微米的宽度和距离的直线狭缝。蚀刻钝化层和底层半导体层以及光致抗蚀剂以暴露在光致抗蚀剂的第三部分之下的栅极绝缘层的部分以及在光致抗蚀剂的第二部分下的钝化层的部分。去除钝化层和栅极绝缘层的暴露部分，以露出漏电极，栅极线和数据线以及随后被去除的部分半导体层。

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