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1. 发明申请

US20080210943A1 THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF 有权
标题翻译：薄膜晶体管阵列及其制造方法
公开(公告)号：US20080210943A1
公开(公告)日：2008-09-04
申请号：US12119707
申请日：2008-05-13
申请人： Sahng-Ik Jun , Jae-Hong Jeon , Kwon-Young Choi , Jeong-Young Lee
发明人： Sahng-Ik Jun , Jae-Hong Jeon , Kwon-Young Choi , Jeong-Young Lee
IPC分类号： H01L27/088
CPC分类号： H01L27/124 , H01L29/41733
摘要： A thin film transistor array panel is provided, which includes: a substrate; a first signal line formed on the substrate; a second signal line formed on the substrate and intersecting the first signal line; a thin film transistor including a gate electrode connected to the first signal line and having an edge substantially parallel to the first signal line, a source electrode connected to the second signal line, and a drain electrode overlapping the edge of the gate electrode; and a pixel electrode connected to the drain electrode.
摘要翻译：提供薄膜晶体管阵列面板，其包括：基板; 形成在所述基板上的第一信号线; 形成在所述基板上并与所述第一信号线相交的第二信号线; 薄膜晶体管，包括连接到第一信号线的栅极，并且具有基本上平行于第一信号线的边缘，连接到第二信号线的源电极和与栅电极的边缘重叠的漏电极; 以及连接到漏电极的像素电极。

2. 发明授权

US07408200B2 Thin film transistor array panel and manufacturing method thereof 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07408200B2
公开(公告)日：2008-08-05
申请号：US11612141
申请日：2006-12-18
申请人： Sahng-Ik Jun , Jae-Hong Jeon , Kwon-Young Choi , Jeong-Young Lee
发明人： Sahng-Ik Jun , Jae-Hong Jeon , Kwon-Young Choi , Jeong-Young Lee
IPC分类号： H01L33/00
CPC分类号： H01L27/124 , H01L29/41733
摘要： A thin film transistor array panel is provided, which includes: a substrate; a first signal line formed on the substrate; a second signal line formed on the substrate and intersecting the first signal line; a thin film transistor including a gate electrode connected to the first signal line and having an edge substantially parallel to the first signal line, a source electrode connected to the second signal line, and a drain electrode overlapping the edge of the gate electrode; and a pixel electrode connected to the drain electrode.
摘要翻译：提供薄膜晶体管阵列面板，其包括：基板; 形成在所述基板上的第一信号线; 形成在所述基板上并与所述第一信号线相交的第二信号线; 薄膜晶体管，包括连接到第一信号线的栅极，并且具有基本上平行于第一信号线的边缘，连接到第二信号线的源电极和与栅电极的边缘重叠的漏电极; 以及连接到漏电极的像素电极。

3. 发明申请

US20080090404A1 CONTACT STRUCTURE OF A WIRES AND METHOD MANUFACTURING THE SAME, AND THIN FILM TRANSISTOR SUBSTRATE INCLUDING THE CONTACT STRUCTURE AND METHOD MANUFACTURING THE SAME 审中-公开
标题翻译：一种线的接触结构及其制造方法，以及包括接触结构的薄膜晶体管基板及其制造方法
公开(公告)号：US20080090404A1
公开(公告)日：2008-04-17
申请号：US11947204
申请日：2007-11-29
申请人： Seung-Taek Lim , Mun-Pyo Hong , Nam-Seok Roh , Young-Joo Song , Sang-Ki Kwak , Kwon-Young Choi , Keun-kyu Song
发明人： Seung-Taek Lim , Mun-Pyo Hong , Nam-Seok Roh , Young-Joo Song , Sang-Ki Kwak , Kwon-Young Choi , Keun-kyu Song
IPC分类号： H01L21/4763
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , G02F2001/13629 , H01L21/76805 , H01L21/76816 , H01L23/53223 , H01L27/124 , H01L2924/0002 , H01L2924/00
摘要： In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes, and gate pads. A gate insulating layer is deposited onto the insulating substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. A data line assembly is formed on the ohmic contact layer with a chrome-based under-layer and an aluminum alloy-based over-layer. The data line assembly has data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads. The sidewall of the under-layers for the gate line assembly and the data line assembly is exposed through the contact holes. An IZO-based layer is deposited onto the substrate, and patterned to thereby form pixel electrodes, subsidiary gate pads, and subsidiary data pads. The pixel electrodes are connected to the sidewall of the drain electrodes, and the subsidiary gate and data pads are connected to the sidewall of the gate and the data pads.
摘要翻译：在制造用于液晶显示器的薄膜晶体管阵列基板的方法中，栅极线组件在沿水平方向前进的基底上形成有铬基底层和基于铝合金的超层。栅极线组件具有栅极线，栅电极和栅极焊盘。栅极绝缘层沉积在绝缘基板上，使得栅极绝缘层覆盖栅极线组件。在栅极绝缘层上依次形成半导体层和欧姆接触层。数据线组件在欧姆接触层上形成有铬基底层和基于铝合金的超层。数据线组件具有跨越栅极线，源电极，漏电极和数据焊盘的数据线。保护层沉积到衬底上，并被图案化，从而形成露出漏电极，栅极焊盘和数据焊盘的接触孔。用于栅极线组件和数据线组件的下层的侧壁通过接触孔暴露。将基于IZO的层沉积到衬底上并构图，从而形成像素电极，辅助栅极焊盘和辅助数据焊盘。像素电极连接到漏电极的侧壁，辅助栅极和数据焊盘连接到栅极和数据焊盘的侧壁。

4. 发明申请

US20070091220A1 THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF 有权
标题翻译：薄膜晶体管阵列及其制造方法
公开(公告)号：US20070091220A1
公开(公告)日：2007-04-26
申请号：US11612141
申请日：2006-12-18
申请人： Sahng-Ik Jun , Jae-Hong Jeon , Kwon-Young Choi , Jeong-Young Lee
发明人： Sahng-Ik Jun , Jae-Hong Jeon , Kwon-Young Choi , Jeong-Young Lee
IPC分类号： G02F1/136 , G02F1/1343
CPC分类号： H01L27/124 , H01L29/41733
摘要： A thin film transistor array panel is provided, which includes: a substrate; a first signal line formed on the substrate; a second signal line formed on the substrate and intersecting the first signal line; a thin film transistor including a gate electrode connected to the first signal line and having an edge substantially parallel to the first signal line, a source electrode connected to the second signal line, and a drain electrode overlapping the edge of the gate electrode; and a pixel electrode connected to the drain electrode.
摘要翻译：提供薄膜晶体管阵列面板，其包括：基板; 形成在所述基板上的第一信号线; 形成在所述基板上并与所述第一信号线相交的第二信号线; 薄膜晶体管，包括连接到第一信号线的栅极，并且具有基本上平行于第一信号线的边缘，连接到第二信号线的源电极和与栅电极的边缘重叠的漏电极; 以及连接到漏电极的像素电极。

5. 发明申请

US20050082535A1 Thin film transistor array panel and manufacturing method thereof 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US20050082535A1
公开(公告)日：2005-04-21
申请号：US10926719
申请日：2004-08-26
申请人： Min-Wook Park , Sang-Jin Jeon , Jung-Joon Park , Jeong-Young Lee , Bum-Ki Baek , Se-Hwan Yu , Sang-Ki Kwak , Han-Ju Lee , Kwon-Young Choi
发明人： Min-Wook Park , Sang-Jin Jeon , Jung-Joon Park , Jeong-Young Lee , Bum-Ki Baek , Se-Hwan Yu , Sang-Ki Kwak , Han-Ju Lee , Kwon-Young Choi
IPC分类号： G02F1/136 , G02F1/133 , G02F1/1339 , G02F1/1368 , G03C1/85 , G03C5/00 , G09F9/30 , H01L21/00 , H01L21/336 , H01L29/786
CPC分类号： G02F1/1368 , G02F1/1339
摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.
摘要翻译：提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在下导电膜的第一和第二部分上形成像素电极和一对冗余电极，所述冗余电极暴露下导电膜的第二部分的一部分; 去除下导电膜的第二部分的暴露部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

6. 发明申请

US20110033904A1 METHOD FOR PREPARING ORTHODIHYDROXYISOFLAVONES USING A BIOTRANSFORMATION SYSTEM 审中-公开
标题翻译：使用生物传感系统制备异硫氰酸盐的方法
公开(公告)号：US20110033904A1
公开(公告)日：2011-02-10
申请号：US12937876
申请日：2008-04-25
申请人： Jun Seong Park , Hye Yoon Park , Ho Sik Rho , Duck Hee Kim , Ih Seop Chang , Byung Gee Kim , Chang Hyun Roh , Su Hyun Seo , Kwon Young Choi , June Hyung Kim , Min-Ho Cha , Prasad Pandey Bishnu
发明人： Jun Seong Park , Hye Yoon Park , Ho Sik Rho , Duck Hee Kim , Ih Seop Chang , Byung Gee Kim , Chang Hyun Roh , Su Hyun Seo , Kwon Young Choi , June Hyung Kim , Min-Ho Cha , Prasad Pandey Bishnu
IPC分类号： C12P17/06
CPC分类号： C12P17/06 , C12N1/20
摘要： Disclosed herein is a method for preparing ortho-dihydroxyisoflavones using a biotransformation system. More specifically, disclosed is a method for preparing ortho-dihydroxyisoflavones, which comprises biotransforming daidzein or genistein by actinomycete microorganisms, particularly Streptomyces avermitilis, Nocardia farcinica or Streptomyces lincolnesis, in order to efficiently prepare ortho-dihydroxyisoflavones having an excellent antioxidant function and a whitening effect.
摘要翻译：本文公开了使用生物转化体系制备邻二羟基异黄酮的方法。更具体地，公开了一种制备邻二羟基异黄酮的方法，其包括通过放线菌微生物，特别是阿维链霉素（Streptomyces avermitilis），诺卡氏菌（Nocardia farcinica）或林链霉菌（Streptomyces lincolnesis））生物转化黄豆苷原或染料木黄酮，以有效制备具有优异抗氧化功能和增白效果的邻二羟基异黄酮。

7. 发明授权

US07742118B2 Thin film transistor array panel and manufacturing method thereof 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07742118B2
公开(公告)日：2010-06-22
申请号：US11690563
申请日：2007-03-23
申请人： Jun-Hyung Souk , Jeong-Young Lee , Jong-Soo Yoon , Kwon-Young Choi , Bum-Ki Baek
发明人： Jun-Hyung Souk , Jeong-Young Lee , Jong-Soo Yoon , Kwon-Young Choi , Bum-Ki Baek
IPC分类号： G02F1/136
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , H01L27/12 , H01L27/124 , H01L27/1288
摘要： A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.
摘要翻译：提供一种制造薄膜晶体管阵列面板的方法，该方法包括：在绝缘基板上形成栅极线; 形成栅极绝缘层; 形成半导体层; 形成包括数据线和漏电极的数据导电层; 沉积钝化层; 形成包括位于所述栅极线的端部的第一部分的光致抗蚀剂，比所述第一部分更厚且位于所述漏极上的第二部分，以及比所述第二部分更厚的第三部分; 通过使用光致抗蚀剂作为蚀刻掩模，将光致抗蚀剂的第二部分下的钝化层的一部分暴露在光致抗蚀剂的第一部分下方的栅绝缘层的一部分; 形成分别露出所述漏电极和所述栅极线的端部的第一和第二接触孔; 以及通过所述第一接触孔形成连接到所述漏电极的像素电极。

8. 发明申请

US20100096176A1 CONTACT STRUCTURE OF A WIRES AND METHOD MANUFACTURING THE SAME, AND THIN FILM TRANSISTOR SUBSTRATE INCLUDING THE CONTACT STRUCTURE AND METHOD MANUFACTURING THE SAME 审中-公开
标题翻译：一种线的接触结构及其制造方法，以及包括接触结构的薄膜晶体管基板及其制造方法
公开(公告)号：US20100096176A1
公开(公告)日：2010-04-22
申请号：US12645458
申请日：2009-12-22
申请人： Seung-Taek LIM , Mun-Pyo Hong , Nam-Seok Roh , Young-Joo Song , Sang-Ki Kwak , Kwon-Young Choi , Keun-Kyu Song
发明人： Seung-Taek LIM , Mun-Pyo Hong , Nam-Seok Roh , Young-Joo Song , Sang-Ki Kwak , Kwon-Young Choi , Keun-Kyu Song
IPC分类号： H05K1/11
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , G02F2001/13629 , H01L21/76805 , H01L21/76816 , H01L23/53223 , H01L27/124 , H01L2924/0002 , H01L2924/00
摘要： In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes, and gate pads. A gate insulating layer is deposited onto the insulating substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. A data line assembly is formed on the ohmic contact layer with a chrome-based under-layer and an aluminum alloy-based over-layer. The data line assembly has data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads. The sidewall of the under-layers for the gate line assembly and the data line assembly is exposed through the contact holes. An IZO-based layer is deposited onto the substrate, and patterned to thereby form pixel electrodes, subsidiary gate pads, and subsidiary data pads. The pixel electrodes are connected to the sidewall of the drain electrodes, and the subsidiary gate and data pads are connected to the sidewall of the gate and the data pads.
摘要翻译：在制造用于液晶显示器的薄膜晶体管阵列基板的方法中，栅极线组件在沿水平方向前进的基底上形成有铬基底层和基于铝合金的超层。栅极线组件具有栅极线，栅电极和栅极焊盘。栅极绝缘层沉积在绝缘基板上，使得栅极绝缘层覆盖栅极线组件。在栅极绝缘层上依次形成半导体层和欧姆接触层。数据线组件在欧姆接触层上形成有铬基底层和基于铝合金的超层。数据线组件具有跨越栅极线，源电极，漏电极和数据焊盘的数据线。保护层沉积到衬底上，并被图案化，从而形成露出漏电极，栅极焊盘和数据焊盘的接触孔。用于栅极线组件和数据线组件的下层的侧壁通过接触孔暴露。将基于IZO的层沉积到衬底上并构图，从而形成像素电极，辅助栅极焊盘和辅助数据焊盘。像素电极连接到漏电极的侧壁，辅助栅极和数据焊盘连接到栅极和数据焊盘的侧壁。

9. 发明申请

US20090096105A1 CONTACT STRUCTURE OF A WIRES AND METHOD MANUFACTURING THE SAME, AND THIN FILM TRANSISTOR SUBSTRATE INCLUDING THE CONTACT STRUCTURE AND METHOD MANUFACTURING THE SAME 有权
标题翻译：一种线的接触结构及其制造方法，以及包括接触结构的薄膜晶体管基板及其制造方法
公开(公告)号：US20090096105A1
公开(公告)日：2009-04-16
申请号：US12333973
申请日：2008-12-12
申请人： Seung-Taek LIM , Mun-Pyo Hong , Nam-Seok Roh , Young-Joo Song , Sang-Ki Kwak , Kwon-Young Choi , Keun-Kyu Song
发明人： Seung-Taek LIM , Mun-Pyo Hong , Nam-Seok Roh , Young-Joo Song , Sang-Ki Kwak , Kwon-Young Choi , Keun-Kyu Song
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , G02F2001/13629 , H01L21/76805 , H01L21/76816 , H01L23/53223 , H01L27/124 , H01L2924/0002 , H01L2924/00
摘要： In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes, and gate pads. A gate insulating layer is deposited onto the insulating substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. A data line assembly is formed on the ohmic contact layer with a chrome-based under-layer and an aluminum alloy-based over-layer. The data line assembly has data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads. The sidewall of the under-layers for the gate line assembly and the data line assembly is exposed through the contact holes. An IZO-based layer is deposited onto the substrate, and patterned to thereby form pixel electrodes, subsidiary gate pads, and subsidiary data pads. The pixel electrodes are connected to the sidewall of the drain electrodes, and the subsidiary gate and data pads are connected to the sidewall of the gate and the data pads.
摘要翻译：在制造用于液晶显示器的薄膜晶体管阵列基板的方法中，栅极线组件在沿水平方向前进的基底上形成有铬基底层和基于铝合金的超层。栅极线组件具有栅极线，栅电极和栅极焊盘。栅极绝缘层沉积在绝缘基板上，使得栅极绝缘层覆盖栅极线组件。在栅极绝缘层上依次形成半导体层和欧姆接触层。数据线组件在欧姆接触层上形成有铬基底层和基于铝合金的超层。数据线组件具有跨越栅极线，源电极，漏电极和数据焊盘的数据线。保护层沉积到衬底上，并被图案化，从而形成露出漏电极，栅极焊盘和数据焊盘的接触孔。用于栅极线组件和数据线组件的下层的侧壁通过接触孔暴露。将基于IZO的层沉积到衬底上并构图，从而形成像素电极，辅助栅极焊盘和辅助数据焊盘。像素电极连接到漏电极的侧壁，辅助栅极和数据焊盘连接到栅极和数据焊盘的侧壁。

10. 发明申请

US20080252806A1 THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF 有权
标题翻译：薄膜晶体管阵列及其制造方法
公开(公告)号：US20080252806A1
公开(公告)日：2008-10-16
申请号：US12141623
申请日：2008-06-18
申请人： Jun-Hyung SOUK , Jeong-Young Lee , Jong-Soo Yoon , Kwon-Young Choi , Bum-Ki Baek
发明人： Jun-Hyung SOUK , Jeong-Young Lee , Jong-Soo Yoon , Kwon-Young Choi , Bum-Ki Baek
IPC分类号： G02F1/136
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , H01L27/12 , H01L27/124 , H01L27/1288
摘要： A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.
摘要翻译：提供一种制造薄膜晶体管阵列面板的方法，该方法包括：在绝缘基板上形成栅极线; 形成栅极绝缘层; 形成半导体层; 形成包括数据线和漏电极的数据导电层; 沉积钝化层; 形成包括位于所述栅极线的端部的第一部分的光致抗蚀剂，比所述第一部分更厚且位于所述漏极上的第二部分，以及比所述第二部分更厚的第三部分; 通过使用光致抗蚀剂作为蚀刻掩模，将光致抗蚀剂的第二部分下的钝化层的一部分暴露在光致抗蚀剂的第一部分下方的栅绝缘层的一部分; 形成分别露出所述漏电极和所述栅极线的端部的第一和第二接触孔; 以及通过所述第一接触孔形成连接到所述漏电极的像素电极。

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