专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07155006B2 Method and apparatus for outbound wave subtraction using a variable offset amplifier 失效
公开(公告)号：US07155006B2
公开(公告)日：2006-12-26
申请号：US09960821
申请日：2001-09-21
申请人： Bryan K. Casper , Stephen R. Mooney , Aaron K. Martin
发明人： Bryan K. Casper , Stephen R. Mooney , Aaron K. Martin
IPC分类号： H04M1/00 , H04M9/00
CPC分类号： H04B3/03 , H04L25/063
摘要： A method and apparatus for outbound wave subtraction using a variable offset amplifier is described. The method includes calibration of a bi-directional signaling circuit in order to calculate one or more offset codes for cancellation of an outbound wave within a bi-directional communications link. Once the one or more offset codes are calculated, it is determined whether a dual inbound wave is received by the bi-directional signaling circuit. Once received, an offset code from the one or more calculated offset codes is selected according to a value of an outbound wave within the dual inbound/outbound wave. Finally, the outbound wave is cancelled from the dual inbound wave at an output of a variable offset amplifier using the selected offset code.

2. 发明授权

US06608582B2 A/D conversion using a variable offset comparator 有权
标题翻译：使用可变偏移比较器进行A / D转换
公开(公告)号：US06608582B2
公开(公告)日：2003-08-19
申请号：US10037751
申请日：2002-01-02
申请人： Bryan K. Casper , Aaron K. Martin
发明人： Bryan K. Casper , Aaron K. Martin
IPC分类号： H03M112
CPC分类号： H03F3/45183 , H03F3/45672 , H03F2203/45371 , H03M1/1033 , H03M1/46
摘要： An A/D conversion reference level is applied to an input of a variable offset comparator (i.e. VOC). A binary number that corresponds to the A/D conversion reference level is determined by changing a binary variable that is applied to vary the offset of the VOC until the VOC output changes states. The same procedure is applied to determine corresponding reference, binary numbers for all of the other A/D conversion reference levels. A successive approximation procedure (binary search) is then performed for a reference window in which an input analog level (to be converted into digital form) would fall, by successively applying the reference binary numbers to vary the VOC offset.
摘要翻译： A / D转换参考电平被施加到可变偏移比较器（即VOC）的输入端。通过改变应用于改变VOC的偏移量的二进制变量直到VOC输出改变状态来确定对应于A / D转换参考电平的二进制数。应用相同的程序确定所有其他A / D转换参考电平的相应参考二进制数。然后，通过连续地应用参考二进制数来改变VOC偏移量，对其中输入模拟电平（待转换成数字形式）的参考窗口执行逐次逼近程序（二进制搜索）。

3. 发明授权

US07301391B2 Filtering variable offset amplifier 有权
标题翻译：滤波可变失调放大器
公开(公告)号：US07301391B2
公开(公告)日：2007-11-27
申请号：US11181380
申请日：2005-07-14
申请人： James E. Jaussi , Bryan K. Casper , Aaron K. Martin
发明人： James E. Jaussi , Bryan K. Casper , Aaron K. Martin
IPC分类号： H03F3/45 , H03K5/22
CPC分类号： G06G7/16 , H03H11/1213
摘要： A current summing FIR filter can be implemented with multiple differential input stages and variable tail currents. The variable tail currents can be used to appropriately weight the present and previous digital input signals. The weighted outputs of the differential transistor pairs can be summed to provide a filtered output signal. The tail currents can be advantageously varied with variable current sources or by adjustment of the relative widths of the differential transistor pairs. In other embodiments, additional differential pairs can be added to adjust for systematic offset voltages caused by process-induced variations in the structure of circuit devices or to induce a desired offset.
摘要翻译：可以用多个差分输入级和可变尾电流来实现电流求和FIR滤波器。可变尾电流可用于适当地加权当前和以前的数字输入信号。可以将差分晶体管对的加权输出相加以提供经滤波的输出信号。可以利用可变电流源或通过调整差分晶体管对的相对宽度来有利地改变尾电流。在其他实施例中，可以添加额外的差分对以调整由电路装置的结构中的过程引起的变化引起的系统偏移电压或引起期望的偏移。

4. 发明授权

US07190931B2 Receiver calibration apparatus, method, and system 有权
标题翻译：接收机校准装置，方法和系统
公开(公告)号：US07190931B2
公开(公告)日：2007-03-13
申请号：US10674175
申请日：2003-09-29
申请人： Bryan K. Casper , Aaron K. Martin , James E. Jaussi , Stephen R. Mooney
发明人： Bryan K. Casper , Aaron K. Martin , James E. Jaussi , Stephen R. Mooney
IPC分类号： H04B17/00
CPC分类号： H04B17/21
摘要： A receiver is calibrated using a transmitter that can output a plurality of substantially constant amplitude signals.
摘要翻译：使用可以输出多个基本上恒定的振幅信号的发射机校准接收机。

5. 发明授权

US07177288B2 Simultaneous transmission and reception of signals in different frequency bands over a bus line 有权
标题翻译：在总线上同时发送和接收不同频段的信号
公开(公告)号：US07177288B2
公开(公告)日：2007-02-13
申请号：US09998008
申请日：2001-11-28
申请人： Stephen R. Mooney , Aaron K. Martin , Matthew B. Haycock , Bryan K. Casper , Shekhar Y. Borkar , Joseph T. Kennedy , James E. Jaussi
发明人： Stephen R. Mooney , Aaron K. Martin , Matthew B. Haycock , Bryan K. Casper , Shekhar Y. Borkar , Joseph T. Kennedy , James E. Jaussi
IPC分类号： H04L5/14
CPC分类号： H04L5/1423
摘要： A device includes a bus, a first transmitter connected to the bus and configured to transmit a first signal over the bus in a first frequency band, a second transmitter connected to the bus and configured to transmit a second signal over the bus in a second frequency band at the same time that the first transmitter is transmitting the first signal, a first receiver connected to the bus and configured to receive the first signal transmitted over the bus in the first frequency band, and a second receiver connected to the bus and configured to receive the second signal transmitted over the bus in the second frequency band. The first frequency band and the second frequency band occupy different portions of the frequency spectrum.
摘要翻译：一种设备包括总线，连接到总线的第一发射机，并且被配置为在第一频带中通过总线传输第一信号，第二发射器连接到总线并且被配置为以第二频率通过总线发送第二信号与第一发射机正在发送第一信号的同时，连接到总线并被配置为接收通过总线在第一频带中发送的第一信号的第一接收机和连接到总线的第二接收机，并且被配置为接收在第二频带中通过总线发送的第二信号。第一频带和第二频带占据频谱的不同部分。

6. 发明授权

US06774686B2 Method for minimizing jitter using matched, controlled-delay elements slaved to a closed-loop timing reference 有权
标题翻译：使用从动到闭环定时参考的匹配的受控延迟元件来最小化抖动的方法
公开(公告)号：US06774686B2
公开(公告)日：2004-08-10
申请号：US09968460
申请日：2001-09-28
申请人： Joseph T. Kennedy , Bryan K. Casper , Stephen R. Mooney , Aaron K. Martin
发明人： Joseph T. Kennedy , Bryan K. Casper , Stephen R. Mooney , Aaron K. Martin
IPC分类号： H03L706
CPC分类号： H03L7/0805 , H03L7/0812
摘要： A method for minimizing jitter using substantially matched, controlled, delay elements is disclosed. The method includes generating an internal loop-timing reference, and controlling elements outside of the loop with the internal loop-timing reference generated. In one embodiment the outside elements are substantially identical to those internal to the closed-loop. Controlled delay elements for preconditioning and distributing closed-loop inputs and outputs, using the same control reference used by internal loop elements are disclosed.
摘要翻译：公开了一种使用基本匹配的受控延迟元件来最小化抖动的方法。该方法包括生成内部循环定时参考，以及生成内部循环定时参考，控制环外的元素。在一个实施例中，外部元件与闭环内部元件基本相同。公开了用于预调节和分配闭环输入和输出的受控延迟元件，使用与内部环路元件相同的控制参考。

7. 发明授权

US06704818B1 Voltage-mode driver with pre-emphasis, slew-rate control and source termination 有权
标题翻译：具有预加重，转换速率控制和源终止的电压模式驱动器
公开(公告)号：US06704818B1
公开(公告)日：2004-03-09
申请号：US09752645
申请日：2000-12-29
申请人： Aaron K. Martin , Bryan K. Casper , Joseph T. Kennedy
发明人： Aaron K. Martin , Bryan K. Casper , Joseph T. Kennedy
IPC分类号： G06F1300
CPC分类号： H03K17/164 , H03K19/0005
摘要： The invention provides an apparatus, method, and means for maintaining a constant slew rate while providing pre-emphasis, to adapt a push-pull voltage driver to the interconnect that it is driving. In an aspect, the invention modifies a driver output voltage amplitude, providing a small swing out for low frequency signals, and a large swing out for high frequency signals, such that low frequency signals and high frequency signals reach a receiver with equal amplitude. In an aspect, a slew rate control, having a delay mixer, selects and individually transmits to individual segments of a driver leg, at a desired time, one of output data and a signal for a pre-emphasis version of output data. In an aspect, the invention maintains a matched direct current termination impedance to the characteristic impedance of a transmission line being driven.
摘要翻译：本发明提供了一种用于在提供预加重的同时保持恒定的转换速率以使推挽电压驱动器适应于其所驱动的互连的装置，方法和装置。在一方面，本发明修改驱动器输出电压幅度，为低频信号提供小的摆幅，并且对于高频信号进行大的摆动，使得低频信号和高频信号以相等的幅度到达接收机。在一方面，具有延迟混频器的转换速率控制在期望的时间选择和单独地发送驱动器支路的各个段，输出数据和输出数据的预加重版本的信号之一。在一方面，本发明保持与被驱动的传输线的特性阻抗匹配的直流端接阻抗。

8. 发明授权

US06639423B2 Current mode driver with variable termination 有权
标题翻译：具有可变终端的电流模式驱动器
公开(公告)号：US06639423B2
公开(公告)日：2003-10-28
申请号：US10096546
申请日：2002-03-12
申请人： Aaron K. Martin , Bryan K. Casper , Stephen R. Mooney
发明人： Aaron K. Martin , Bryan K. Casper , Stephen R. Mooney
IPC分类号： H03K1716
CPC分类号： H03K19/01759 , H03K19/0005
摘要： A simultaneous bidirectional port circuit includes a current mode output driver for driving an output node and a current mode return driver for driving a differential receiver. Variable impedance termination devices are included to provide terminations for both the current mode output driver and current mode return driver. A control circuit and method set the impedance value of the variable impedance termination devices by comparing voltage values at the output of the current mode output driver and current mode return driver.
摘要翻译：同时双向端口电路包括用于驱动输出节点的电流模式输出驱动器和用于驱动差分接收器的电流模式返回驱动器。包括可变阻抗端接装置，为电流模式输出驱动器和电流模式返回驱动器提供终端。控制电路和方法通过比较电流模式输出驱动器和电流模式返回驱动器的输出端的电压值来设定可变阻抗端接装置的阻抗值。

9. 发明授权

US06621323B1 Signal sampling circuits, systems, and methods 有权
标题翻译：信号采样电路，系统和方法
公开(公告)号：US06621323B1
公开(公告)日：2003-09-16
申请号：US10131443
申请日：2002-04-24
申请人： Bryan K. Casper , Aaron K. Martin , Stephen R. Mooney , James E. Jaussi
发明人： Bryan K. Casper , Aaron K. Martin , Stephen R. Mooney , James E. Jaussi
IPC分类号： H03K1730
CPC分类号： H04L25/0292 , G11C27/024 , H04L5/1423 , H04L25/0272 , H04L25/028
摘要： A circuit samples a voltage on a simultaneous bi-directional bus, and subtracts an outbound voltage to determine an inbound voltage. Sampling capacitors are variable to adjust for matching time constants. A mechanism is provided to sample error voltages over clock phase variations and sampling capacitor values.
摘要翻译：电路对同时双向总线上的电压进行采样，并减去出站电压以确定入站电压。采样电容是可变的，用于调整匹配的时间常数。提供了一种机制来对时钟相位变化和采样电容值进行误差电压的采样。

10. 发明授权

US07457393B2 Clock recovery apparatus, method, and system 有权
标题翻译：时钟恢复装置，方法和系统
公开(公告)号：US07457393B2
公开(公告)日：2008-11-25
申请号：US11025771
申请日：2004-12-29
申请人： Bryan K. Casper , Aaron K. Martin , Stephen R. Mooney , James E. Jaussi
发明人： Bryan K. Casper , Aaron K. Martin , Stephen R. Mooney , James E. Jaussi
IPC分类号： H03D3/24
CPC分类号： H03L7/07 , H03L7/0814 , H03L7/18 , H04L7/0008 , H04L7/0025 , H04L7/10
摘要： A global clock recovery circuit and port circuit determine and combine static phase adjustment information and dynamic phase adjustment information for multiple data signals. Static phase adjustment information is determined for each of the multiple data signals, and dynamic phase adjustment information is determined in common for the multiple data signals.
摘要翻译：全局时钟恢复电路和端口电路确定并组合多个数据信号的静态相位调整信息和动态相位调整信息。为多个数据信号中的每一个确定静态相位调整信息，并且为多个数据信号共同确定动态相位调整信息。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式