专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07177288B2 Simultaneous transmission and reception of signals in different frequency bands over a bus line 有权
标题翻译：在总线上同时发送和接收不同频段的信号
公开(公告)号：US07177288B2
公开(公告)日：2007-02-13
申请号：US09998008
申请日：2001-11-28
申请人： Stephen R. Mooney , Aaron K. Martin , Matthew B. Haycock , Bryan K. Casper , Shekhar Y. Borkar , Joseph T. Kennedy , James E. Jaussi
发明人： Stephen R. Mooney , Aaron K. Martin , Matthew B. Haycock , Bryan K. Casper , Shekhar Y. Borkar , Joseph T. Kennedy , James E. Jaussi
IPC分类号： H04L5/14
CPC分类号： H04L5/1423
摘要： A device includes a bus, a first transmitter connected to the bus and configured to transmit a first signal over the bus in a first frequency band, a second transmitter connected to the bus and configured to transmit a second signal over the bus in a second frequency band at the same time that the first transmitter is transmitting the first signal, a first receiver connected to the bus and configured to receive the first signal transmitted over the bus in the first frequency band, and a second receiver connected to the bus and configured to receive the second signal transmitted over the bus in the second frequency band. The first frequency band and the second frequency band occupy different portions of the frequency spectrum.
摘要翻译：一种设备包括总线，连接到总线的第一发射机，并且被配置为在第一频带中通过总线传输第一信号，第二发射器连接到总线并且被配置为以第二频率通过总线发送第二信号与第一发射机正在发送第一信号的同时，连接到总线并被配置为接收通过总线在第一频带中发送的第一信号的第一接收机和连接到总线的第二接收机，并且被配置为接收在第二频带中通过总线发送的第二信号。第一频带和第二频带占据频谱的不同部分。

2. 发明授权

US06774686B2 Method for minimizing jitter using matched, controlled-delay elements slaved to a closed-loop timing reference 有权
标题翻译：使用从动到闭环定时参考的匹配的受控延迟元件来最小化抖动的方法
公开(公告)号：US06774686B2
公开(公告)日：2004-08-10
申请号：US09968460
申请日：2001-09-28
申请人： Joseph T. Kennedy , Bryan K. Casper , Stephen R. Mooney , Aaron K. Martin
发明人： Joseph T. Kennedy , Bryan K. Casper , Stephen R. Mooney , Aaron K. Martin
IPC分类号： H03L706
CPC分类号： H03L7/0805 , H03L7/0812
摘要： A method for minimizing jitter using substantially matched, controlled, delay elements is disclosed. The method includes generating an internal loop-timing reference, and controlling elements outside of the loop with the internal loop-timing reference generated. In one embodiment the outside elements are substantially identical to those internal to the closed-loop. Controlled delay elements for preconditioning and distributing closed-loop inputs and outputs, using the same control reference used by internal loop elements are disclosed.
摘要翻译：公开了一种使用基本匹配的受控延迟元件来最小化抖动的方法。该方法包括生成内部循环定时参考，以及生成内部循环定时参考，控制环外的元素。在一个实施例中，外部元件与闭环内部元件基本相同。公开了用于预调节和分配闭环输入和输出的受控延迟元件，使用与内部环路元件相同的控制参考。

3. 发明申请

US20080181331A1 Pulse amplitude modulated system with reduced intersymbol interference 有权
公开(公告)号：US20080181331A1
公开(公告)日：2008-07-31
申请号：US12077987
申请日：2008-03-24
申请人： Bryan K. Casper , Shekhar Y. Borkar , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy , Matthew B. Haycock , James E. Jaussi
发明人： Bryan K. Casper , Shekhar Y. Borkar , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy , Matthew B. Haycock , James E. Jaussi
IPC分类号： H03K7/02 , H03D1/24 , H03K9/02 , H04L27/04
CPC分类号： H04L25/4917
摘要： A system and method for encoding and receiving data is provided. The data is encoded as a pulse amplitude modulated signal such that the amplitude signals do not transition from the highest signal level to the lowest signal level and do not transition from the lowest signal level to the highest signal level. The encoding and decoding is performed in some embodiments via a lookup table, and in further embodiments is designed to minimize the step between sequential pulse amplitude modulated symbols.

4. 发明授权

US07653165B2 Pulse amplitude modulated system with reduced intersymbol interference 有权
标题翻译：具有减少符号间干扰的脉冲幅度调制系统
公开(公告)号：US07653165B2
公开(公告)日：2010-01-26
申请号：US12077987
申请日：2008-03-24
申请人： Bryan K. Casper , Shekhar Y. Borkar , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy , Matthew B. Haycock , James E. Jaussi
发明人： Bryan K. Casper , Shekhar Y. Borkar , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy , Matthew B. Haycock , James E. Jaussi
IPC分类号： H03K7/02 , H04L25/34
CPC分类号： H04L25/4917
摘要： A system and method for encoding and receiving data is provided. The data is encoded as a pulse amplitude modulated signal such that the amplitude signals do not transition from the highest signal level to the lowest signal level and do not transition from the lowest signal level to the highest signal level. The encoding and decoding is performed in some embodiments via a lookup table, and in further embodiments is designed to minimize the step between sequential pulse amplitude modulated symbols.
摘要翻译：提供了一种用于编码和接收数据的系统和方法。数据被编码为脉冲幅度调制信号，使得振幅信号不从最高信号电平转换到最低信号电平，并且不从最低信号电平转换到最高信号电平。在一些实施例中，通过查找表执行编码和解码，并且在另外的实施例中设计为使顺序脉冲幅度调制符号之间的步长最小化。

5. 发明授权

US07391834B2 Pulse amplitude modulated system with reduced intersymbol interference 有权
标题翻译：具有减少符号间干扰的脉冲幅度调制系统
公开(公告)号：US07391834B2
公开(公告)日：2008-06-24
申请号：US10261574
申请日：2002-10-01
申请人： Bryan K. Casper , Shekhar Y. Borkar , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy , Matthew B. Haycock , James E. Jaussi
发明人： Bryan K. Casper , Shekhar Y. Borkar , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy , Matthew B. Haycock , James E. Jaussi
IPC分类号： H03K7/02 , H04L25/34
CPC分类号： H04L25/4917
摘要： A system and method for encoding and receiving data is provided. The data is encoded as a pulse amplitude modulated signal such that the amplitude signals do not transition from the highest signal level to the lowest signal level and do not transition from the lowest signal level to the highest signal level. The encoding and decoding is performed in some embodiments via a lookup table, and in further embodiments is designed to minimize the step between sequential pulse amplitude modulated symbols.
摘要翻译：提供了一种用于编码和接收数据的系统和方法。数据被编码为脉冲幅度调制信号，使得振幅信号不从最高信号电平转换到最低信号电平，并且不从最低信号电平转换到最高信号电平。在一些实施例中，通过查找表执行编码和解码，并且在另外的实施例中设计为使顺序脉冲幅度调制符号之间的步长最小化。

6. 发明授权

US07120838B2 Method and unit for deskewing signals 有权
公开(公告)号：US07120838B2
公开(公告)日：2006-10-10
申请号：US10106636
申请日：2002-03-26
申请人： Bryan K. Casper , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy , Matthew B. Haycock
发明人： Bryan K. Casper , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy , Matthew B. Haycock
IPC分类号： G11B5/00 , G11B20/00 , G06K5/04
CPC分类号： G11B20/1403 , G11B20/20 , H03L7/0814 , H03L7/091 , H03L7/093 , H04L7/0008 , H04L7/0037
摘要： A clock deskew method includes receiving a data signal and a clock signal, processing the data signal to generate a jitter characterization parameter, shifting the clock signal by about 90° from the jitter characterization parameter to generate a sampling clock signal, and sampling the data signal with the sampling clock signal to generate a deskewed data signal. A clock deskew unit includes a clock unit, a sampling unit, and a deskew unit. The deskew unit includes a jitter characterization unit that generates a jitter characterization parameter. The jitter characterization parameter establishes a phase location for aligning a clock signal. Shifting the clock signal by about 90° from the phase location of the jitter characterization parameter provides a location for sampling a data signal to generate a deskewed data signal.

7. 发明授权

US06894536B2 Low power NRZ interconnect for pulsed signaling 有权
标题翻译：用于脉冲信号的低功率NRZ互连
公开(公告)号：US06894536B2
公开(公告)日：2005-05-17
申请号：US10013165
申请日：2001-12-10
申请人： Aaron K. Martin , Bryan K. Casper , Shekhar Y. Borkar , Stephen R. Mooney , Joseph T. Kennedy , Matthew B. Haycock , James E. Jaussi
发明人： Aaron K. Martin , Bryan K. Casper , Shekhar Y. Borkar , Stephen R. Mooney , Joseph T. Kennedy , Matthew B. Haycock , James E. Jaussi
IPC分类号： H04L25/493 , H03K19/0175
CPC分类号： H04L25/493
摘要： A digital interconnect system transmits pulses across a differential transmission line in response to transitions in an input data signal.
摘要翻译：数字互连系统响应于输入数据信号中的转变，跨差分传输线传输脉冲。

8. 发明授权

US06845424B2 Memory pass-band signaling 有权
标题翻译：存储器通带信令
公开(公告)号：US06845424B2
公开(公告)日：2005-01-18
申请号：US10062034
申请日：2002-01-31
申请人： Bryan K. Casper , Shekhar Y. Borkar , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy , Matthew B. Haycock , James E. Jaussi
发明人： Bryan K. Casper , Shekhar Y. Borkar , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy , Matthew B. Haycock , James E. Jaussi
IPC分类号： G06F12/06 , G06F12/00
CPC分类号： G06F12/06
摘要： A memory system provides includes multiple memory devices or banks of memory devices that are assigned frequency pass-bands. Each memory device includes frequency translation circuitry to up-convert and down-convert data signals to and from the assigned frequency pass-band. Some embodiments include simultaneous bidirectional communications between memory devices and a controller by assigning multiple frequency pass-bands to each memory device or bank of memory devices. A memory system substrate is provided with bandpass filters between memory device footprints and other device footprints.
摘要翻译：存储器系统提供包括分配有频率通带的多个存储器件或存储器器件组。每个存储器件包括频率转换电路，用于将数据信号上变频和下转换到分配的频率通带。一些实施例包括通过将多个频率通带分配给每个存储器件或存储器组来同时在存储器件与控制器之间进行双向通信。存储器系统基板在存储器件占用面积和其它器件占用面积之间提供带通滤波器。

9. 发明授权

US06747490B1 Sampling pulse generation 有权
标题翻译：采样脉冲发生
公开(公告)号：US06747490B1
公开(公告)日：2004-06-08
申请号：US10328205
申请日：2002-12-23
申请人： James E. Jaussi , Bryan K. Casper , Joseph T. Kennedy , Stephen R. Mooney
发明人： James E. Jaussi , Bryan K. Casper , Joseph T. Kennedy , Stephen R. Mooney
IPC分类号： H03K3289
CPC分类号： H04L25/028 , H03K3/356139 , H03K3/35625 , H04L25/0272 , H04L25/0292
摘要： According to some embodiments, a circuit provides a first set of one or more flip-flops to receive a low-swing differential clock, and a second set of one or more flip-flops to receive the low-swing differential clock. One of the one or more flip-flops of the first set is to generate a first CMOS-level sampling pulse for each cycle of the low-swing differential clock, and wherein one of the one or more flip-flops of the second set is to generate a second CMOS-level sampling pulse for each cycle of the low-swing differential clock.
摘要翻译：根据一些实施例，电路提供第一组一个或多个触发器以接收低摆幅差分时钟，以及第二组一个或多个触发器来接收低摆幅差分时钟。第一组的一个或多个触发器中的一个是为低摆动差分时钟的每个周期产生第一CMOS电平采样脉冲，并且其中第二组的一个或多个触发器中的一个是以产生低回波差分时钟的每个周期的第二CMOS电平采样脉冲。

10. 发明授权

US06704818B1 Voltage-mode driver with pre-emphasis, slew-rate control and source termination 有权
标题翻译：具有预加重，转换速率控制和源终止的电压模式驱动器
公开(公告)号：US06704818B1
公开(公告)日：2004-03-09
申请号：US09752645
申请日：2000-12-29
申请人： Aaron K. Martin , Bryan K. Casper , Joseph T. Kennedy
发明人： Aaron K. Martin , Bryan K. Casper , Joseph T. Kennedy
IPC分类号： G06F1300
CPC分类号： H03K17/164 , H03K19/0005
摘要： The invention provides an apparatus, method, and means for maintaining a constant slew rate while providing pre-emphasis, to adapt a push-pull voltage driver to the interconnect that it is driving. In an aspect, the invention modifies a driver output voltage amplitude, providing a small swing out for low frequency signals, and a large swing out for high frequency signals, such that low frequency signals and high frequency signals reach a receiver with equal amplitude. In an aspect, a slew rate control, having a delay mixer, selects and individually transmits to individual segments of a driver leg, at a desired time, one of output data and a signal for a pre-emphasis version of output data. In an aspect, the invention maintains a matched direct current termination impedance to the characteristic impedance of a transmission line being driven.
摘要翻译：本发明提供了一种用于在提供预加重的同时保持恒定的转换速率以使推挽电压驱动器适应于其所驱动的互连的装置，方法和装置。在一方面，本发明修改驱动器输出电压幅度，为低频信号提供小的摆幅，并且对于高频信号进行大的摆动，使得低频信号和高频信号以相等的幅度到达接收机。在一方面，具有延迟混频器的转换速率控制在期望的时间选择和单独地发送驱动器支路的各个段，输出数据和输出数据的预加重版本的信号之一。在一方面，本发明保持与被驱动的传输线的特性阻抗匹配的直流端接阻抗。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式