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1. 发明授权

US5596664A Transmitter module for optical interconnections 失效
标题翻译：用于光互连的发射器模块
公开(公告)号：US5596664A
公开(公告)日：1997-01-21
申请号：US531244
申请日：1995-09-20
申请人： Bruno Bostica , Franco Delpiano , Luca Pesando
发明人： Bruno Bostica , Franco Delpiano , Luca Pesando
IPC分类号： G02B6/42 , H01S5/00 , H04B10/12 , H04B10/13 , H04B10/135 , H04B10/14 , G02B6/421
CPC分类号： G02B6/4236 , G02B6/4224 , G02B6/4238 , G02B6/4239
摘要： Transmitter module for optical interconnections, comprising a metal container housing an optical emitting device, an integrated circuit containing the driving circuit of the emitting device and an optical fibre extending outside the container, the emitting device being mounted on a metallic ground area realized on the integrated circuit. The cathode is electrically connected to the ground area and the anode is connected to a second metal area, connected with the output of the driving circuit. The module uses a type of assembly which minimises problems due to the length of the connecting wires, to parasitic effects and to the effects of signal reflections due to impedance mismatching. It also requires reduced power for its operation and it is provided with a structure facilitating dissipation.
摘要翻译：用于光学互连的发射器模块，包括容纳发光器件的金属容器，包含发射器件的驱动电路的集成电路和延伸到容器外部的光纤，该发射器件安装在集成的金属接地区域上电路。阴极电连接到接地区域，阳极连接到与驱动电路的输出端连接的第二金属区域。该模块使用一种类型的组件，其最小化由于连接线的长度，寄生效应和由于阻抗失配引起的信号反射的影响所引起的问题。它还需要降低功率的操作，并且其具有便于耗散的结构。

2. 发明授权

US5828246A Circuit in CMOS technology for high speed driving of optical sources 失效
标题翻译： CMOS技术中的电路用于高速驱动光源
公开(公告)号：US5828246A
公开(公告)日：1998-10-27
申请号：US815118
申请日：1997-03-11
申请人： Bruno Bostica , Marco Burzio , Paolo Pellegrino , Luca Pesando
发明人： Bruno Bostica , Marco Burzio , Paolo Pellegrino , Luca Pesando
IPC分类号： H01L27/092 , H01L21/8238 , H01S5/042 , H01S5/068 , H01S5/40 , H04B10/04 , H04B10/06 , H04B10/142 , H04B10/152 , H03K3/42
CPC分类号： H01S5/042 , H01S5/0427 , H01S5/4025
摘要： A circuit source has bias and modulation current generators for both p-type and n-type optical sources, and a pair of sources of control voltages for the bias and modulation current generators, which obtain pairs of control voltages from an adjustable driving current. An external signal allows selecting, by means of a control logic and CMOS gates, the generators required by the source. The circuit is made by using three pads of an integrated circuit, one for each control voltage source and the third comprising the current generators, the CMOS gates and the control logic.
摘要翻译：电路源具有用于p型和n型光源的偏置和调制电流发生器，以及用于偏置和调制电流发生器的一对控制电压源，其从可调节的驱动电流获得成对的控制电压。外部信号允许通过控制逻辑和CMOS门选择源所需的发生器。电路通过使用集成电路的三个焊盘制成，每个控制电压源一个，第三个包括电流发生器，CMOS栅极和控制逻辑。

3. 发明授权

US6067334A Device for and method of aligning in time digital signals, for example a clock signal and data stream 失效
标题翻译：时间数字信号对准的装置和方法，例如时钟信号和数据流
公开(公告)号：US6067334A
公开(公告)日：2000-05-23
申请号：US869936
申请日：1997-06-05
申请人： Bruno Bostica , Marco Burzio , Paolo Pellegrino
发明人： Bruno Bostica , Marco Burzio , Paolo Pellegrino
IPC分类号： G06F13/42 , H03K5/00 , H03K5/13 , H04L7/02 , H04L7/033 , H03D3/24 , H03L7/00
CPC分类号： H04L7/0338
摘要： A device and a method for aligning in time two essentially isochronous digital signals are provided, in which a plurality (2.sup.n) of replicas (CK1-CK4) of the first signal (CKIN), separated by a given phase difference, are generated and a number of said replicas (CK3, CK4) is subjected to sampling (4, 5) in correspondence with the rising edges of the second signal (DATA). As the result of the sampling, a combination of logic signals (SL0, SL1) is obtained which is representative of the phase relation existing between each of said replicas (CK1-CK4) and the second signal (DATA). The output signal (CKOUT) of the device, aligned with the second signal, corresponds to the one, among the replicas (CK1-CK4) of the first signal, which best reproduces the desired alignment condition.
摘要翻译：一种用于在时间上对准的装置和方法，提供两个基本上同步的数字信号，其中产生由给定相位差分开的第一信号（CKIN）的多个（2n）个复制品（CK1-CK4），并且产生一个对应于第二信号（DATA）的上升沿对所述副本（CK3，CK4）的数量进行采样（4,5）。作为采样的结果，获得表示存在于每个所述副本（CK1-CK4）和第二信号（DATA）之间的相位关系的逻辑信号（SL0，SL1）的组合。与第二信号对准的装置的输出信号（CKOUT）对应于第一信号的副本（CK1-CK4）中的一个，其最好地再现期望的对准条件。

4. 发明授权

US5450225A Optical switch for fast cell-switching network 失效
标题翻译：用于快速小区切换网络的光交换机
公开(公告)号：US5450225A
公开(公告)日：1995-09-12
申请号：US348770
申请日：1994-12-02
申请人： Bruno Bostica , Paola Cinato , Alfredo De Bosio
发明人： Bruno Bostica , Paola Cinato , Alfredo De Bosio
IPC分类号： H04Q3/52 , H04L12/56 , H04Q11/00 , H04Q11/04 , H04J14/08
CPC分类号： H04L49/104 , H04L49/1553 , H04Q11/0001 , H04Q11/0478 , H04Q11/0066
摘要： The optical switch for fast cell-switching networks comprises an optical interconnection network (CM) and an electrical control network (CT). In order to fully exploit optical component capabilities and to overcome the constraints imposed by operating speed limits of electronic components, each input (IN1 . . . INk) of the interconnection network (CM) is associated with units (PAC1 . . . PACk) forming aggregates of cells which are to follow a same path through the interconnection network and time-compressing the aggregates, and each output (OU1 . . . OUk) is associated with units (PAD1 . . . PADk) for the time expansion of the aggregates and separation of the aggregate cells.
摘要翻译：用于快速小区交换网络的光交换机包括光互连网（CM）和电控网（CT）。为了充分利用光学部件能力并克服电子部件的运行速度限制所施加的限制，互连网络（CM）的每个输入（IN1 ... INK）与形成的单元（PAC1 ... PACk）相关联要通过互连网络遵循相同路径并对聚合进行时间压缩的单元的聚合，并且每个输出（OU1 ... OUK）与用于聚合的时间扩展的单元（PAD1 ... PADk）相关联，并且聚集细胞的分离。

5. 发明授权

US4543653A Modular self-routing PCM switching network for distributed-control telephone exchange 失效
标题翻译：模块化自路由PCM交换网络用于分布式控制电话交换
公开(公告)号：US4543653A
公开(公告)日：1985-09-24
申请号：US506710
申请日：1983-06-22
申请人： Piero Belforte , Mario Bondonno , Bruno Bostica , Luciano Pilati
发明人： Piero Belforte , Mario Bondonno , Bruno Bostica , Luciano Pilati
IPC分类号： H04Q3/545 , H04Q11/04 , H04J3/12
CPC分类号： H04Q11/04
摘要： An automatic exchange of a telephone system comprises a PCM switching network with a plurality of cascaded stages for establishing temporal and spatial connections between incoming channels on input lines of the first stage and outgoing channels on output lines of the last stage in response to commands from external controllers dialoguing with internal controllers of the network. Pairs of switching matrices forming part of nonadjacent stages are combined ito modular switching units each provided with its own internal controller. Routing instructions are transmitted from an external controller to a first internal controller which selects a signal path through the matrices of its own switching unit and informs a second internal controller of that selection whereupon the latter extends the path through an adjoining switching unit, and so on until the connection is completed. Each matrix is provided with a data store which is asynchronously loadable from the associated internal controller with a routing instruction to be synchronously forwarded, in a special time slot dedicated to intercontroller dialoguing in a PCM group to which the instruction pertains, to the data store of a coacting matrix in the next stage for asynchronous retransmission to the controller thereof; each data store may be paired with a respective series/parallel converter coupling it to the associated matrix for serially loading that store in any PCM frame with the contents of the dedicated channels of concurrently arriving PCM groups and feeding stored instruction words in parallel to the output lines of the matrix during a predetermined time slot of each frame. The internal controllers also perform diagnostic operations by comparing bytes extracted from an established signal path at locations upstream and downstream of a matrix.
摘要翻译：电话系统的自动交换包括具有多个级联级的PCM交换网络，用于响应于来自外部的命令建立第一级输入线路上的输入信道和最后级输出线路上的输出信道之间的时间和空间连接控制器与网络的内部控制器对话。构成非相邻级的一部分的开关矩阵的对将其组合成各自具有其自己的内部控制器的模块化交换单元。路由指令从外部控制器发送到第一内部控制器，该第一内部控制器通过其自己的切换单元的矩阵来选择信号路径，并且向第二内部控制器通知该选择，然后通过相邻的切换单元延伸路径，等等直到连接完成。每个矩阵都具有一个数据存储器，该数据存储器在专用于指令所涉及的PCM组中的对应于控制器的特殊时隙中，与相关联的内部控制器异步地加载以便同步转发的路由指令，在下一级中用于异步重传到其控制器的协作矩阵; 每个数据存储器可以与将其耦合到相关矩阵的相应串联/并行转换器配对，用于将任何PCM帧中的存储串行加载到同时到达的PCM组的专用信道的内容，并将存储的指令字馈送到输出在每个帧的预定时隙期间矩阵的行。内部控制器还通过比较从矩阵上游和下游位置处建立的信号路径提取的字节来执行诊断操作。

6. 发明授权

US5526156A Device for the phase realignment of ATM cells optical ATM nodes 失效
标题翻译： ATM信元ATM ATM节点的相位重新调整的装置
公开(公告)号：US5526156A
公开(公告)日：1996-06-11
申请号：US404954
申请日：1995-03-16
申请人： Bruno Bostica , Paola Cinato , Libero Zucchelli
发明人： Bruno Bostica , Paola Cinato , Libero Zucchelli
IPC分类号： H04B10/02 , H04L7/00 , H04L7/04 , H04L12/56 , H04Q3/00 , H04J14/08
CPC分类号： H04L12/5601 , H04L49/3081 , H04L7/0075 , H04L2012/5674 , H04L7/0041 , H04L7/042
摘要： The device for the phase realignment of ATM cells in an optical ATM switching node is associated with each input line (Fe) of node and includes a circuit for recognizing the beginning of a cell, a circuit for evaluating the time shift between of a cell and a reference instant and for generating an error signal (ER) depending on the amount of time difference, and a delay line for compensating the time difference, driven by the error signal (ER). The time difference compensator means includes a logarithmic optical delay line that is connected upstream of the device for recognizing the beginning of a cell and for evaluating the amount of the time difference.
摘要翻译：用于光学ATM交换节点中的ATM信元的相位重新对准的装置与节点的每个输入线（Fe）相关联，并且包括用于识别小区开始的电路，用于评估小区和时隙之间的时移的电路参考时刻，用于根据时间差产生误差信号（ER），以及用于补偿由误差信号（ER）驱动的时间差的延迟线。时差补偿装置包括连接在装置的上游的对数光学延迟线，用于识别小区的开始并用于评估时间差的量。

7. 发明授权

US5307343A Basic element for the connection network of a fast packet switching node 失效
标题翻译：快速分组交换节点的连接网络的基本元素
公开(公告)号：US5307343A
公开(公告)日：1994-04-26
申请号：US859502
申请日：1992-07-29
申请人： Bruno Bostica , Antonella Daniele , Vinicio Vercellone
发明人： Bruno Bostica , Antonella Daniele , Vinicio Vercellone
IPC分类号： H04L12/54 , H04L12/70 , H04L12/933 , H04L12/947 , H04Q11/04
CPC分类号： H04L12/5601 , H04L49/108 , H04L49/256 , H04L2012/5674
摘要： A basic element for the interconnection network of a fast packet switching node, where a synchronization is made at bit input stream level, the cell beginning is identified and a stream conversion from the serial form to a word parallel form is performed. Cells are thus transformed in a completely parallel form and in the same form they are cyclically discharged in the subsequent cell time in a memory, where cells are written and read in a shared way on the basis of instructions given by a control unit, thus performing the switching function. The control unit is essentially based on the use of a content-addressed associative memory, where a fraction of the routing header and a code indicating the time sequence on which the cells are stored. Memory outgoing cells are reconverted from a completely parallel form to a form having the length of one word and therefore in a completely serial form at a bitrate equal to the input one.
摘要翻译： PCT No.PCT / EP90 / 02010 Sec。 371日期：1992年7月29日 102（e）日期1992年7月29日PCT 1990年11月27日PCT PCT。公开号WO91 / 08633 日期1991年6月13日。快速分组交换节点的互连网络的基本元素，其中在比特输入流级别进行同步，识别小区开始并从串行形式到字并行形式的流转换被执行。因此，单元以完全平行的形式并且以相同的形式被转换成在随后的单元格时间内在存储器中循环地放电，其中基于由控制单元给出的指令以共享的方式写入和读取单元，从而执行切换功能。控制单元基本上基于内容寻址关联存储器的使用，其中路由报头的一部分和指示存储单元的时间顺序的代码。存储器输出单元从完全并行形式转换为具有一个字长度的形式，因此以等于输入单位的比特率以完全串行形式。

8. 发明授权

US4545051A Switching unit for the transfer of digitized signals in PCM system 失效
标题翻译：用于PCM系统中数字化信号传输的切换单元
公开(公告)号：US4545051A
公开(公告)日：1985-10-01
申请号：US478467
申请日：1983-03-24
申请人： Piero Belforte , Bruno Bostica , Luciano Pilati , Amilcare Bovo , Luigi Canato
发明人： Piero Belforte , Bruno Bostica , Luciano Pilati , Amilcare Bovo , Luigi Canato
IPC分类号： H04Q3/52 , H04Q11/04 , H04Q11/00 , H04J3/02
CPC分类号： H04Q11/04
摘要： A switching unit for the selective transfer of bytes concurrently arriving in successive time slots over eight incoming signal paths to as many outgoing signal paths with intervening temporal and/or spatial transposition comprises a byte memory, loaded by way of a series/parallel converter and read out by way of a parallel/series converter, under the control of a routing memory dialoguing via a logic network with a microprocessor. The latter, through instructions sent to the logic network, may command the blocking of the readout from the byte memory onto an outgoing path during a given time slot, the insertion of a particular byte into such a time slot, or the transfer of selected bytes from either memory to the microprocessor itself. In particular, bytes from the first time slots of PCM frames arriving over selected signal paths can be so extracted from diagnostic purposes.
摘要翻译：用于选择性地传送八个输入信号路径到达连续时隙的字节的切换单元，其具有间隔时间和/或空间转置的尽可能多的输出信号路径，包括通过串/并转换器加载的字节存储器通过并行/串联转换器，在通过与微处理器的逻辑网络对话的路由存储器的控制下。后者通过发送到逻辑网络的指令可以在给定时隙期间命令将字节存储器中的读出阻塞到输出路径上，将特定字节插入到这样的时隙中，或者将所选字节的传送从任何一个存储器到微处理器本身。特别地，从诊断目的可以提取从所选信号路径到达的PCM帧的第一时隙的字节。

9. 发明授权

US4386425A Switching unit for the transfer of digitized signals in PCM system 失效
标题翻译：用于PCM系统中数字化信号传输的切换单元
公开(公告)号：US4386425A
公开(公告)日：1983-05-31
申请号：US262933
申请日：1981-05-12
申请人： Piero Belforte , Bruno Bostica , Luciano Pilati
发明人： Piero Belforte , Bruno Bostica , Luciano Pilati
IPC分类号： H04Q3/52 , H04Q11/04 , H04Q11/08
CPC分类号： H04Q11/08
摘要： A switching unit for the selective transfer of bytes concurrently arriving in successive time slots over eight incoming signal paths to as many outgoing signal paths with intervening temporal and/or spatial transposition comprises a byte memory loaded by way of a series/parallel converter and read out by way of a parallel/series converter; two 8.times.8 storage matrices may alternately serve as the two converters. A routing memory, connected via a logic network to a command unit such as a microprocessor, controls the transfer and may also block the readout from the byte memory under certain conditions, specifically during an initiation procedure or where the switching unit is one of several such units forming part of a larger switching or concentration structure. In response to particular instructions from the command unit, a single byte from an incoming path may be transferred to one or all of the outgoing paths.
摘要翻译：用于通过八个输入信号路径同时到达连续时隙的字节的选择性传送的切换单元包括具有中间时间和/或空间转置的尽可能多的输出信号路径，包括通过串/并转换器加载的字节存储器并读出通过并联/串联转换器; 两个8×8存储矩阵可以交替地用作两个转换器。通过逻辑网络连接到诸如微处理器的命令单元的路由存储器控制传输，并且还可以在特定条件下，特别是在启动过程期间或者在多个这样的开关单元之一中阻塞来自字节存储器的读出形成较大开关或浓度结构的一部分的单元。响应于来自命令单元的特定指令，来自输入路径的单个字节可以被传送到一个或所有输出路径。

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