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1. 发明授权

US5828246A Circuit in CMOS technology for high speed driving of optical sources 失效
标题翻译： CMOS技术中的电路用于高速驱动光源
公开(公告)号：US5828246A
公开(公告)日：1998-10-27
申请号：US815118
申请日：1997-03-11
申请人： Bruno Bostica , Marco Burzio , Paolo Pellegrino , Luca Pesando
发明人： Bruno Bostica , Marco Burzio , Paolo Pellegrino , Luca Pesando
IPC分类号： H01L27/092 , H01L21/8238 , H01S5/042 , H01S5/068 , H01S5/40 , H04B10/04 , H04B10/06 , H04B10/142 , H04B10/152 , H03K3/42
CPC分类号： H01S5/042 , H01S5/0427 , H01S5/4025
摘要： A circuit source has bias and modulation current generators for both p-type and n-type optical sources, and a pair of sources of control voltages for the bias and modulation current generators, which obtain pairs of control voltages from an adjustable driving current. An external signal allows selecting, by means of a control logic and CMOS gates, the generators required by the source. The circuit is made by using three pads of an integrated circuit, one for each control voltage source and the third comprising the current generators, the CMOS gates and the control logic.
摘要翻译：电路源具有用于p型和n型光源的偏置和调制电流发生器，以及用于偏置和调制电流发生器的一对控制电压源，其从可调节的驱动电流获得成对的控制电压。外部信号允许通过控制逻辑和CMOS门选择源所需的发生器。电路通过使用集成电路的三个焊盘制成，每个控制电压源一个，第三个包括电流发生器，CMOS栅极和控制逻辑。

2. 发明授权

US06259327B1 PLL having circuits for selecting optimum VCO input/output characteristics 有权
标题翻译： PLL具有用于选择最佳VCO输入/输出特性的电路
公开(公告)号：US06259327B1
公开(公告)日：2001-07-10
申请号：US09439959
申请日：1999-11-12
申请人： Emanuele Balistreri , Marco Burzio
发明人： Emanuele Balistreri , Marco Burzio
IPC分类号： H03L7099
CPC分类号： H03L7/0995 , H03L7/10
摘要： A phase locked loop circuit includes an input comparator (2) capable of generating a deviation signal which can be used for driving an oscillator (5) so as to generate an output signal (CLKOUT) locked to the input signal. The oscillator (5) can operate according to a plurality of characteristics under the control of a control circuit (8) including searching circuits arranged to carry out a first search phase by scanning the family of characteristics admitted for the operation of the oscillator (5) by bands of progressively reduced width, according to a general, dichotomic procedure. Upon completion of this first search phase, additional circuits of fine search are destined to identify the optimum operating point, compensating possible fluctuations of the characteristics.
摘要翻译：锁相环电路包括能够产生可用于驱动振荡器（5）的偏差信号的输入比较器（2），以产生锁定到输入信号的输出信号（CLKOUT）。振荡器（5）可以在控制电路（8）的控制下根据多个特性进行操作，所述控制电路（8）包括搜索电路，所述搜索电路被布置为通过扫描为所述振荡器（5）的操作而允许的特征族进行第一搜索阶段，根据一般的二分法程序逐渐减小的频带。在完成第一搜索阶段后，精细搜索的附加电路将注定要识别最佳工作点，以补偿特性的可能波动。

3. 发明授权

US6127896A Phase locked loop having control circuit for automatically operating VCO on an optimum input/output characteristic 有权
标题翻译：锁相环具有用于在最佳输入/输出特性上自动操作VCO的控制电路
公开(公告)号：US6127896A
公开(公告)日：2000-10-03
申请号：US156930
申请日：1998-09-18
申请人： Marco Burzio
发明人： Marco Burzio
IPC分类号： H03K5/26 , H03K3/027 , H03K3/03 , H03L7/093 , H03L7/099 , H03L7/10 , H04L7/033
CPC分类号： H03L7/099 , H03L7/10 , H04L7/033
摘要： A phase locked loop (1) including an oscillator (5), usually made as a voltage controlled oscillator (VCO), arranged to operate selectively according to different input/output characteristics. The circuit further includes a control circuit (81) for selectively controlling the operation of the oscillator (5) thereby making the oscillator (5) itself operate on one of an optimum characteristic selectively determined according to the operating conditions of the loop (1).
摘要翻译：通常设置为压控振荡器（VCO）的振荡器（5）的锁相环（1）被布置为根据不同的输入/输出特性选择性地工作。电路还包括用于选择性地控制振荡器（5）的操作的控制电路（81），从而使得振荡器（5）本身根据循环（1）的操作条件选择性地确定的最佳特性之一进行操作。

4. 发明授权

US06292039B1 Integrated circuit phase-locked loop charge pump 有权
标题翻译：集成电路锁相环电荷泵
公开(公告)号：US06292039B1
公开(公告)日：2001-09-18
申请号：US09597058
申请日：2000-06-20
申请人： Marco Burzio , Emanuele Balistreri
发明人： Marco Burzio , Emanuele Balistreri
IPC分类号： H03C706
CPC分类号： H03L7/0895
摘要： A charge pump (2) is supplied to reset in rated conditions the error signal of a phase-locked loop of the type whereby a phase detector (1) periodically supplies this pump (2) with a first and second impulse having emission instants dependent on the phase ratio between phase-locked loop input signals and are allocated to control circuit output increase or decrease respectively by means of ring filter (3a, 3b). The pump features loops (21, 22, 23, 24, 28) to transform the first and second impulse into a first and second voltage signal of longer duration than maximum impulse duration and featuring values the difference of which depends on the phase ratio between the loop input signals and to generate a signal in a current representative of such difference.
摘要翻译：提供电荷泵（2）以在额定条件下复位该类型的锁相环的误差信号，由此相位检测器（1）周期性地向该泵（2）供应具有依赖于发射时间的发射瞬间的第一和第二脉冲分别通过环形滤波器（3a，3b）将锁相环输入信号之间的相位比分配给控制电路输出增加或减小。泵具有环路（21,22,23,24,28），以将第一和第二脉冲变换成比最大脉冲持续时间更长的持续时间的第一和第二电压信号，其特征在于其差值取决于并产生代表这种差异的电流中的信号。

5. 发明授权

US06218886B1 Device for compensating process and operating parameter variations in CMOS integrated circuits 失效
标题翻译：用于补偿CMOS集成电路中的工艺和工作参数变化的器件
公开(公告)号：US06218886B1
公开(公告)日：2001-04-17
申请号：US09452643
申请日：1999-12-01
申请人： Emanuele Balistreri , Marco Burzio
发明人： Emanuele Balistreri , Marco Burzio
IPC分类号： H03K1714
CPC分类号： H03K19/00384 , G05F3/245 , H01L27/0211
摘要： A device (DC) is provided for compensating process and operating parameters variations in a CMOS integrated circuit. The device comprises means (CP, CT) for generating a first and a second compensation signals which depend on quality indexes of the fabrication process of the P and N transistors of the integrated circuit and on the operating temperature, and which are capable of compensating deviations of the controlled quantity from the desired value, due to the deviation of the quality indexes and temperature, respectively, from a typical value which would originate the desired value for the output parameter. The compensating device also can be implemented in the form of CMOS integrated circuit, preferably jointly with the device (OS) to be subjected to compensation (FIG. 1).
摘要翻译：提供了一种用于补偿CMOS集成电路中的工艺和工作参数变化的器件（DC）。该装置包括用于产生取决于集成电路的P和N晶体管的制造工艺的质量指标和操作温度的第一和第二补偿信号的装置（CP，CT），并且能够补偿偏差由于质量指标和温度的偏差分别来自于产生输出参数的期望值的典型值，所需控制量来自期望值。补偿装置还可以以CMOS集成电路的形式实现，优选地与要进行补偿的装置（OS）共同实施（图1）。

6. 发明授权

US6067334A Device for and method of aligning in time digital signals, for example a clock signal and data stream 失效
标题翻译：时间数字信号对准的装置和方法，例如时钟信号和数据流
公开(公告)号：US6067334A
公开(公告)日：2000-05-23
申请号：US869936
申请日：1997-06-05
申请人： Bruno Bostica , Marco Burzio , Paolo Pellegrino
发明人： Bruno Bostica , Marco Burzio , Paolo Pellegrino
IPC分类号： G06F13/42 , H03K5/00 , H03K5/13 , H04L7/02 , H04L7/033 , H03D3/24 , H03L7/00
CPC分类号： H04L7/0338
摘要： A device and a method for aligning in time two essentially isochronous digital signals are provided, in which a plurality (2.sup.n) of replicas (CK1-CK4) of the first signal (CKIN), separated by a given phase difference, are generated and a number of said replicas (CK3, CK4) is subjected to sampling (4, 5) in correspondence with the rising edges of the second signal (DATA). As the result of the sampling, a combination of logic signals (SL0, SL1) is obtained which is representative of the phase relation existing between each of said replicas (CK1-CK4) and the second signal (DATA). The output signal (CKOUT) of the device, aligned with the second signal, corresponds to the one, among the replicas (CK1-CK4) of the first signal, which best reproduces the desired alignment condition.
摘要翻译：一种用于在时间上对准的装置和方法，提供两个基本上同步的数字信号，其中产生由给定相位差分开的第一信号（CKIN）的多个（2n）个复制品（CK1-CK4），并且产生一个对应于第二信号（DATA）的上升沿对所述副本（CK3，CK4）的数量进行采样（4,5）。作为采样的结果，获得表示存在于每个所述副本（CK1-CK4）和第二信号（DATA）之间的相位关系的逻辑信号（SL0，SL1）的组合。与第二信号对准的装置的输出信号（CKOUT）对应于第一信号的副本（CK1-CK4）中的一个，其最好地再现期望的对准条件。

7. 发明授权

US5790058A Serializing-parallelizing circuit for high speed digital signals 失效
标题翻译：用于高速数字信号的串行化并行电路
公开(公告)号：US5790058A
公开(公告)日：1998-08-04
申请号：US721595
申请日：1996-09-26
申请人： Marco Burzio , Paolo Pellegrino
发明人： Marco Burzio , Paolo Pellegrino
IPC分类号： H04L7/08 , H03M9/00 , H04J3/04 , H04L12/56 , H04Q3/00 , H04Q11/04
CPC分类号： H04Q11/0478 , H03M9/00 , H04J3/047 , H04L2012/5674
摘要： The serializing-parallelizing circuit comprises, on a single integrated circuit chip (IC), a transmitter (TX) which performs the parallel-to-series conversion of the data stream, the insertion into the serial stream, with a pre-set periodicity, of a synchronism word, and the line coding of the serial stream, and a receiver (RX) in which clock signals synchronous with the data stream are extracted from a serial stream of coded data and in which the data are decoded and the decoded signals undergo series-to-parallel conversion. The transmitter (TX) and the receiver (RX) can be configured to operate with 4 or 8-bit parallelism.
摘要翻译：串行并行化电路在单个集成电路芯片（IC）上包括以预定周期执行数据流的并行到串行转换的插入到串行流中的发射机（TX）同步字的串行编码和串行数据流的行编码以及与数据流同步的时钟信号从编码数据的串行数据中提取的数据被解码并且解码的信号经历的接收器（RX）串并转换。发送器（TX）和接收器（RX）可以配置为以4或8位并行运行。

8. 发明授权

US06255881B1 High tunability CMOS delay element 有权
标题翻译：高可调CMOS延迟元件
公开(公告)号：US06255881B1
公开(公告)日：2001-07-03
申请号：US09441775
申请日：1999-11-17
申请人： Emanuele Balistreri , Marco Burzio
发明人： Emanuele Balistreri , Marco Burzio
IPC分类号： H03K513
CPC分类号： H03K5/133 , H03K3/0231 , H03K3/0322
摘要： The delay element consists of a differential amplifier (M15, M8, M2, M6, M5) in which the load transistors (M2, M5) are associated to respective gate biasing transistors (M21, M22) connected in a source follower configuration, and to feedback transistors (M3, M4), which implement a negative impedance in parallel to a positive impedance represented by each of the load transistors (M2, M5). The modulation of the delay is achieved by modulating the bias currents of the load transistors (M2, M5), the feedback transistors (M3. M4) and the gate biasing transistors (M21, M22).
摘要翻译：延迟元件包括差分放大器（M15，M8，M2，M6，M5），其中负载晶体管（M2，M5）与以源跟随器配置连接的各个栅极偏置晶体管（M21，M22）相关联，反馈晶体管（M3，M4），其实现与由每个负载晶体管（M2，M5）表示的正阻抗并联的负阻抗。通过调制负载晶体管（M2，M5），反馈晶体管（M3·M4）和栅极偏置晶体管（M21，M22）的偏置电流来实现延迟的调制。

9. 发明授权

US6166587A CMOS circuit for generating a current reference, the circuit comprising a transistor in a weak inversion region 有权
标题翻译： CMOS电路，用于产生电流基准，该电路包括处于弱反转区域的晶体管
公开(公告)号：US6166587A
公开(公告)日：2000-12-26
申请号：US409033
申请日：1999-09-29
申请人： Marco Burzio , Emanuele Balistreri
发明人： Marco Burzio , Emanuele Balistreri
IPC分类号： G05F3/24 , G05F3/26 , H03F1/30 , H03L7/089 , G05F1/10
CPC分类号： H03L7/0891 , G05F3/245 , G05F3/247 , G05F3/262
摘要： A current reference generator comprises a pair of identical units (G1, G2) which generate respective current references (I1, I2), and a circuit (CL) for the linear combination of the two references. In each of the two units, the elements (S1, S2) which, by their current-voltage characteristics, determine the working point comprise respectively a single transistor (T1) and a pair of transistors (T2, T3), of the same type as the first, connected in series. A differential amplifier (AD) maintains stable the working point of the respective unit as power supply voltage varies. (FIG. 2)
摘要翻译：电流参考发生器包括一对相同的单元（G1，G2），其产生相应的电流参考值（I1，I2），以及用于两个参考线性组合的电路（CL）。在两个单元中的每一个中，通过其电流 - 电压特性确定工作点的元件（S1，S2）分别包括相同类型的单个晶体管（T1）和一对晶体管（T2，T3）作为第一个，串联连接。当电源电压变化时，差分放大器（AD）保持各单元的工作点的稳定。（图2）

10. 发明授权

US5686849A Circuit for clock signal extraction from a high speed data stream 失效
标题翻译：从高速数据流中提取时钟信号的电路
公开(公告)号：US5686849A
公开(公告)日：1997-11-11
申请号：US605393
申请日：1996-02-22
申请人： Marco Burzio
发明人： Marco Burzio
IPC分类号： H03K19/0175 , H03D13/00 , H03L7/085 , H03L7/087 , H03L7/089 , H03L7/113 , H03L7/14 , H04L7/033
CPC分类号： H03L7/14 , H03L7/113 , H04L7/033 , H03D13/004 , H03L7/087 , H03L7/0891
摘要： The circuit for clock signal extraction from a high speed data stream which allows a rapid attainment of the identity between the frequencies of the locally generated clock signal and of the data signal, even when such frequencies are very different. The circuit can easily be inserted into a more complex CMOS digital integrated circuit, it has low power dissipation and is capable of operating at bit rates exceeding 300 Mbit/s. The circuit has a main phase locked loop, which controls a voltage controlled oscillator by continually controlling its phase and a secondary loop, which allows the main loop to become locked, by causing the voltage controlled oscillator to oscillate at a frequency close to the operating frequency.
摘要翻译：用于从高速数据流提取时钟信号的电路，即使在这种频率非常不同的时候，也能够快速获得本地产生的时钟信号和数据信号的频率之间的同一性。该电路可以轻松插入更复杂的CMOS数字集成电路，具有低功耗，能够以超过300 Mbit / s的比特率运行。该电路具有主锁相环，其通过连续控制其相位和次级环路来控制压控振荡器，其允许主回路锁定，通过使压控振荡器以接近工作频率的频率振荡。

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