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1. 发明授权

US10313097B2 Bufferless ring network 有权
公开(公告)号：US10313097B2
公开(公告)日：2019-06-04
申请号：US15886912
申请日：2018-02-02
申请人： Huawei Technologies Co., Ltd.
发明人： Qiaoshi Zheng , Zhirui Chen , Jing Xia
IPC分类号： H04L5/22 , H04Q11/08 , G06F9/30 , H04L12/933 , H04J3/00 , H04L12/70
摘要： A bufferless ring network including at least two nodes and at least two timeslots, the at least two timeslots include a dedicated timeslot, and a first node in the bufferless ring network has use permission for the dedicated timeslot. The first node is configured to, in a state of having the use permission for the dedicated timeslot, detect whether all dedicated timeslots that pass through the first node are available, set a permission switch signal, and cancel the use permission for the dedicated timeslot according to the permission switch signal after detecting that all the dedicated timeslots that pass through the first node are available. A remaining node in the bufferless ring network is configured to obtain the use permission for the dedicated timeslot according to the permission switch signal. The remaining node is a node that needs to use the dedicated timeslot.

2. 发明授权

US5544163A Expandable telecommunications system 失效
公开(公告)号：US5544163A
公开(公告)日：1996-08-06
申请号：US207931
申请日：1994-03-08
申请人： Robert P. Madonna
发明人： Robert P. Madonna
IPC分类号： H04M3/00 , H04L12/43 , H04L12/56 , H04L12/64 , H04Q3/00 , H04Q11/04 , H04Q11/08
CPC分类号： H04L49/105 , H04L12/43 , H04L12/6418 , H04Q11/0478 , H04Q3/002 , H04L2012/5612 , H04L2012/6437 , H04L2012/6443 , H04L2012/6459 , H04L2012/6475 , H04L2012/6481 , H04L2012/6486 , Y10S379/909
摘要： An open, high speed, high bandwidth digital communication network for connecting multiple programmable telecommunications switches to form a large capacity, non-blocking switching system. Each network switching node includes circuitry for transmitting and receiving variable-length, packetized information over the network, thus enabling each node to receive information from or transmit information to all other nodes. The network may carry any type of information present in the system including voice, data, video, multimedia, control, configuration and maintenance, and the bandwidth of the network may be divided or shared across various information types. Devices such as voice processing resources may also interface with the network, thereby gaining direct access to all information passing through the network. Also provided are methods and packet structures for communicating information over the network. Multiple networks may be interconnected to provide even greater switching capacity or voice processing capacity.

3. 发明授权

US5541921A Isochronous serial time division multiplexer 失效
标题翻译：同步串行时分复用器
公开(公告)号：US5541921A
公开(公告)日：1996-07-30
申请号：US349977
申请日：1994-12-06
申请人： Erik R. Swenson , Paul Foster
发明人： Erik R. Swenson , Paul Foster
IPC分类号： H04J3/04 , H04Q11/04 , H04Q11/08
CPC分类号： H04J3/047 , H04Q11/04
摘要： A serial time division multiplexer routes data from a plurality of isochronous data sources to a plurality of isochronous data sinks without buffering the data in a random-access memory by utilizing a plurality of selectors that each select predetermined time slots from a plurality of incoming isochronous data streams. Each selector selects which time slots are to be received in response to a sequence of selection codes. A control stage controls the timing of the selection codes so that each selector receives a selection code when the time slot that corresponds to that selection code is received.
摘要翻译：串行时分多路复用器将数据从多个同步数据源路由到多个等时数据接收器，而不用随机存取存储器中的数据缓冲数据，利用多个选择器，每个选择器从多个输入同步数据中选择预定的时隙流。每个选择器响应于选择代码的顺序选择要接收的时隙。控制级控制选择代码的定时，使得当接收到对应于该选择代码的时隙时，每个选择器接收选择代码。

4. 发明授权

US5430718A Generating idle codes in switches 失效
标题翻译：在交换机中生成空闲代码
公开(公告)号：US5430718A
公开(公告)日：1995-07-04
申请号：US73667
申请日：1993-06-08
申请人： Lars-Goran Petersen
发明人： Lars-Goran Petersen
IPC分类号： H04Q11/08
CPC分类号： H04Q11/08
摘要： A circuit switch connected between transmitting and receiving devices includes a switch memory including a number of memory positions for entering of received time slot data from the transmitting devices, a control memory including a number of memory positions for entering read-out addresses for the switch memory, an addressing path from the control memory to the switch memory for a read-out address in the latter, from which read-out of data shall be made towards a receiving device, and a control unit for entering the read-out addresses in the control memory and for receiving information from the devices related to the connect and disconnect of calls. The addressing path from the control memory has an alternative communication path towards the receiving devices, and each memory position in the control memory includes a specific position for an indicator bit containing information with respect to whether read-out of time slot data should be made from the switch memory or from the control memory.
摘要翻译：连接在发送和接收设备之间的电路交换机包括一个开关存储器，包括用于从发送设备输入接收的时隙数据的多个存储器位置;控制存储器，包括用于输入开关存储器的读出地址的多个存储器位置，从控制存储器到开关存储器的寻址路径，用于在后者中的读出地址，从该数据读出数据到接收设备，以及控制单元，用于输入读出地址控制存储器和用于从与呼叫的连接和断开相关的设备接收信息。来自控制存储器的寻址路径具有朝向接收设备的替代通信路径，并且控制存储器中的每个存储器位置包括用于指示位的特定位置，该位置包含关于是否应当从开关存储器或控制存储器。

5. 发明授权

US5416772A Apparatus for insertion of overhead protocol data into a switched data stream 失效
标题翻译：将开销协议数据插入交换数据流的装置
公开(公告)号：US5416772A
公开(公告)日：1995-05-16
申请号：US109766
申请日：1993-08-20
申请人： John S. Helton , Stephen R. Peck , Floyd C. Wolverton
发明人： John S. Helton , Stephen R. Peck , Floyd C. Wolverton
IPC分类号： H04J3/00 , H04J3/08 , H04Q11/04 , H04Q11/08
CPC分类号： H04Q11/0421 , H04J3/08 , Y10S370/907
摘要： An apparatus that provides two different sources for generating the bytes to be inserted into frames of data being communicated through a switching unit. This apparatus allows for the insertion of variable, programmable data patterns in multiple frames. Under program control of a controller, the first source can selectively write data into designated time slots within designated rows and designated frames of multiple frames. Different data can be inserted into different rows of the same column of each frame. In addition, different data for different frames can be inserted into different rows of the same column. Also, the same data can be inserted into designated a row and column of a designated frame. The second source can write data into every row of a designated column of every frame.
摘要翻译：一种提供两个不同来源的装置，用于生成待插入到通过切换单元传送的数据帧中的字节。该装置允许在多个帧中插入可变的可编程数据模式。在控制器的程序控制下，第一源可以选择性地将数据写入指定行中的指定时隙和多个帧的指定帧。不同的数据可以插入到每个帧的同一列的不同行中。此外，不同帧的不同数据可以插入同一列的不同行。此外，相同的数据可以插入到指定的帧的指定行和列中。第二个源可以将数据写入每帧指定列的每一行。

6. 发明授权

US5408468A Queueing system for switches having fast circuit properties 失效
标题翻译：具有快速电路特性的开关排队系统
公开(公告)号：US5408468A
公开(公告)日：1995-04-18
申请号：US64445
申请日：1993-05-21
申请人： Lars-Goran Petersen
发明人： Lars-Goran Petersen
IPC分类号： H04M3/48 , H04L12/70 , H04L12/935 , H04L12/937 , H04Q11/04 , H04Q11/08 , H04L12/16 , H04M3/42
CPC分类号： H04L49/3081 , H04L49/255 , H04Q11/0478 , H04Q11/08 , H04J2203/0005 , H04J2203/0012 , H04J2203/0066 , H04L2012/563
摘要： A digital switch serves a number of terminal units for switching signal traffic therebetween, the traffic being logically divided into data time slots and control time slots with control packets. It comprises a switch memory for receiving the data time slots, a control memory containing information for facilitating through connection of the data time slots in the switch memory, a control memory terminal for receiving the control time slots and control packets located therein, for writing information into the control memory, and for transmitting acknowledgement packets to called and calling ones of the terminal units, and an occupied/unoccupied memory cooperating with the control memory terminal and storing actual status of each of the terminal units. A queue system is associated with the control memory terminal and the occupied/unoccupied memory, the queue system including memory and control logic for effecting, in case a first terminal unit tries to establish connection to a second terminal unit that is occupied, queueing of a call request and transmission to the first terminal unit of an acknowledgement "request for connection queued" and, at the receipt of a request for disconnection from the second terminal unit, direct connection of the first terminal unit to the second terminal unit, and transmission of acknowledgements to the first and second terminal units with the information "connection effected" and "request effected", respectively.
摘要翻译：数字交换机为多个终端单元服务，用于切换其间的信号业务，业务在逻辑上划分为具有控制分组的数据时隙和控制时隙。它包括用于接收数据时隙的开关存储器，包含用于便于通过连接开关存储器中的数据时隙的信息的控制存储器，用于接收控制时隙的控制存储器端子和位于其中的控制分组，用于写入信息进入控制存储器，以及用于将确认分组发送到所述终端单元的被叫和呼叫，以及与所述控制存储器终端配合的占用/未占用的存储器，并存储每个所述终端单元的实际状态。队列系统与控制存储器终端和被占用/未占用存储器相关联，该队列系统包括存储器和控制逻辑，用于在第一终端单元尝试建立到被占用的第二终端单元的连接的情况下进行排队呼叫请求和向第一终端单元传送确认“连接排队请求”，并且在接收到从第二终端单元断开请求时，将第一终端单元直接连接到第二终端单元，并且传送对第一和第二个终端单位的承认，分别具有“连接实现”和“请求实现”的信息。

7. 发明授权

US5381406A Time switching circuit 失效
标题翻译：时间切换电路
公开(公告)号：US5381406A
公开(公告)日：1995-01-10
申请号：US938432
申请日：1992-08-31
申请人： Hiroshi Yamashita
发明人： Hiroshi Yamashita
IPC分类号： H04Q3/52 , H04Q11/04 , H04Q11/08 , H04J3/02
CPC分类号： H04Q11/08
摘要： A time switching circuit includes n data memories (n being an integer equal to or greater than 2), a respective address control memory for each data memory, and a control section. Each of the n data memories has n input ports corresponding to n data strings and one output port. The n input ports are multi-connected. The respective address control memory of each data memory writes the n data strings in the data memories as written data strings. The control section selectively reads out the written data strings from each of the data memories and outputs the written data strings as readout data strings.
摘要翻译：时间切换电路包括n个数据存储器（n为2以上的整数），各数据存储器的各自的地址控制存储器以及控制部。 n个数据存储器中的每一个具有对应于n个数据串和一个输出端口的n个输入端口。 n个输入端口是多连接的。每个数据存储器的相应地址控制存储器将n个数据串写入数据存储器中作为写入的数据串。控制部分从每个数据存储器中选择性地读出写入的数据串，并将写入的数据串作为读出数据串输出。

8. 发明授权

US5304992A Method of allocating identifiers and apparatus for the same 失效
标题翻译：为其分配标识符和装置的方法
公开(公告)号：US5304992A
公开(公告)日：1994-04-19
申请号：US791306
申请日：1991-11-14
申请人： Shuuji Harashima
发明人： Shuuji Harashima
IPC分类号： H04L12/24 , H04Q11/08 , G08C15/06 , H04J3/24 , H04L29/06
CPC分类号： H04L41/26
摘要： In a distributed system where a plurality of sites broadcast data using a common communication line for data processing, the object site is identified by its unique identifier. When multiple sites are newly participating in the distributed system in operation, unique identifiers are allocated to the individual new sites.
摘要翻译：在多个站点使用公共通信线广播数据进行数据处理的分布式系统中，通过其唯一标识符识别对象站点。当多个站点新参与正在运行的分布式系统时，将唯一的标识符分配给各个新站点。

9. 发明授权

US4912700A Telecommunications digital switch 失效
标题翻译：电信数字开关
公开(公告)号：US4912700A
公开(公告)日：1990-03-27
申请号：US265821
申请日：1988-11-01
申请人： Thomas S. Maddern , Geoffrey Chopping
发明人： Thomas S. Maddern , Geoffrey Chopping
IPC分类号： H04Q11/04 , H04Q11/08
CPC分类号： H04Q11/08
摘要： In order to permit multislot connections to be simply made across a telecommunications digital switch, so that all the slots of the multislot connection experience the same whole frame time delay, the switch is constructed as input and output switch stages each comprising arrays of digital switching modules (DSM) and a central switching area comprising two arrays of Demultiplexing/Mixing/Remultiplexing devices (DMR) interconnected by an array of digital switching modules (DSM), wherein each DMR has a transfer function such that a channel (p) in a time frame of (q) channels on an input line (r) appears on an output line (s) which is related to the input line by means of a backward rotate function, where s=MOD (q-r+p), where MOD=modulo q. This construction of switch ensures that all channels routed through the switch have one of only two possible values of whole frame time delay, thereby simplifying the setting up of a multislot connection.

10. 发明授权

US4903259A Time-division multiplex switching network 失效
标题翻译：时分复用交换网络
公开(公告)号：US4903259A
公开(公告)日：1990-02-20
申请号：US222259
申请日：1988-07-21
申请人： Shin-Ichiro Hayano
发明人： Shin-Ichiro Hayano
IPC分类号： H04Q11/08
CPC分类号： H04Q11/08
摘要： A switching network is constituted by a plurality of time switches which are arranged in a matrix and at cross points between a plurality of input buses and a plurality of output buses, on which frame synchronization signals are multiplexed. Each time switch includes a data memory in which data on the input bus is written in synchronism with the frame synchronization signal included in the input bus, and from which data is read out under the address control of a control memory in synchronization with the frame synchronization signal included in the output bus.
摘要翻译：开关网络由多个时间开关构成，多个时间开关以矩阵形式布置在多个输入总线与多个输出总线之间的交叉点，帧同步信号被多路复用。每次开关包括一个数据存储器，其中输入总线上的数据与包括在输入总线中的帧同步信号同步写入，并且在与帧同步同步的同时在控制存储器的地址控制下从中读出数据输出总线中包含的信号。

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