专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07577794B2 Low latency coherency protocol for a multi-chip multiprocessor system 失效
标题翻译：用于多芯片多处理器系统的低延迟一致性协议
公开(公告)号：US07577794B2
公开(公告)日：2009-08-18
申请号：US10961751
申请日：2004-10-08
申请人： Bruce L. Beukema , Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich , Sandra S. Woodward
发明人： Bruce L. Beukema , Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich , Sandra S. Woodward
IPC分类号： G06F12/00
CPC分类号： G06F12/0828
摘要： Methods and apparatus for reducing the amount of latency involved when accessing, by a remote device, data residing in a cache of a processor are provided. For some embodiments, virtual channels may be utilized to conduct request/response transactions between the remote device and processor that satisfy a set of associated coherency rules.
摘要翻译：提供了用于减少由远程设备访问驻留在处理器的高速缓存中的数据所涉及的等待时间量的方法和装置。对于一些实施例，虚拟信道可以用于在满足一组相关联的一致性规则的远程设备和处理器之间进行请求/响应事务。

2. 发明授权

US07840757B2 Method and apparatus for providing high speed memory for a processing unit 有权
标题翻译：用于为处理单元提供高速存储器的方法和装置
公开(公告)号：US07840757B2
公开(公告)日：2010-11-23
申请号：US10901600
申请日：2004-07-29
申请人： Bruce L. Beukema , Russell D. Hoover , Jon K. Kriegel , Jamie R. Kuesel , Eric O. Mejdrich , Robert A. Shearer , Bruce M. Walk
发明人： Bruce L. Beukema , Russell D. Hoover , Jon K. Kriegel , Jamie R. Kuesel , Eric O. Mejdrich , Robert A. Shearer , Bruce M. Walk
IPC分类号： G06F12/00
CPC分类号： G06F12/0888
摘要： Computer systems with direct updating of cache (e.g., primary L1 cache) memories of a processor, such as a central processing unit (CPU) or graphics processing unit (GPU). Special addresses are reserved for high speed memory. Memory access requests involving these reserved addresses are routed directly to the high speed memory. Memory access requests not involving these reserved addresses are routed to memory external to the processor.
摘要翻译：具有直接更新诸如中央处理单元（CPU）或图形处理单元（GPU）的处理器的高速缓存（例如，主要L1高速缓存）存储器的计算机系统。专用地址保留给高速存储器。涉及这些保留地址的存储器访问请求直接路由到高速存储器。不涉及这些保留地址的存储器访问请求被路由到处理器外部的存储器。

3. 发明授权

US07385925B2 Data flow control method for simultaneous packet reception 失效
标题翻译：用于同时进行数据包接收的数据流控制方法
公开(公告)号：US07385925B2
公开(公告)日：2008-06-10
申请号：US10981063
申请日：2004-11-04
申请人： Bruce L. Beukema , Mark J. Hickey , Robert A. Shearer
发明人： Bruce L. Beukema , Mark J. Hickey , Robert A. Shearer
IPC分类号： H04L12/26
CPC分类号： H04L47/10 , H04L47/30 , H04L47/39
摘要： Embodiments of the present invention provide methods, a module, and a system for calculating a credit limit for an interface capable of receiving multiple packets simultaneously. Generally, the multiple packets are simultaneously received at an interface on the second device, each packet being one of a plurality of packet types, and a flow control credit limit to be transmitted to the first device is adjusted based on the combination of packet types of the simultaneously received packets.
摘要翻译：本发明的实施例提供了用于计算能够同时接收多个分组的接口的信用限额的方法，模块和系统。通常，在第二设备的接口处同时接收多个分组，每个分组是多个分组类型之一，并且基于分组类型的组合来调整要发送到第一设备的流控制信用限制同时接收的数据包。

4. 发明授权

US07366813B2 Event queue in a logical partition 有权
标题翻译：逻辑分区中的事件队列
公开(公告)号：US07366813B2
公开(公告)日：2008-04-29
申请号：US11764988
申请日：2007-06-19
申请人： Thomas A. Gregg , Richard L. Arndt , Bruce L. Beukema , David Craddock , Ronald E. Fuhs , Steven L. Rogers , Donald W. Schmidt , Bruce M. Walk
发明人： Thomas A. Gregg , Richard L. Arndt , Bruce L. Beukema , David Craddock , Ronald E. Fuhs , Steven L. Rogers , Donald W. Schmidt , Bruce M. Walk
IPC分类号： G06F13/24 , G06F3/00 , G06F13/40
CPC分类号： G06F9/546 , G06F2209/548 , H04L49/901
摘要： An information processing system is provided which includes a plurality of system resources, and an event queue having a predetermined number of entries. An event recording mechanism of the information processing system is operable to make entries regarding events in the event queue, wherein the entries are limited to a predetermined number of active entries in the event queue per each type of event per each of the system resources. In a particular embodiment, the number of entries per each type of event for each of the system resources is limited to one.
摘要翻译：提供了包括多个系统资源的信息处理系统和具有预定数量的条目的事件队列。信息处理系统的事件记录机制可操作用于对事件队列中的事件进行条目，其中每个系统资源每个事件类型事件限制事件队列中预定数量的活动条目。在特定实施例中，每个系统资源的每种类型的事件的条目数量被限制为一个。

5. 发明授权

US07660247B2 Dynamic load-based credit distribution 失效
标题翻译：基于动态负载的信用分配
公开(公告)号：US07660247B2
公开(公告)日：2010-02-09
申请号：US12018226
申请日：2008-01-23
申请人： Bruce L. Beukema , Jamie R. Kuesel , Robert A. Shearer , Bruce M. Walk
发明人： Bruce L. Beukema , Jamie R. Kuesel , Robert A. Shearer , Bruce M. Walk
IPC分类号： H04J3/14 , H04J3/22
CPC分类号： G06F13/4208
摘要： Methods and systems for dynamically adjusting credits used to distribute available bus bandwidth among multiple virtual channels, based on the workload of each virtual channel, are provided. Accordingly, for some embodiments, virtual channels with higher workloads relative to other virtual channels may receive a higher allocation of bus bandwidth (more credits).
摘要翻译：提供了基于每个虚拟通道的工作负载动态调整用于在多个虚拟通道中分配可用总线带宽的信用的方法和系统。因此，对于一些实施例，相对于其他虚拟信道具有较高工作负载的虚拟信道可以接收更高的总线带宽分配（更多信用）。

6. 发明授权

US07362705B2 Dynamic load-based credit distribution 有权
标题翻译：基于动态负载的信用分配
公开(公告)号：US07362705B2
公开(公告)日：2008-04-22
申请号：US10845497
申请日：2004-05-13
申请人： Bruce L. Beukema , Jamie R. Kuesel , Robert A. Shearer , Bruce M. Walk
发明人： Bruce L. Beukema , Jamie R. Kuesel , Robert A. Shearer , Bruce M. Walk
IPC分类号： H04J3/14 , H04J3/22
CPC分类号： G06F13/4208
摘要： Methods and systems for dynamically adjusting credits used to distribute available bus bandwidth among multiple virtual channels, based on the workload of each virtual channel, are provided. Accordingly, for some embodiments, virtual channels with higher workloads relative to other virtual channels may receive a higher allocation of bus bandwidth (more credits).
摘要翻译：提供了基于每个虚拟通道的工作负载动态调整用于在多个虚拟通道中分配可用总线带宽的信用的方法和系统。因此，对于一些实施例，相对于其他虚拟信道具有较高工作负载的虚拟信道可以接收更高的总线带宽分配（更多信用）。

7. 发明授权

US5584033A Apparatus and method for burst data transfer employing a pause at fixed data intervals 失效
标题翻译：用于以固定数据间隔进行暂停的突发数据传输的装置和方法
公开(公告)号：US5584033A
公开(公告)日：1996-12-10
申请号：US335228
申请日：1994-11-07
申请人： Wayne M. Barrett , Bruce L. Beukema , William E. Hammer , Daniel F. Moertl
发明人： Wayne M. Barrett , Bruce L. Beukema , William E. Hammer , Daniel F. Moertl
IPC分类号： G06F13/28 , G06F13/36 , G06F13/42 , H04L29/08
CPC分类号： G06F13/28 , G06F13/4226
摘要： A plurality of devices attached to a communications bus observe a burst transfer protocol which allows pausing only at pre-determined, fixed intervals of n data words, where a word is the width of the bus. In accordance with this protocol, once burst transfer is initialized the sending device transmits an uninterrupted stream of n data words over the communications bus, after which either the sender or receiver may cause transmission to pause. The sender may need to wait for more data, or the receiver may need to finish processing the data just received. The pause lasts as long as needed until both devices are ready to proceed. This cycle is repeated until the data transmission is complete. The sending and receiving devices do not relinquish control of the bus during a pause, and therefore are not required to re-initialize communications. In the preferred embodiment, after n data words have been transmitted, the sender and receiver toggle interlocking signals that accomplish a handshaking between the two devices. The sender de-activates its signal when it is ready to send more, and the receiver de-activates its signal when it is ready to receive more. Both devices are equipped with buffers large enough to hold n data words, but the buffers need not be as large as the longest possible burst communication.
摘要翻译：连接到通信总线的多个设备观察突发传输协议，该协议允许仅以n个数据字的预定的固定间隔暂停，其中一个字是总线的宽度。根据该协议，一旦突发传送被初始化，发送设备通过通信总线发送不间断的n个数据字流，之后发送者或接收者可能导致传输暂停。发送方可能需要等待更多的数据，否则接收方可能需要完成处理刚收到的数据。暂停持续时间长，直到两台设备都准备好继续。重复此循环，直到数据传输完成。发送和接收设备在暂停期间不放弃总线的控制，因此不需要重新初始化通信。在优选实施例中，在发送n个数据字之后，发送器和接收器切换在两个装置之间完成握手的互锁信号。当准备好发送更多信号时，发送器取消激活其信号，当接收器准备好接收信号时，接收器会取消激活信号。两个设备都配备有足够大的缓冲器以容纳n个数据字，但缓冲器不需要像最长可能的突发通信一样大。

8. 发明授权

US08069353B2 Low-latency data decryption interface 有权
标题翻译：低延迟数据解密界面
公开(公告)号：US08069353B2
公开(公告)日：2011-11-29
申请号：US12142007
申请日：2008-06-19
申请人： Bruce L. Beukema , Robert A. Drehmel , William E. Hall , Jamie R. Kuesel , Gilad Pivonia , Robert A. Shearer
发明人： Bruce L. Beukema , Robert A. Drehmel , William E. Hall , Jamie R. Kuesel , Gilad Pivonia , Robert A. Shearer
IPC分类号： H04L9/32
CPC分类号： G06F21/72 , H04L9/06 , H04L63/123 , H04L2209/125
摘要： Methods and apparatus for reducing the impact of latency associated with decrypting encrypted data are provided. Rather than wait until an entire packet of encrypted data is validated (e.g., by checking for data transfer errors), the encrypted data may be pipelined to a decryption engine as it is received, thus allowing decryption to begin prior to validation. In some cases, the decryption engine may be notified of data transfer errors detected during the validation process, in order to prevent reporting false security violations.
摘要翻译：提供了减少与解密加密数据相关的延迟的影响的方法和装置。而不是等到整个加密数据包被验证（例如，通过检查数据传输错误），加密的数据可以在被接收时被流水线化到解密引擎，从而允许在验证之前开始解密。在一些情况下，可以向解密引擎通知在验证过程期间检测到的数据传输错误，以防止报告错误的安全违规。

9. 发明授权

US07970952B2 Performance counters for virtualized network interfaces of communications networks 失效
标题翻译：通信网络虚拟化网络接口的性能计数器
公开(公告)号：US07970952B2
公开(公告)日：2011-06-28
申请号：US12472648
申请日：2009-05-27
申请人： Richard L. Arndt , Bruce L. Beukema , David Craddock , Ronald E. Fuhs , Thomas A. Gregg , Donald W. Schmidt , Bruce M. Walk
发明人： Richard L. Arndt , Bruce L. Beukema , David Craddock , Ronald E. Fuhs , Thomas A. Gregg , Donald W. Schmidt , Bruce M. Walk
IPC分类号： G06F15/16
CPC分类号： H04L43/00 , H04L41/046 , H04L41/5009 , H04L43/0847
摘要： Performance counters are provided for virtualized network interfaces of communications networks, while minimizing the use of hardware resources. A virtualized network interface includes physical resources, as well as logical resources. Dedicated performance counters are provided for the physical resources of the virtualized network interface, as well as for logical partitions coupled to that interface, while non-dedicated performance counters are provided for the logical resources. This enables the provision of performance counters for virtualized network interfaces, while minimizing hardware resources consumed by those interfaces.
摘要翻译：为通信网络的虚拟网络接口提供性能计数器，同时最大限度地减少硬件资源的使用。虚拟化网络接口包括物理资源以及逻辑资源。为虚拟化网络接口的物理资源以及耦合到该接口的逻辑分区提供专用性能计数器，同时为逻辑资源提供非专用性能计数器。这使得能够为虚拟化网络接口提供性能计数器，同时最小化这些接口所消耗的硬件资源。

10. 发明授权

US07409558B2 Low-latency data decryption interface 有权
标题翻译：低延迟数据解密界面
公开(公告)号：US07409558B2
公开(公告)日：2008-08-05
申请号：US10932727
申请日：2004-09-02
申请人： Bruce L. Beukema , Robert A. Drehmel , William E. Hall , Jamie R. Kuesel , Gilad Pivonia , Robert A. Shearer
发明人： Bruce L. Beukema , Robert A. Drehmel , William E. Hall , Jamie R. Kuesel , Gilad Pivonia , Robert A. Shearer
IPC分类号： H04L9/00
CPC分类号： G06F21/72 , H04L9/06 , H04L63/123 , H04L2209/125
摘要： Methods and apparatus for reducing the impact of latency associated with decrypting encrypted data are provided. Rather than wait until an entire packet of encrypted data is validated (e.g., by checking for data transfer errors), the encrypted data may be pipelined to a decryption engine as it is received, thus allowing decryption to begin prior to validation. In some cases, the decryption engine may be notified of data transfer errors detected during the validation process, in order to prevent reporting false security violations.
摘要翻译：提供了减少与解密加密数据相关的延迟的影响的方法和装置。而不是等到整个加密数据包被验证（例如，通过检查数据传输错误），加密的数据可以在被接收时被流水线化到解密引擎，从而允许在验证之前开始解密。在一些情况下，可以向解密引擎通知在验证过程期间检测到的数据传输错误，以防止报告错误的安全违规。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式