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1. 发明申请

US20090077320A1 DIRECT ACCESS OF CACHE LOCK SET DATA WITHOUT BACKING MEMORY 审中-公开
标题翻译：直接访问缓存设置数据，而不需要备份内存
公开(公告)号：US20090077320A1
公开(公告)日：2009-03-19
申请号：US12274548
申请日：2008-11-20
申请人： Russell D. Hoover , Eric O. Mejdrich , Sandra S. Woodward
发明人： Russell D. Hoover , Eric O. Mejdrich , Sandra S. Woodward
IPC分类号： G06F12/08
CPC分类号： G06F12/126 , G06F12/084 , G06F2212/2515
摘要： Apparatus and system for quickly accessing data residing in a cache of one processor, by another processor, while avoiding lengthy accesses to main memory are provided. A portion of the cache may be placed in a lock set mode by the processor in which it resides. While in the lock set mode, this portion of the cache may be accessed directly by another processor without lengthy “backing” writes of the accessed data to main memory.
摘要翻译：提供了用于通过另一处理器快速访问位于一个处理器的高速缓存中的数据的装置和系统，同时避免对主存储器的长时间访问。高速缓存的一部分可以由其驻留的处理器置于锁定模式中。在锁定模式下，高速缓存的这一部分可能被另一个处理器直接访问，而不会对所访问的数据进行长时间的“后退”写入主存储器。

2. 发明授权

US07305524B2 Snoop filter directory mechanism in coherency shared memory system 失效
标题翻译： Snoop过滤器目录机制中的一致性共享内存系统
公开(公告)号：US07305524B2
公开(公告)日：2007-12-04
申请号：US10961749
申请日：2004-10-08
申请人： Russell D. Hoover , Eric O. Mejdrich , Jon K. Kriegel , Sandra S. Woodward
发明人： Russell D. Hoover , Eric O. Mejdrich , Jon K. Kriegel , Sandra S. Woodward
IPC分类号： G06F12/00
CPC分类号： G06F12/0835 , G06F12/0822 , G06F2212/302
摘要： Methods and apparatus that may be utilized to maintain coherency of data accessed by both a processor and a remote device are provided. Various mechanisms, such as a remote cache directory, castout buffer, and/or outstanding transaction buffer may be utilized by the remote device to track the state of processor cache lines that may hold data targeted by requests initiated by the remote device. Based on the content of these mechanisms, requests targeting data that is not in the processor cache may be routed directly to memory, thus reducing overall latency.
摘要翻译：提供了可用于维护由处理器和远程设备访问的数据的一致性的方法和装置。远程设备可以利用各种机制，诸如远程高速缓存目录，转储缓冲区和/或未完成的事务缓冲器来跟踪可以保存由远程设备发起的请求所针对的数据的处理器高速缓存行的状态。基于这些机制的内容，针对不在处理器高速缓存中的数据的请求可以直接路由到存储器，从而减少总体延迟。

3. 发明授权

US06791352B2 Method and apparatus for debugging a chip 失效
标题翻译：调试芯片的方法和装置
公开(公告)号：US06791352B2
公开(公告)日：2004-09-14
申请号：US10072103
申请日：2002-02-08
申请人： David Joel Verdoorn , Sandra S. Woodward
发明人： David Joel Verdoorn , Sandra S. Woodward
IPC分类号： H03K19173
CPC分类号： G01R31/31705 , G01R31/317 , G01R31/31704
摘要： In a first aspect, an apparatus is provided that is adapted to multiplex debug signals of an integrated circuit. The apparatus includes at least a first multiplexing circuit and a second multiplexing circuit. The first multiplexing circuit is adapted to receive first debug signals from the integrated circuit and to selectively multiplex at least a first portion of the first debug signals onto a first bus. The second multiplexing circuit is adapted to receive second debug signals from the integrated circuit and to selectively multiplex at least a first portion of the second debug signals onto a second bus. The apparatus further includes a logic circuit adapted to combine any debug signals of the first and second buses onto a third bus. An output stage of the apparatus is adapted to selectively output debug signals of the third bus. Numerous other aspects are provided, as are systems and methods.
摘要翻译：在第一方面，提供一种适于复用集成电路的调试信号的装置。该装置至少包括第一复用电路和第二复用电路。第一复用电路适于从集成电路接收第一调试信号，并且将第一调试信号的至少第一部分选择性地复用到第一总线上。第二复用电路适于从集成电路接收第二调试信号，并且将第二调试信号的至少第一部分选择性地复用到第二总线上。该装置还包括适于将第一和第二总线的任何调试信号组合到第三总线上的逻辑电路。该装置的输出级适于选择性地输出第三总线的调试信号。还提供了许多其他方面，系统和方法也是如此。

4. 发明授权

US07475190B2 Direct access of cache lock set data without backing memory 失效
标题翻译：直接访问缓存锁集数据而无需备份内存
公开(公告)号：US07475190B2
公开(公告)日：2009-01-06
申请号：US10961752
申请日：2004-10-08
申请人： Russell D. Hoover , Eric O. Mejdrich , Sandra S. Woodward
发明人： Russell D. Hoover , Eric O. Mejdrich , Sandra S. Woodward
IPC分类号： G06F15/167 , G06F12/00
CPC分类号： G06F12/126 , G06F12/084 , G06F2212/2515
摘要： Methods for quickly accessing data residing in a cache of one processor, by another processor, while avoiding lengthy accesses to main memory are provided. A portion of the cache may be placed in a lock set mode by the processor in which it resides. While in the lock set mode, this portion of the cache may be accessed directly by another processor without lengthy “backing” writes of the accessed data to main memory.
摘要翻译：提供了一种方法，用于通过另一处理器快速访问位于一个处理器的高速缓存中的数据，同时避免长时间访问主存储器。高速缓存的一部分可以由其驻留的处理器置于锁定模式中。在锁定模式下，高速缓存的这一部分可能被另一个处理器直接访问，而不会对所访问的数据进行长时间的“后退”写入主存储器。

5. 发明授权

US6044447A Method and apparatus for communicating translation command information in a multithreaded environment 失效
标题翻译：在多线程环境中传达转换命令信息的方法和装置
公开(公告)号：US6044447A
公开(公告)日：2000-03-28
申请号：US017307
申请日：1998-01-30
申请人： Duane Arlyn Averill , John Michael Borkenhagen , James Anthony Steenburgh , Sandra S. Woodward
发明人： Duane Arlyn Averill , John Michael Borkenhagen , James Anthony Steenburgh , Sandra S. Woodward
IPC分类号： G06F12/10 , G06F12/00
CPC分类号： G06F12/10
摘要： A method and apparatus are provided for communicating translation command information in a multithreaded environment in a computer system. The computer system includes a processor unit, an instruction unit coupled to the processor unit, a cache coupled to the processor unit, a main memory, and a storage control unit including a dataflow control partition, a cache control partition, a translation control partition. A translation miss signal is sent from the dataflow control partition to the translation control partition, responsive to detecting a translation miss condition. A translation command next signal is sent from the translation control partition to the cache control partition responsive to the translation miss signal. Then a translation command signal is sent from the translation control partition to the cache control partition. Responsive to the translation miss signal, a steal command signal is applied to the instruction unit for providing the translation command priority over execution of another thread. A series of the translation command signals are sent from the translation control partition to the cache control partition, and in one control cycle, the translation control partition can receive a translation command taken signal from the cache control partition for a translation command signal and can receive a translation data valid signal from the cache control partition for another translation command signal.
摘要翻译：提供了一种用于在计算机系统中的多线程环境中传送转换命令信息的方法和装置。计算机系统包括处理器单元，耦合到处理器单元的指令单元，耦合到处理器单元的高速缓存，主存储器和包括数据流控制分区，高速缓存控制分区，转换控制分区的存储控制单元。响应于检测到翻译未命中状况，将翻译未命中信号从数据流控制分区发送到翻译控制分区。翻译命令下一个信号从翻译控制分区发送到缓存控制分区，以响应于翻译未命中信号。然后，转换命令信号从转换控制分区发送到高速缓存控制分区。响应于翻译未命中信号，窃取命令信号被施加到指令单元，以提供翻译命令优先级超过另一线程的执行。一系列翻译命令信号从翻译控制分区发送到高速缓存控制分区，并且在一个控制周期中，转换控制分区可以接收来自用于转换命令信号的高速缓存控制分区的转换命令信号，并且可以接收来自高速缓存控制分区的翻译数据有效信号用于另一个转换命令信号。

6. 发明授权

US07577794B2 Low latency coherency protocol for a multi-chip multiprocessor system 失效
标题翻译：用于多芯片多处理器系统的低延迟一致性协议
公开(公告)号：US07577794B2
公开(公告)日：2009-08-18
申请号：US10961751
申请日：2004-10-08
申请人： Bruce L. Beukema , Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich , Sandra S. Woodward
发明人： Bruce L. Beukema , Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich , Sandra S. Woodward
IPC分类号： G06F12/00
CPC分类号： G06F12/0828
摘要： Methods and apparatus for reducing the amount of latency involved when accessing, by a remote device, data residing in a cache of a processor are provided. For some embodiments, virtual channels may be utilized to conduct request/response transactions between the remote device and processor that satisfy a set of associated coherency rules.
摘要翻译：提供了用于减少由远程设备访问驻留在处理器的高速缓存中的数据所涉及的等待时间量的方法和装置。对于一些实施例，虚拟信道可以用于在满足一组相关联的一致性规则的远程设备和处理器之间进行请求/响应事务。

7. 发明授权

US07355601B2 System and method for transfer of data between processors using a locked set, head and tail pointers 失效
标题翻译：使用锁定集，头和尾指针在处理器之间传输数据的系统和方法
公开(公告)号：US07355601B2
公开(公告)日：2008-04-08
申请号：US11303525
申请日：2005-12-16
申请人： Jeffrey A. Andrews , Nicholas R. Baker , J. Andrew Goossen , Russell D. Hoover , Eric O. Mejdrich , Sandra S. Woodward
发明人： Jeffrey A. Andrews , Nicholas R. Baker , J. Andrew Goossen , Russell D. Hoover , Eric O. Mejdrich , Sandra S. Woodward
IPC分类号： G06F12/08 , G06F9/46 , G06F13/20 , G06F15/80 , G06F13/28 , G09G9/36 , G06T15/00 , G06F15/16 , G06F15/78
CPC分类号： G06T15/005
摘要： A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task associated with the high-level host-related task. Each data-generating processing element includes logic configured to receive input data, and logic configured to process the input data to produce output data.
摘要翻译： CPU模块包括被配置为执行高级主机相关任务的主机元件，以及被配置为执行与高级主机相关任务相关联的数据生成任务的一个或多个数据生成处理元件。每个数据生成处理元件包括被配置为接收输入数据的逻辑和被配置为处理输入数据以产生输出数据的逻辑。

8. 发明授权

US4961140A Apparatus and method for extending a parallel synchronous data and message bus 失效
标题翻译：用于扩展并行同步数据和消息总线的装置和方法
公开(公告)号：US4961140A
公开(公告)日：1990-10-02
申请号：US212784
申请日：1988-06-29
申请人： Gerald G. Pechanek , David J. Shippy , Mark C. Snedaker , Sandra S. Woodward
发明人： Gerald G. Pechanek , David J. Shippy , Mark C. Snedaker , Sandra S. Woodward
IPC分类号： G06F13/20 , G06F13/36
CPC分类号： G06F13/36
摘要： An input/output bus for a data processing system which has extended addressing capabilities and a variable length handshake which accommodates the difference delays associated with various sets of logic and a two part address field which allows a bus unit and channel to be identified. The various units can disconnect from the bus during internal processing to free the bus for other activity. The unit removes the busy signal prior to dropping the data lines to allow a bus arbitration sequence to occur without slowing down the bus.

9. 发明授权

US6134699A Method and apparatus for detecting virtual address parity error for a translation lookaside buffer 失效
标题翻译：用于检测翻译后备缓冲器的虚拟地址奇偶校验错误的方法和装置
公开(公告)号：US6134699A
公开(公告)日：2000-10-17
申请号：US16244
申请日：1998-01-30
申请人： James Anthony Steenburgh , Sandra S. Woodward
发明人： James Anthony Steenburgh , Sandra S. Woodward
IPC分类号： G06F11/10 , G06F11/00
CPC分类号： G06F11/1064
摘要： A method and apparatus are provided for detecting virtual address parity error for a translation lookaside buffer in a computer system. The computer system includes a processor unit, a cache coupled to the processor unit, a main memory, and a storage control unit including a translation lookaside buffer (TLB) and a segment lookaside buffer (SLB). A virtual address parity (VAP) is generated for each entry written in the segment lookaside buffer (SLB). A virtual address parity (VAP) is generated for each virtual address entry written in the translation lookaside buffer (TLB). The SLB virtual address parity (VAP) and the TLB virtual address parity (VAP) are utilized for identifying a translation miss condition.
摘要翻译：提供了一种用于检测计算机系统中的翻译后备缓冲器的虚拟地址奇偶校验错误的方法和装置。计算机系统包括处理器单元，耦合到处理器单元的高速缓存器，主存储器和包括转换后备缓冲器（TLB）和段后备缓冲器（SLB）的存储控制单元。为写入片段后备缓冲器（SLB）的每个条目生成虚拟地址奇偶校验（VAP）。为写入翻译后备缓冲器（TLB）的每个虚拟地址条目生成虚拟地址奇偶校验（VAP）。 SLB虚拟地址奇偶校验（VAP）和TLB虚拟地址奇偶校验（VAP）用于识别翻译未命中状态。

10. 发明授权

US4943984A Data processing system parallel data bus having a single oscillator clocking apparatus 失效
标题翻译：具有单个振荡器计时装置的数据处理系统并行数据总线
公开(公告)号：US4943984A
公开(公告)日：1990-07-24
申请号：US211032
申请日：1988-06-24
申请人： Gerald G. Pechanek , David J. Shippy , Mark C. Snedaker , Sandra S. Woodward
发明人： Gerald G. Pechanek , David J. Shippy , Mark C. Snedaker , Sandra S. Woodward
IPC分类号： G06F1/10 , G06F13/42
CPC分类号： G06F13/4217
摘要： A synchronous parallel data bus particularly adapted for use in a data processing system where it is necessary to transfer data over long distances. The physical connection between communicating units includes a plurality of wires adapted to carry the parallel data signal and a wire which carries a clock signal to the remote unit. When data is transmitted from the remote unit to the base unit, the clock signal which originated at the base unit and was transmitted to the remote unit is "turned around" and transmitted back to the base unit for use in receiving the data from the remote unit.

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