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1. 发明授权

US07577794B2 Low latency coherency protocol for a multi-chip multiprocessor system 失效
标题翻译：用于多芯片多处理器系统的低延迟一致性协议
公开(公告)号：US07577794B2
公开(公告)日：2009-08-18
申请号：US10961751
申请日：2004-10-08
申请人： Bruce L. Beukema , Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich , Sandra S. Woodward
发明人： Bruce L. Beukema , Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich , Sandra S. Woodward
IPC分类号： G06F12/00
CPC分类号： G06F12/0828
摘要： Methods and apparatus for reducing the amount of latency involved when accessing, by a remote device, data residing in a cache of a processor are provided. For some embodiments, virtual channels may be utilized to conduct request/response transactions between the remote device and processor that satisfy a set of associated coherency rules.
摘要翻译：提供了用于减少由远程设备访问驻留在处理器的高速缓存中的数据所涉及的等待时间量的方法和装置。对于一些实施例，虚拟信道可以用于在满足一组相关联的一致性规则的远程设备和处理器之间进行请求/响应事务。

2. 发明授权

US07840757B2 Method and apparatus for providing high speed memory for a processing unit 有权
标题翻译：用于为处理单元提供高速存储器的方法和装置
公开(公告)号：US07840757B2
公开(公告)日：2010-11-23
申请号：US10901600
申请日：2004-07-29
申请人： Bruce L. Beukema , Russell D. Hoover , Jon K. Kriegel , Jamie R. Kuesel , Eric O. Mejdrich , Robert A. Shearer , Bruce M. Walk
发明人： Bruce L. Beukema , Russell D. Hoover , Jon K. Kriegel , Jamie R. Kuesel , Eric O. Mejdrich , Robert A. Shearer , Bruce M. Walk
IPC分类号： G06F12/00
CPC分类号： G06F12/0888
摘要： Computer systems with direct updating of cache (e.g., primary L1 cache) memories of a processor, such as a central processing unit (CPU) or graphics processing unit (GPU). Special addresses are reserved for high speed memory. Memory access requests involving these reserved addresses are routed directly to the high speed memory. Memory access requests not involving these reserved addresses are routed to memory external to the processor.
摘要翻译：具有直接更新诸如中央处理单元（CPU）或图形处理单元（GPU）的处理器的高速缓存（例如，主要L1高速缓存）存储器的计算机系统。专用地址保留给高速存储器。涉及这些保留地址的存储器访问请求直接路由到高速存储器。不涉及这些保留地址的存储器访问请求被路由到处理器外部的存储器。

3. 发明授权

US07305524B2 Snoop filter directory mechanism in coherency shared memory system 失效
标题翻译： Snoop过滤器目录机制中的一致性共享内存系统
公开(公告)号：US07305524B2
公开(公告)日：2007-12-04
申请号：US10961749
申请日：2004-10-08
申请人： Russell D. Hoover , Eric O. Mejdrich , Jon K. Kriegel , Sandra S. Woodward
发明人： Russell D. Hoover , Eric O. Mejdrich , Jon K. Kriegel , Sandra S. Woodward
IPC分类号： G06F12/00
CPC分类号： G06F12/0835 , G06F12/0822 , G06F2212/302
摘要： Methods and apparatus that may be utilized to maintain coherency of data accessed by both a processor and a remote device are provided. Various mechanisms, such as a remote cache directory, castout buffer, and/or outstanding transaction buffer may be utilized by the remote device to track the state of processor cache lines that may hold data targeted by requests initiated by the remote device. Based on the content of these mechanisms, requests targeting data that is not in the processor cache may be routed directly to memory, thus reducing overall latency.
摘要翻译：提供了可用于维护由处理器和远程设备访问的数据的一致性的方法和装置。远程设备可以利用各种机制，诸如远程高速缓存目录，转储缓冲区和/或未完成的事务缓冲器来跟踪可以保存由远程设备发起的请求所针对的数据的处理器高速缓存行的状态。基于这些机制的内容，针对不在处理器高速缓存中的数据的请求可以直接路由到存储器，从而减少总体延迟。

4. 发明申请

US20090307714A1 NETWORK ON CHIP WITH AN I/O ACCELERATOR 失效
标题翻译：使用I / O加速器的芯片上的网络
公开(公告)号：US20090307714A1
公开(公告)日：2009-12-10
申请号：US12135364
申请日：2008-06-09
申请人： Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich
发明人： Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich
IPC分类号： G06F9/54
CPC分类号： G06F9/546 , G06F15/7825 , H04L45/00
摘要： Data processing on a network on chip (‘NOC’) that includes IP blocks, routers, memory communications controllers, and network interface controllers; each IP block adapted to a router through a memory communications controller and a network interface controller; each memory communications controller controlling communication between an IP block and memory; each network interface controller controlling inter-IP block communications through routers; each IP block adapted to the network by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox; a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID with each stage executing on a thread of execution on an IP block; and at least one of the IP blocks comprising an input/output (‘I/O’) accelerator that administers at least some data communications traffic to and from the at least one IP block.
摘要翻译：芯片上的数据处理（“NOC”）包括IP块，路由器，存储器通信控制器和网络接口控制器; 每个IP块通过存储器通信控制器和网络接口控制器适应于路由器; 每个存储器通信控制器控制IP块和存储器之间的通信; 每个网络接口控制器通过路由器控制IP间块通信; 每个IP块通过包括收件箱和发件箱的低延迟，高带宽应用消息互连来适应于网络; 每个阶段包括由阶段ID标识的计算机程序指令的灵活可配置模块，每个阶段在IP块上的执行线程上执行; 并且所述IP块中的至少一个包括向所述至少一个IP块执行至少一些数据通信业务的输入/输出（'I / O'）加速器。

5. 发明申请

US20090210592A1 Network On Chip With A Low Latency, High Bandwidth Application Messaging Interconnect 有权
标题翻译：网络片上低延迟，高带宽应用程序消息传递互连
公开(公告)号：US20090210592A1
公开(公告)日：2009-08-20
申请号：US12031733
申请日：2008-02-15
申请人： Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich
发明人： Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich
IPC分类号： G06F13/42 , G06F13/38
CPC分类号： G06F13/4027
摘要： A network on chip (‘NOC’) and methods of data processing on the NOC, the NOC including integrated processor (‘IP’) blocks, a data communications bus (110), memory communications controllers (106), and bus interface controllers (108); each IP block adapted to the data communications bus through a memory communications controller and a bus interface controller; each memory communications controller, in conjunction with one of the bus interface controllers, controlling memory addressed communications between an IP block and memory; each memory communications controller, in conjunction with one of the bus interface controllers, controlling memory addressed communications between one of the IP blocks and other IP blocks; each IP block adapted to the data communications bus by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox.
摘要翻译：片上网络（NOC）和NOC数据处理方法，NOC包括集成处理器（IP）块，数据通信总线（110），存储器通信控制器（106）和总线接口控制器 108）; 每个IP块通过存储器通信控制器和总线接口控制器适应于数据通信总线; 每个存储器通信控制器与一个总线接口控制器一起控制IP块和存储器之间的存储器寻址通信; 每个存储器通信控制器与一个总线接口控制器一起控制IP块和其它IP块之一之间的存储器寻址通信; 每个IP块通过包括收件箱和发件箱的低延迟，高带宽应用消息互连来适应数据通信总线。

6. 发明授权

US08438578B2 Network on chip with an I/O accelerator 失效
标题翻译：使用I / O加速器的网络芯片
公开(公告)号：US08438578B2
公开(公告)日：2013-05-07
申请号：US12135364
申请日：2008-06-09
申请人： Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich
发明人： Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich
IPC分类号： G06F3/00 , G06F9/44 , G06F9/46 , G06F13/00 , G06F15/00
CPC分类号： G06F9/546 , G06F15/7825 , H04L45/00
摘要： Data processing on a network on chip (‘NOC’) that includes IP blocks, routers, memory communications controllers, and network interface controllers; each IP block adapted to a router through a memory communications controller and a network interface controller; each memory communications controller controlling communication between an IP block and memory; each network interface controller controlling inter-IP block communications through routers; each IP block adapted to the network by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox; a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID with each stage executing on a thread of execution on an IP block; and at least one of the IP blocks comprising an input/output (‘I/O’) accelerator that administers at least some data communications traffic to and from the at least one IP block.
摘要翻译：芯片上的数据处理（“NOC”）包括IP块，路由器，存储器通信控制器和网络接口控制器; 每个IP块通过存储器通信控制器和网络接口控制器适应于路由器; 每个存储器通信控制器控制IP块和存储器之间的通信; 每个网络接口控制器通过路由器控制IP间块通信; 每个IP块通过包括收件箱和发件箱的低延迟，高带宽应用消息互连来适应于网络; 每个阶段包括由阶段ID标识的计算机程序指令的灵活可配置模块，每个阶段在IP块上的执行线程上执行; 并且所述IP块中的至少一个包括对至少一个IP块执行至少一些数据通信业务的输入/输出（“I / O”）加速器。

7. 发明申请

US20090210883A1 Network On Chip Low Latency, High Bandwidth Application Messaging Interconnect 有权
标题翻译：网络片上低延迟，高带宽应用程序消息传递互连
公开(公告)号：US20090210883A1
公开(公告)日：2009-08-20
申请号：US12031738
申请日：2008-02-15
申请人： Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich , Robert A. Shearer
发明人： Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich , Robert A. Shearer
IPC分类号： G06F9/54
CPC分类号： G06F15/7825
摘要： Data processing on a network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, each network interface controller controlling inter-IP block communications through routers, with each IP block also adapted to the network by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox.
摘要翻译：包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”）上的数据处理，每个IP块通过存储器通信控制器和网络适配于路由器接口控制器，其中每个存储器通信控制器控制IP块和存储器之间的通信，每个网络接口控制器控制通过路由器的IP间块通信，每个IP块还通过低延迟的高带宽应用消息传送互连来适应于网络，包括收件箱和发件箱。

8. 发明授权

US07913010B2 Network on chip with a low latency, high bandwidth application messaging interconnect 有权
标题翻译：具有低延迟，高带宽应用消息互连的片上网络
公开(公告)号：US07913010B2
公开(公告)日：2011-03-22
申请号：US12031733
申请日：2008-02-15
申请人： Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich
发明人： Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich
IPC分类号： G06F13/00 , G06F13/28 , H04L12/43
CPC分类号： G06F13/4027
摘要： A network on chip (‘NOC’) and methods of data processing on the NOC, the NOC including integrated processor (‘IP’) blocks, a data communications bus (110), memory communications controllers (106), and bus interface controllers (108); each IP block adapted to the data communications bus through a memory communications controller and a bus interface controller; each memory communications controller, in conjunction with one of the bus interface controllers, controlling memory addressed communications between an IP block and memory; each memory communications controller, in conjunction with one of the bus interface controllers, controlling memory addressed communications between one of the IP blocks and other IP blocks; each IP block adapted to the data communications bus by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox.
摘要翻译：片上网络（NOC）和NOC数据处理方法，NOC包括集成处理器（IP）块，数据通信总线（110），存储器通信控制器（106）和总线接口控制器 108）; 每个IP块通过存储器通信控制器和总线接口控制器适应于数据通信总线; 每个存储器通信控制器与一个总线接口控制器一起控制IP块和存储器之间的存储器寻址通信; 每个存储器通信控制器与一个总线接口控制器一起控制IP块和其它IP块之一之间的存储器寻址通信; 每个IP块通过包括收件箱和发件箱的低延迟，高带宽应用消息互连来适应数据通信总线。

9. 发明授权

US08490110B2 Network on chip with a low latency, high bandwidth application messaging interconnect 有权
标题翻译：具有低延迟，高带宽应用消息互连的片上网络
公开(公告)号：US08490110B2
公开(公告)日：2013-07-16
申请号：US12031738
申请日：2008-02-15
申请人： Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich , Robert A. Shearer
发明人： Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich , Robert A. Shearer
IPC分类号： G06F9/44 , G06F15/00
CPC分类号： G06F15/7825
摘要： Data processing on a network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, each network interface controller controlling inter-IP block communications through routers, with each IP block also adapted to the network by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox.
摘要翻译：包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”）上的数据处理，每个IP块通过存储器通信控制器和网络适配于路由器接口控制器，其中每个存储器通信控制器控制IP块和存储器之间的通信，每个网络接口控制器控制通过路由器的IP间块通信，每个IP块还通过低延迟的高带宽应用消息互连互连来适应于网络，包括收件箱和发件箱。

10. 发明申请

US20090125706A1 Software Pipelining on a Network on Chip 审中-公开
标题翻译：网络芯片上的软件流水线
公开(公告)号：US20090125706A1
公开(公告)日：2009-05-14
申请号：US11936873
申请日：2007-11-08
申请人： Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich , Paul E. Schardt
发明人： Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich , Paul E. Schardt
IPC分类号： G06F9/38
CPC分类号： G06F9/5038 , G06F9/30047 , G06F9/3851 , G06F9/3885 , G06F15/7825 , G06F15/8053 , G06F2209/5017
摘要： A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, the NOC also including a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID with each stage executing on a thread of execution on an IP block.
摘要翻译：包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），每个IP块通过存储器通信控制器和网络接口控制器适配于路由器，其中每个存储器通信控制器控制IP块和存储器之间的通信以及控制通过路由器进行IP间块通信的每个网络接口控制器，NOC还包括被分段成阶段的计算机软件应用，每个级包括计算机程序的可灵活配置的模块由阶段ID标识的指令，每个阶段在IP块上的执行线程上执行。

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