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1. 发明申请

US20060253661A1 Distributed address arbitration scheme for symmetrical multiprocessor system 失效
公开(公告)号：US20060253661A1
公开(公告)日：2006-11-09
申请号：US11120909
申请日：2005-05-03
申请人： Brian Bass , Thomas Jeremiah , Charles Johns , David Shippy , Thuong Truong
发明人： Brian Bass , Thomas Jeremiah , Charles Johns , David Shippy , Thuong Truong
IPC分类号： G06F13/00 , G06F12/06
CPC分类号： G06F12/06
摘要： The present invention utilizes the good qualities of a single address concentrator (AC), without any extra chips or wires, and distributes the AC function among the various chips, making use of the fact that each chip in the system has a copy of the AC function therein. Using the distributed address concentrator function, each chip will handle approximately one-fourth of the command traffic and the average latency of servicing the commands will be approximately the same across each chip in the system.

2. 发明申请

US20050080998A1 Method and apparatus for coherent memory structure of heterogeneous processor systems 失效
标题翻译：异构处理器系统的相干存储器结构的方法和装置
公开(公告)号：US20050080998A1
公开(公告)日：2005-04-14
申请号：US10682386
申请日：2003-10-09
申请人： Michael Day , Harm Hofstee , Charles Johns , James Kahle , David Shippy , Thuong Truong
发明人： Michael Day , Harm Hofstee , Charles Johns , James Kahle , David Shippy , Thuong Truong
IPC分类号： G06F12/08
CPC分类号： G06F12/0835
摘要： Disclosed is a coherent cache system that operates in conjunction with non-homogeneous processing units. A set of processing units of a first configuration has conventional cache and directly accesses common or shared system physical and virtual address memory through the use of a conventional MMU (Memory Management Unit). Additional processors of a different configuration and/or other devices that need to access system memory are configured to store accessed data in compatible caches. Each of the caches is compatible with a given protocol coherent memory management bus interspersed between the caches and the system memory.
摘要翻译：公开了与非均匀处理单元结合操作的一致的缓存系统。一组第一配置的处理单元具有常规高速缓存，并且通过使用常规MMU（存储器管理单元）直接访问公用或共享系统物理和虚拟地址存储器。需要访问系统存储器的不同配置和/或其他设备的其他处理器被配置为将访问的数据存储在兼容的高速缓存中。每个缓存与散列在高速缓存和系统存储器之间的给定协议相干存储器管理总线兼容。

3. 发明申请

US20050055505A1 Software-controlled cache set management with software-generated class identifiers 失效
标题翻译：软件控制的缓存集管理与软件生成的类标识符
公开(公告)号：US20050055505A1
公开(公告)日：2005-03-10
申请号：US10655365
申请日：2003-09-04
申请人： Michael Day , Harm Hofstee , Charles Johns , James Kahle , David Shippy , Thuong Truong , Takeshi Yamazaki
发明人： Michael Day , Harm Hofstee , Charles Johns , James Kahle , David Shippy , Thuong Truong , Takeshi Yamazaki
IPC分类号： G06F12/00 , G06F12/12
CPC分类号： G06F12/126
摘要： The present invention provides for selectively overwriting sets of a cache as a function of a replacement management table and a least recently used function. A class identifier is created as a function of an address miss. A replacement management table is employable to read the class identifier to create a tag replacement control indicia. The cache, comprising a plurality of sets, is employable to disable the replacement of at least one of the plurality of sets as a function of the tag replacement control indicia.
摘要翻译：本发明提供了根据替换管理表和最近最少使用的功能来选择性地覆盖高速缓存的集合。根据地址未命中创建类标识符。替换管理表可用于读取类标识符以创建标签替换控制标记。包括多个集合的高速缓存可用于根据标签替换控制标记来禁用对多个集合中的至少一个的替换。

4. 发明申请

US20050055507A1 Software-controlled cache set management 失效
标题翻译：软件控制缓存集管理
公开(公告)号：US20050055507A1
公开(公告)日：2005-03-10
申请号：US10655367
申请日：2003-09-04
申请人： Michael Day , Harm Hofstee , Charles Johns , James Kahle , David Shippy , Thuong Truong , Takeshi Yamazaki
发明人： Michael Day , Harm Hofstee , Charles Johns , James Kahle , David Shippy , Thuong Truong , Takeshi Yamazaki
IPC分类号： G06F12/00 , G06F12/12
CPC分类号： G06F12/126
摘要： The present invention provides for selectively overwriting sets of a cache as a function of a replacement management table and a least recently used function. A class identifier is created as a function of an address miss. A replacement management table is employable to read the class identifier to create a tag replacement control indicia. The cache, comprising a plurality of sets, is employable to disable the replacement of at least one of the plurality of sets as a function of the tag replacement control indicia.
摘要翻译：本发明提供了根据替换管理表和最近最少使用的功能来选择性地覆盖高速缓存的集合。根据地址未命中创建类标识符。替换管理表可用于读取类标识符以创建标签替换控制标记。包括多个集合的高速缓存可用于根据标签替换控制标记来禁用对多个集合中的至少一个的替换。

5. 发明授权

US07900024B2 Handling data cache misses out-of-order for asynchronous pipelines 有权
标题翻译：异步管道处理数据高速缓存无序乱序
公开(公告)号：US07900024B2
公开(公告)日：2011-03-01
申请号：US12253448
申请日：2008-10-17
申请人： Christopher M. Abernathy , Jeffrey P. Bradford , Ronald P. Hall , Timothy H. Heil , David Shippy
发明人： Christopher M. Abernathy , Jeffrey P. Bradford , Ronald P. Hall , Timothy H. Heil , David Shippy
IPC分类号： G06F9/312
CPC分类号： G06F9/30043 , G06F9/3836 , G06F9/384 , G06F9/3859 , G06F9/3861
摘要： Mechanisms for handling data cache misses out-of-order for asynchronous pipelines are provided. The mechanisms associate load tag (LTAG) identifiers with the load instructions and uses them to track the load instruction across multiple pipelines as an index into a load table data structure of a load target buffer. The load table is used to manage cache “hits” and “misses” and to aid in the recycling of data from the L2 cache. With cache misses, the LTAG indexed load table permits load data to recycle from the L2 cache in any order. When the load instruction issues and sees its corresponding entry in the load table marked as a “miss,” the effects of issuance of the load instruction are canceled and the load instruction is stored in the load table for future reissuing to the instruction pipeline when the required data is recycled.
摘要翻译：提供了处理异步管道数据高速缓存未命中的机制。这些机制将负载标签（LTAG）标识符与加载指令相关联，并使用它们来跟踪跨多个管道的加载指令作为加载目标缓冲区的加载表数据结构的索引。加载表用于管理缓存“命中”和“未命中”，并帮助从L2缓存回收数据。由于缓存未命中，LTAG索引的加载表允许加载数据以任何顺序从二级缓存中回收。当加载指令发出并看到其在负载表中的相应条目标记为“未命中”时，发出加载指令的影响被取消，并且加载指令存储在加载表中，以便将来重新发布到指令流水线时所需数据被回收。

6. 发明授权

US07370176B2 System and method for high frequency stall design 失效
标题翻译：高频失速设计系统及方法
公开(公告)号：US07370176B2
公开(公告)日：2008-05-06
申请号：US11204414
申请日：2005-08-16
申请人： Jonathan James DeMent , Kurt Alan Feiste , Robert Alan Philhower , David Shippy
发明人： Jonathan James DeMent , Kurt Alan Feiste , Robert Alan Philhower , David Shippy
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3875
摘要： A system and method for a high frequency stall design is presented. An issue unit includes a first instruction stage, a second instruction stage, and issue control logic. During a first instruction cycle, the issue unit performs two tasks, which are 1) the instructions located in the first instruction stage are moved to a second instruction stage, and 2) the issue control logic determines whether to issue or stall the instructions that are moved to the second instruction stage based upon their particular instruction attributes and the issue control unit's previous state. During a second instruction cycle that immediately follows the first instruction cycle, the second instruction stage's instructions are either issued or stalled based upon the issue control logic's decision from the first instruction cycle.
摘要翻译：提出了一种用于高频失速设计的系统和方法。发行单元包括第一指令阶段，第二指令阶段和发布控制逻辑。在第一指令周期期间，发行单元执行两个任务，即1）位于第一指令阶段的指令移动到第二指令阶段，2）发行控制逻辑确定是否发出或停止指令基于其特定的指令属性和发布控制单元的先前状态，移动到第二指令阶段。在紧随第一指令周期的第二指令周期中，基于从第一指令周期的发布控制逻辑的判定，发出或停止第二指令级的指令。

7. 发明申请

US20070198812A1 Method and apparatus for issuing instructions from an issue queue including a main issue queue array and an auxiliary issue queue array in an information handling system 审中-公开
标题翻译：用于从包括主要问题队列阵列和辅助问题队列阵列在内的问题队列发出指令的方法和装置
公开(公告)号：US20070198812A1
公开(公告)日：2007-08-23
申请号：US11236835
申请日：2005-09-27
申请人： Christopher Abernathy , Jonathan DeMent , Kurt Feiste , David Shippy
发明人： Christopher Abernathy , Jonathan DeMent , Kurt Feiste , David Shippy
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3857
摘要： An information handling system includes a processor that issues instructions out of program order. The processor includes an issue queue that may advance instructions toward issue even though some instructions in the queue are not ready-to-issue. The issue queue includes a main array of storage cells and an auxiliary array of storage cells coupled thereto. When a particular row of the main array includes an instruction that is not ready-to-issue, a stall condition occurs for that instruction. However, to prevent the entire issue queue and processor from stalling, a ready-to-issue instruction in another row of the main array may bypass the row including the stalled or not-ready-to-issue instruction. To effect this bypass, the issue queue moves the ready-to-issue instruction to an issue row of the auxiliary array for issuance to an appropriate execution unit. Out-of-order issuance of instructions to the execution units thus continues despite the stalled instruction.
摘要翻译：信息处理系统包括处理器，其以程序顺序发出指令。处理器包括一个问题队列，即使队列中的某些指令还没有准备就绪，也可能提前发出指令。问题队列包括存储单元的主阵列和与其耦合的存储单元的辅助阵列。当主阵列的特定行包含不能准备发出的指令时，该指令将发生停顿状态。然而，为了防止整个问题队列和处理器停止，主阵列的另一行中的就绪指令可以绕过包括已停止或尚未准备就绪的指令的行。为了实现此旁路，问题队列将准备就绪指令移动到辅助阵列的问题行以发布到适当的执行单元。因此，执行单元的指令的乱序发布仍然停止。

8. 发明申请

US20070118726A1 System and method for dynamically selecting storage instruction performance scheme 审中-公开
标题翻译：动态选择存储指令性能方案的系统和方法
公开(公告)号：US20070118726A1
公开(公告)日：2007-05-24
申请号：US11284681
申请日：2005-11-22
申请人： Christopher Abernathy , Jonathan DeMent , David Shippy , Albert Nordstrand
发明人： Christopher Abernathy , Jonathan DeMent , David Shippy , Albert Nordstrand
IPC分类号： G06F9/44 , G06F13/28
CPC分类号： G06F9/30181 , G06F9/30076 , G06F9/3824 , G06F9/3851 , G06F9/3867
摘要： A system and method for dynamic switching between performance schemes is presented. The software program uses an instruction to indicate whether a pacing performance scheme or a flushing performance scheme is to be used. The selection by the software program is stored in a hardware register that the processor uses to determine whether the pacing or flushing performance scheme is used. After setting the performance scheme, subsequent instructions of the software program will be executed using the selected performance scheme. The pacing performance scheme preemptively stalls an instruction that might overload the queue that stores instructions for the Load/Store Unit (LSU). The flushing performance scheme flushes instructions when the LSU storage queue is overloaded and holds the thread that caused the overflow dormant until the queue is no longer full.
摘要翻译：介绍了性能方案之间动态切换的系统和方法。软件程序使用指令来指示是否使用起搏性能方案或冲洗性能方案。软件程序的选择存储在硬件寄存器中，处理器用来确定是否使用起搏或冲洗性能方案。在设置性能方案之后，将使用所选择的性能方案来执行软件程序的后续指令。起搏性能方案会先预先停止可能使存储针对加载/存储单元（LSU）的指令的队列过载的指令。当LSU存储队列过载时，刷新性能方案会刷新指令，并保持导致溢出休眠的线程，直到队列不再满。

9. 发明申请

US20050044434A1 Power throttling method and apparatus 失效
标题翻译：功率节流方法和装置
公开(公告)号：US20050044434A1
公开(公告)日：2005-02-24
申请号：US10645024
申请日：2003-08-21
申请人： James Kahle , David Shippy , Albert Norstrand
发明人： James Kahle , David Shippy , Albert Norstrand
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F9/30112 , G06F1/3203 , G06F1/3287 , G06F9/30141 , G06F9/30189 , Y02D10/171 , Y02D50/20
摘要： Disclosed is an apparatus which deactivates both the AC as well as the DC component of power for various functions in a CPU. The CPU partitions dataflow registers and arithmetic units such that voltage can be removed from the upper portion of dataflow registers when the software is not utilizing same. Clock signals are also prevented from being applied to these non-utilized components. As an example, if a 64 bit CPU (processor unit) is to be used with both 32 and 64 bit software, the mentioned components may be partitioned in equal sized upper and lower portions. The logic signal for activating the removal of voltage may be obtained from a software-accessible architected control register designated as a machine state register in some CPUs. The same logic may be used in connection with removing voltage and clocks from other specialized functional components such as the floating point unit when software instructions do not presently require same.
摘要翻译：公开了一种对CPU中的各种功能的AC以及DC分量进行停用的装置。 CPU分配数据流寄存器和算术单元，使得当软件不使用相同时，可以从数据流寄存器的上部去除电压。还防止时钟信号被施加到这些未使用的组件。作为示例，如果要使用32位和64位软件的64位CPU（处理器单元），则所提到的组件可以被分成相同大小的上部和下部。用于激活电压去除的逻辑信号可以从在某些CPU中指定为机器状态寄存器的软件可访问的架构控制寄存器获得。当软件指令当前不需要相同时，相同的逻辑可用于从其他专门功能组件（例如浮点单元）中去除电压和时钟。

10. 发明授权

US07953960B2 Method and apparatus for delaying a load miss flush until issuing the dependent instruction 有权
标题翻译：用于延迟负载奇偶校验的方法和装置，直到发出依赖指令
公开(公告)号：US07953960B2
公开(公告)日：2011-05-31
申请号：US11252410
申请日：2005-10-18
申请人： Kurt Alan Feiste , David Scott Ray , David Shippy , Albert James Van Norstrand, Jr.
发明人： Kurt Alan Feiste , David Scott Ray , David Shippy , Albert James Van Norstrand, Jr.
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3859 , G06F9/3861 , G06F9/3867
摘要： A pipeline processor has circuits to detect the presence of a register access instruction in an issue stage of the pipeline. A load-miss occurring at a later stage may cause the register access instruction to be marked with an associated bit. The register access instruction progresses down the pipeline and when the flush stage is reached, the processor checks the associated bit and flushes the register access instruction.
摘要翻译：流水线处理器具有在管线的发布阶段检测寄存器访问指令的存在的电路。在稍后阶段发生的负载丢失可能导致寄存器访问指令被标记有相关位。寄存器访问指令在流水线下进行，当达到flush阶段时，处理器检查相关的位并刷新寄存器访问指令。

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