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1. 发明申请

US20050186802A1 Methods of Forming Openings, And Methods of Forming Container Capacitors 有权
标题翻译：形成开口的方法和形成容器电容器的方法
公开(公告)号：US20050186802A1
公开(公告)日：2005-08-25
申请号：US10783843
申请日：2004-02-20
申请人： Brett Busch , Luan Tran , Ardavan Niroomand , Fred Fishburn , Yoshiki Hishiro , Ulrich Boettiger , Richard Holscher
发明人： Brett Busch , Luan Tran , Ardavan Niroomand , Fred Fishburn , Yoshiki Hishiro , Ulrich Boettiger , Richard Holscher
IPC分类号： H01L21/02 , H01L21/033 , H01L21/302 , H01L21/311 , H01L21/461 , H01L21/8234 , H01L21/8242 , H01L21/8244 , H01L27/108 , H01L29/76
CPC分类号： H01L21/0332 , H01L21/0337 , H01L21/31144 , H01L27/10852 , H01L28/91 , Y10S438/942 , Y10S438/946
摘要： A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking layer. A second patterned photoresist is subsequently formed over the masking layer and utilized during a second etch into the masking layer. The combined first and second etches form openings extending entirely through the masking layer and thus form the masking layer into the patterned mask. The patterned mask can be utilized to form a pattern in a substrate underlying the mask. The pattern formed in the substrate can correspond to an array of capacitor container openings. Capacitor structure can be formed within the openings. The capacitor structures can be incorporated within a DRAM array.
摘要翻译：图案化掩模可以如下形成。在掩模层上形成第一图案化的光致抗蚀剂，并在第一蚀刻进入掩模层期间使用。第一蚀刻延伸到掩模层中的深度不到完全通过掩模层的深度。随后在掩模层上形成第二图案化的光致抗蚀剂，并在第二次蚀刻进入掩模层期间利用。组合的第一和第二蚀刻形成完全延伸穿过掩模层的开口，从而在掩模层中形成掩模层。图案化掩模可以用于在掩模下面的衬底中形成图案。形成在基板中的图案可以对应于电容器容器开口的阵列。可以在开口内形成电容结构。电容器结构可以并入DRAM阵列中。

2. 发明申请

US20060009042A1 Methods of forming openings, and methods of forming container capacitors 失效
公开(公告)号：US20060009042A1
公开(公告)日：2006-01-12
申请号：US11216759
申请日：2005-08-31
申请人： Brett Busch , Luan Tran , Ardavan Niroomand , Fred Fishburn , Yoshiki Hishiro , Ulrich Boettiger , Richard Holscher
发明人： Brett Busch , Luan Tran , Ardavan Niroomand , Fred Fishburn , Yoshiki Hishiro , Ulrich Boettiger , Richard Holscher
IPC分类号： H01L21/302 , H01L21/31
CPC分类号： H01L21/0332 , H01L21/0337 , H01L21/31144 , H01L27/10852 , H01L28/91 , Y10S438/942 , Y10S438/946
摘要： A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking layer. A second patterned photoresist is subsequently formed over the masking layer and utilized during a second etch into the masking layer. The combined first and second etches form openings extending entirely through the masking layer and thus form the masking layer into the patterned mask. The patterned mask can be utilized to form a pattern in a substrate underlying the mask. The pattern formed in the substrate can correspond to an array of capacitor container openings. Capacitor structure can be formed within the openings. The capacitor structures can be incorporated within a DRAM array.

3. 发明申请

US20050269620A1 Capacitor structures, and DRAM arrays 有权
标题翻译：电容结构和DRAM阵列
公开(公告)号：US20050269620A1
公开(公告)日：2005-12-08
申请号：US11187210
申请日：2005-07-22
申请人： Brett Busch , Luan Tran , Ardavan Niroomand , Fred Fishburn , Richard Holscher
发明人： Brett Busch , Luan Tran , Ardavan Niroomand , Fred Fishburn , Richard Holscher
IPC分类号： H01L21/02 , H01L21/033 , H01L21/302 , H01L21/311 , H01L21/461 , H01L21/8234 , H01L21/8242 , H01L21/8244 , H01L27/108 , H01L29/76
CPC分类号： H01L21/0332 , H01L21/0337 , H01L21/31144 , H01L27/10852 , H01L28/91 , Y10S438/942 , Y10S438/946
摘要： A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking layer. A second patterned photoresist is subsequently formed over the masking layer and utilized during a second etch into the masking layer. The combined first and second etches form openings extending entirely through the masking layer and thus form the masking layer into the patterned mask. The patterned mask can be utilized to form a pattern in a substrate underlying the mask. The pattern formed in the substrate can correspond to an array of capacitor container openings. Capacitor structure can be formed within the openings. The capacitor structures can be incorporated within a DRAM array.
摘要翻译：图案化掩模可以如下形成。在掩模层上形成第一图案化的光致抗蚀剂，并在第一蚀刻进入掩模层期间使用。第一蚀刻延伸到掩模层中的深度不到完全通过掩模层的深度。随后在掩模层上形成第二图案化的光致抗蚀剂，并在第二次蚀刻进入掩模层期间利用。组合的第一和第二蚀刻形成完全延伸穿过掩模层的开口，从而在掩模层中形成掩模层。图案化掩模可以用于在掩模下面的衬底中形成图案。形成在基板中的图案可以对应于电容器容器开口的阵列。可以在开口内形成电容结构。电容器结构可以并入DRAM阵列中。

4. 发明申请

US20090294878A1 CIRCUITRY AND GATE STACKS 审中-公开
标题翻译：电路和门架
公开(公告)号：US20090294878A1
公开(公告)日：2009-12-03
申请号：US12537577
申请日：2009-08-07
申请人： Zhiping Yin , Ravi Iyer , Thomas R. Glass , Richard Holscher , Ardavan Niroomand , Linda K. Somerville , Gurtej S. Sandhu
发明人： Zhiping Yin , Ravi Iyer , Thomas R. Glass , Richard Holscher , Ardavan Niroomand , Linda K. Somerville , Gurtej S. Sandhu
IPC分类号： H01L29/78
CPC分类号： H01L21/31144 , H01L21/0276 , H01L21/28123 , H01L21/32139
摘要： The present invention includes semiconductor circuitry. Such circuitry encompasses a metal silicide layer over a substrate and a layer comprising silicon, nitrogen and oxygen in physical contact with the metal silicide layer. The present invention also includes a gate stack which encompasses a polysilicon layer over a substrate, a metal silicide layer over the polysilicon layer, an antireflective material layer over the metal silicide layer, a silicon nitride layer over the antireflective material layer, and a layer of photoresist over the silicon nitride layer, for photolithographically patterning the layer of photoresist to form a patterned masking layer from the layer of photoresist and transferring a pattern from the patterned masking layer to the silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer. The patterned silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer encompass a gate stack.
摘要翻译：本发明包括半导体电路。这种电路包括衬底上的金属硅化物层和与金属硅化物层物理接触的包含硅，氮和氧的层。本发明还包括一个栅极堆叠，其包围衬底上的多晶硅层，多晶硅层上的金属硅化物层，金属硅化物层上的抗反射材料层，抗反射材料层上的氮化硅层，以及一层在氮化硅层上的光致抗蚀剂，用于光刻地图案化该光致抗蚀剂层以从光致抗蚀剂层形成图案化掩模层，并将图案从图案化掩模层转移到氮化硅层，抗反射材料层，金属硅化物层和多晶硅层。图案化氮化硅层，抗反射材料层，金属硅化物层和多晶硅层包围栅极堆叠。

5. 发明授权

US07576400B1 Circuitry and gate stacks 失效
标题翻译：电路和门堆叠
公开(公告)号：US07576400B1
公开(公告)日：2009-08-18
申请号：US09559903
申请日：2000-04-26
申请人： Zhiping Yin , Ravi Iyer , Thomas R. Glass , Richard Holscher , Ardavan Niroomand , Linda K. Somerville , Gurtej S. Sandhu
发明人： Zhiping Yin , Ravi Iyer , Thomas R. Glass , Richard Holscher , Ardavan Niroomand , Linda K. Somerville , Gurtej S. Sandhu
IPC分类号： H01L29/78
CPC分类号： H01L21/31144 , H01L21/0276 , H01L21/28123 , H01L21/32139
摘要： The present invention includes semiconductor circuitry. Such circuitry encompasses a metal silicide layer over a substrate and a layer comprising silicon, nitrogen and oxygen in physical contact with the metal silicide layer. The present invention also includes a gate stack which encompasses a polysilicon layer over a substrate, a metal silicide layer over the polysilicon layer, an antireflective material layer over the metal silicide layer, a silicon nitride layer over the antireflective material layer, and a layer of photoresist over the silicon nitride layer, for photolithographically patterning the layer of photoresist to form a patterned masking layer from the layer of photoresist and transferring a pattern from the patterned masking layer to the silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer. The patterned silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer encompass a gate stack.
摘要翻译：本发明包括半导体电路。这种电路包括衬底上的金属硅化物层和与金属硅化物层物理接触的包含硅，氮和氧的层。本发明还包括一个栅极堆叠，其包围衬底上的多晶硅层，多晶硅层上的金属硅化物层，金属硅化物层上的抗反射材料层，抗反射材料层上的氮化硅层，以及一层在氮化硅层上的光致抗蚀剂，用于光刻地图案化该光致抗蚀剂层以从光致抗蚀剂层形成图案化掩模层，并将图案从图案化掩模层转移到氮化硅层，抗反射材料层，金属硅化物层和多晶硅层。图案化氮化硅层，抗反射材料层，金属硅化物层和多晶硅层包围栅极堆叠。

6. 发明授权

US06461950B2 Semiconductor processing methods, semiconductor circuitry, and gate stacks 有权
标题翻译：半导体处理方法，半导体电路和栅极堆叠
公开(公告)号：US06461950B2
公开(公告)日：2002-10-08
申请号：US09870850
申请日：2001-05-30
申请人： Zhiping Yin , Ravi Iyer , Thomas R. Glass , Richard Holscher , Ardavan Niroomand , Linda K. Somerville , Gurtej S. Sandhu
发明人： Zhiping Yin , Ravi Iyer , Thomas R. Glass , Richard Holscher , Ardavan Niroomand , Linda K. Somerville , Gurtej S. Sandhu
IPC分类号： H01L213205
CPC分类号： H01L21/31144 , H01L21/0276 , H01L21/28123 , H01L21/32139
摘要： In one aspect, the invention includes a semiconductor processing method comprising a) forming a metal silicide layer over a substrate; b) depositing a layer comprising silicon, nitrogen and oxygen over the metal silicide layer; and c) while the layer comprising silicon, nitrogen and oxygen is over the metal silicide layer, annealing the metal silicide layer. In another aspect, the invention includes a gate stack forming method, comprising a) forming a polysilicon layer over a substrate; b) forming a metal silicide layer over the polysilicon layer; c) depositing an antireflective material layer over the metal silicide layer; d) forming a silicon nitride layer over the antireflective material layer; e) forming a layer of photoresist over the silicon nitride layer; f) photolithographically patterning the layer of photoresist to form a patterned masking layer from the layer of photoresist; and g) transferring a pattern from the patterned masking layer to the silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer to pattern the silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer into a gate stack. In yet other aspects, the invention encompasses circuitry and gate stacks.
摘要翻译：一方面，本发明包括一种半导体处理方法，包括：a）在衬底上形成金属硅化物层; b）在所述金属硅化物层上沉积包含硅，氮和氧的层; 和c）当包含硅，氮和氧的层在金属硅化物层之上时，退火金属硅化物层。在另一方面，本发明包括一种栅堆叠形成方法，包括：a）在衬底上形成多晶硅层; b）在所述多晶硅层上形成金属硅化物层; c）在所述金属硅化物层上沉积抗反射材料层; d）在抗反射材料层上形成氮化硅层; e）在氮化硅层上形成光致抗蚀剂层; f）光刻地图案化所述光致抗蚀剂层以从所述光致抗蚀剂层形成图案化掩模层; 并且g）将图案从图案化掩模层转移到氮化硅层，抗反射材料层，金属硅化物层和多晶硅层，以将氮化硅层，抗反射材料层，金属硅化物层和多晶硅层图案化成栅叠层。在另一方面，本发明包括电路和栅极堆叠。

7. 发明授权

US06281100B1 Semiconductor processing methods 有权
标题翻译：半导体加工方法
公开(公告)号：US06281100B1
公开(公告)日：2001-08-28
申请号：US09146842
申请日：1998-09-03
申请人： Zhiping Yin , Ravi Iyer , Thomas R. Glass , Richard Holscher , Ardavan Niroomand , Linda K. Somerville , Gurtej S. Sandhu
发明人： Zhiping Yin , Ravi Iyer , Thomas R. Glass , Richard Holscher , Ardavan Niroomand , Linda K. Somerville , Gurtej S. Sandhu
IPC分类号： H01L213205
CPC分类号： H01L21/31144 , H01L21/0276 , H01L21/28123 , H01L21/32139
摘要： In one aspect, the invention includes a semiconductor processing method comprising a) forming a metal silicide layer over a substrate; b) depositing a layer comprising silicon, nitrogen and oxygen over the metal silicide layer; and c) while the layer comprising silicon, nitrogen and oxygen is over the metal silicide layer, annealing the metal silicide layer. In another aspect, the invention includes a gate stack forming method, comprising a) forming a polysilicon layer over a substrate; b) forming a metal silicide layer over the polysilicon layer; c) depositing an antireflective material layer over the metal silicide layer; d) forming a silicon nitride layer over the antireflective material layer; e) forming a layer of photoresist over the silicon nitride layer; f) photolithographically patterning the layer of photoresist to form a patterned masking layer from the layer of photoresist; and g) transferring a pattern from the patterned masking layer to the silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer to pattern the silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer into a gate stack. In yet other aspects, the invention encompasses circuitry and gate stacks.
摘要翻译：一方面，本发明包括一种半导体处理方法，包括：a）在衬底上形成金属硅化物层; b）在所述金属硅化物层上沉积包含硅，氮和氧的层; 和c）当包含硅，氮和氧的层在金属硅化物层之上时，退火金属硅化物层。在另一方面，本发明包括一种栅堆叠形成方法，包括：a）在衬底上形成多晶硅层; b）在所述多晶硅层上形成金属硅化物层; c）在所述金属硅化物层上沉积抗反射材料层; d）在抗反射材料层上形成氮化硅层; e）在氮化硅层上形成光致抗蚀剂层; f）光刻地图案化所述光致抗蚀剂层以从所述光致抗蚀剂层形成图案化掩模层; 并且g）将图案从图案化掩模层转移到氮化硅层，抗反射材料层，金属硅化物层和多晶硅层，以将氮化硅层，抗反射材料层，金属硅化物层和多晶硅层图案化成栅叠层。在另一方面，本发明包括电路和栅极堆叠。

8. 发明申请

US20070238035A1 Method and apparatus defining a color filter array for an image sensor 审中-公开
标题翻译：定义用于图像传感器的滤色器阵列的方法和装置
公开(公告)号：US20070238035A1
公开(公告)日：2007-10-11
申请号：US11399314
申请日：2006-04-07
申请人： Richard Holscher , Ulrich Boettiger
发明人： Richard Holscher , Ulrich Boettiger
IPC分类号： G02B5/20 , H01L31/0232 , H01L31/00
CPC分类号： H01L27/14621 , H01L27/14623 , H01L31/02162 , H01L31/02164
摘要： An apparatus and method to provide an imager having an array of color filter elements, each color filter element being separated from each other by spacers. The spacers can optically isolate filter elements from each other.
摘要翻译：一种提供具有滤色器元件阵列的成像器的装置和方法，每个滤色器元件通过间隔物彼此分离。间隔物可以将过滤元件彼此光学隔离。

9. 发明申请

US20120273905A1 CFA RESIST SILYLATION FOR LIMITING COLOR INTERACTIONS AND IMPROVING CROSSTALK 有权
标题翻译：用于限制颜色相互作用和改进CROSSTALK的CFA耐腐蚀SILYLATION
公开(公告)号：US20120273905A1
公开(公告)日：2012-11-01
申请号：US13223594
申请日：2011-09-01
申请人： Brian Vaartstra , Richard Holscher
发明人： Brian Vaartstra , Richard Holscher
IPC分类号： H01L31/0232 , H01L31/18
CPC分类号： H01L27/14621 , H04N9/045
摘要： An electronic imager includes a pixel sensor array, a plurality elements of a color filter array containing pigments forming multiple color filter patterns on the pixel sensor array and a silylating agent formed between at least first and second elements of the multiple color filter patterns. A method for forming a color filter array on a pixel sensor array of an electronic imager includes forming a pixel sensor array on a substrate, forming a first color filter pattern on the pixel sensor array, depositing a silylating agent on the first color filter pattern, disposing elements of a second color filter pattern on the silylating agent between respective elements of the first color filter pattern and disposing elements of a third color filter pattern on the silylating agent between respective elements of the first color filter pattern.
摘要翻译：电子成像器包括像素传感器阵列，滤色器阵列的多个元件，其包含在像素传感器阵列上形成多个滤色器图案的颜料和形成在多个滤色器图案的至少第一和第二元素之间的甲硅烷化剂。一种用于在电子成像器的像素传感器阵列上形成滤色器阵列的方法包括在衬底上形成像素传感器阵列，在像素传感器阵列上形成第一滤色器图案，在第一滤色器图案上沉积甲硅烷化剂，将第二滤色器图案的元件设置在第一滤色器图案的各个元件之间的甲硅烷化剂上，并且在第一滤色器图案的各个元件之间的甲硅烷化剂上设置第三滤色器图案的元件。

10. 发明授权

US07626238B2 Semiconductor devices having antireflective material 失效
标题翻译：具有抗反射材料的半导体器件
公开(公告)号：US07626238B2
公开(公告)日：2009-12-01
申请号：US11218045
申请日：2005-08-31
申请人： Richard Holscher , Zhiping Yin , Tom Glass
发明人： Richard Holscher , Zhiping Yin , Tom Glass
IPC分类号： H01L31/0232
CPC分类号： H01L21/0276 , G03F7/091 , H01L21/3086 , Y10S430/151
摘要： In one aspect, the invention includes a semiconductor processing method. An antireflective material layer is formed over a substrate. At least a portion of the antireflective material layer is annealed at a temperature of greater than about 400° C. A layer of photoresist is formed over the annealed antireflective material layer. The layer of photoresist is patterned. A portion of the antireflective material layer unmasked by the patterned layer of photoresist is removed. In another aspect, the invention includes the following semiconductor processing. An antireflective material layer is formed over a substrate. The antireflective material layer is annealed at a temperature of greater than about 400° C. A layer of photoresist is formed over the annealed antireflective material layer. Portions of the layer of photoresist are exposed to radiation waves. Some of the radiation waves are absorbed by the antireflective material during the exposing.
摘要翻译：一方面，本发明包括半导体处理方法。在基板上形成防反射材料层。抗反射材料层的至少一部分在大于约400℃的温度下退火。在退火的抗反射材料层上形成一层光致抗蚀剂。图案化光刻胶层。除去由图案化的光致抗蚀剂层掩蔽的抗反射材料层的一部分。另一方面，本发明包括以下半导体处理。在基板上形成防反射材料层。抗反射材料层在大于约400℃的温度下退火。在退火的抗反射材料层上形成一层光致抗蚀剂。光致抗蚀剂层的一部分暴露于辐射波。一些辐射波在曝光期间被抗反射材料吸收。

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