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1. 发明授权

US10110586B1 Rapid social onboarding 有权
公开(公告)号：US10110586B1
公开(公告)日：2018-10-23
申请号：US15417662
申请日：2017-01-27
申请人： Ravi Iyer
发明人： Ravi Iyer
IPC分类号： G06F7/04 , H04L29/06 , G06F17/30 , H04L12/26 , G06Q50/00
摘要： A method may include identifying a candidate user based on a connection to an established user of a business management application (BMA). The candidate user may have an associated user identifier. The method may further include collecting, using the user identifier, social network data of the candidate user from an online social network, identifying, using the social network data of the candidate user, application programming interfaces (APIs) for collecting public data about the candidate user, retrieving, using the user identifier and an API, public data corresponding to the candidate user, generating, using the public data corresponding to the candidate user, an account creation request including the user identifier, and transmitting the account creation request to the BMA.

2. 发明授权

US07867845B2 Transistor gate forming methods and transistor structures 有权
标题翻译：晶体管栅极形成方法和晶体管结构
公开(公告)号：US07867845B2
公开(公告)日：2011-01-11
申请号：US11219077
申请日：2005-09-01
申请人： Sanh D. Tang , Gordon A. Haller , Prashant Raghu , Ravi Iyer
发明人： Sanh D. Tang , Gordon A. Haller , Prashant Raghu , Ravi Iyer
IPC分类号： H01L29/76
CPC分类号： H01L29/78696 , H01L29/42392 , H01L29/66787
摘要： A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.
摘要翻译：晶体管栅极形成方法包括在线路开口内形成金属层，并在金属层的开口内形成填充层。填充层相对于金属层基本上可选择性地蚀刻。晶体管结构包括线路开口，开口内的电介质层，开口内的电介质层上的金属层，以及开口内的金属层上的填充层。如果填充层被金属层的增加的厚度代替，则金属层/填充层组合的内在特性小于否则会存在。本发明至少应用于三维晶体管结构。

3. 发明授权

US07763327B2 Methods using ozone for CVD deposited films 失效
标题翻译：臭氧用于CVD沉积膜的方法
公开(公告)号：US07763327B2
公开(公告)日：2010-07-27
申请号：US11192326
申请日：2005-07-27
申请人： Gurtej S. Sandhu , Ravi Iyer
发明人： Gurtej S. Sandhu , Ravi Iyer
IPC分类号： B05D3/06
CPC分类号： C23C16/401
摘要： A CVD ozone (O3) deposition process, with the preferred embodiment comprising the steps of disposing a substrate in a chemical vapor deposition chamber and exposing the substrate surface to a SiO2 precursor gas, a carrier gas, and optionally a dopant gas in the presence of ozone and exposing the reaction volume of the 5 gases above the substrate surface to a high intensity light source, to increase the functional atomic oxygen concentration and reduce the fixed charge in the deposited films.
摘要翻译： CVD臭氧（O3）沉积方法，优选实施方案包括以下步骤：在化学气相沉积室中设置衬底，并将衬底表面暴露于SiO 2前体气体，载气和任选的掺杂气体中，臭氧，并将基板表面上方的5种气体的反应体积暴露于高强度光源，以增加功能原子氧浓度并降低沉积膜中的固定电荷。

4. 发明授权

US07620071B2 Packet coalescing 有权
标题翻译：分组聚合
公开(公告)号：US07620071B2
公开(公告)日：2009-11-17
申请号：US10991239
申请日：2004-11-16
申请人： Srihari Makineni , Ravi Iyer , Dave Minturn , Sujoy Sen , Donald Newell , Li Zhao
发明人： Srihari Makineni , Ravi Iyer , Dave Minturn , Sujoy Sen , Donald Newell , Li Zhao
IPC分类号： H04J3/24
CPC分类号： H04L45/74 , H04L49/20 , H04L69/16 , H04L69/161 , H04L69/166
摘要： In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.
摘要翻译：一般来说，一方面，本公开内容描述了一种方法，其包括接收多个入口因特网协议分组，所述多个入口因特网协议分组中的每一个具有因特网协议报头和具有传输控制协议报头和传输控制的传输控制协议段协议有效载荷，其中属于相同传输控制协议/因特网协议的多个分组流。该方法还包括准备具有单个因特网协议报头的互联网协议分组和具有单个传输控制协议报头的单个传输控制协议段和由多个因特网协议分组的传输控制协议段有效载荷的组合形成的单个有效载荷。该方法还包括产生导致因特网协议分组的接收处理的信号。

5. 发明申请

US20090239366A1 Method Of Forming A Transistor Gate Of A Recessed Access Device, Method Of Forming A Recessed Transistor Gate And A Non-Recessed Transistor Gate, And Method Of Fabricating An Integrated Circuit 有权
标题翻译：形成嵌入式接入装置的晶体管栅极的方法，形成嵌入式晶体管栅极和非嵌入晶体管栅极的方法以及制造集成电路的方法
公开(公告)号：US20090239366A1
公开(公告)日：2009-09-24
申请号：US12476364
申请日：2009-06-02
申请人： Hasan Nejad , Thomas A. Figura , Gordon A. Haller , Ravi Iyer , John Mark Meldrim , Justin Harnish
发明人： Hasan Nejad , Thomas A. Figura , Gordon A. Haller , Ravi Iyer , John Mark Meldrim , Justin Harnish
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823418 , H01L21/823443 , H01L21/823814 , H01L27/10852 , H01L27/10876 , H01L27/10897 , H01L29/4975 , H01L29/66621 , H01L2924/0002 , H01L2924/00
摘要： Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon within the trench is allowed to fully silicide without void formation, despite a relatively high aspect ratio for the trench. Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays.
摘要翻译：为嵌入硅完全硅化提供了方法和结构。在沟槽内提供硅。在硅上提供了一种金属混合物，其中一种金属在硅中比硅中更容易扩散到金属中，而另一种金属在硅中比在金属中的硅更容易扩散。示例性的混合物包括80％的镍和20％的钴。尽管沟槽的纵横比相对较高，但沟槽内的硅可以完全无硅化物形成。在其他设备中，可以通过用于存储器阵列的方法形成凹陷接入设备（RAD）。

6. 发明授权

US07557032B2 Silicided recessed silicon 有权
标题翻译：硅胶凹槽硅
公开(公告)号：US07557032B2
公开(公告)日：2009-07-07
申请号：US11219303
申请日：2005-09-01
申请人： Hasan Nejad , Thomas A. Figura , Gordon A. Haller , Ravi Iyer , John Mark Meldrim , Justin Harnish
发明人： Hasan Nejad , Thomas A. Figura , Gordon A. Haller , Ravi Iyer , John Mark Meldrim , Justin Harnish
IPC分类号： H01L21/4763
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823418 , H01L21/823443 , H01L21/823814 , H01L27/10852 , H01L27/10876 , H01L27/10897 , H01L29/4975 , H01L29/66621 , H01L2924/0002 , H01L2924/00
摘要： Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon within the trench is allowed to fully silicide without void formation, despite a relatively high aspect ratio for the trench. Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays.
摘要翻译：为嵌入硅完全硅化提供了方法和结构。在沟槽内提供硅。在硅上提供了一种金属混合物，其中一种金属在硅中比硅中更容易扩散到金属中，而另一种金属在硅中比在金属中的硅更容易扩散。示例性的混合物包括80％的镍和20％的钴。尽管沟槽的纵横比相对较高，但沟槽内的硅可以完全无硅化物形成。在其他设备中，可以通过用于存储器阵列的方法形成凹陷接入设备（RAD）。

7. 发明申请

US20070048946A1 Transistor gate forming methods and integrated circuits 有权
标题翻译：晶体管栅极形成方法和集成电路
公开(公告)号：US20070048946A1
公开(公告)日：2007-03-01
申请号：US11219079
申请日：2005-09-01
申请人： D. V. Ramaswamy , Ravi Iyer
发明人： D. V. Ramaswamy , Ravi Iyer
IPC分类号： H01L21/336
CPC分类号： H01L21/28088 , H01L21/823842 , H01L29/78
摘要： A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal layer. The lower metal layer of the first gate originates from an as-deposited material exhibiting a work function the same as exhibited in an as-deposited material from which the lower metal layer of the second gate originates. However, the first gate's lower metal layer exhibits a modified work function different from a work function exhibited by the second gate's lower metal layer. The first gate's lower metal layer may contain less oxygen and/or carbon in comparison to the second gate's lower metal layer. The first gate's lower metal layer may contain more nitrogen in comparison to the second gate's lower metal layer. The first gate may be a n-channel gate and the second gate may be a p-channel gate.
摘要翻译：晶体管栅极形成方法包括形成第一和第二晶体管栅极。两个栅极中的每一个包括下金属层和上金属层。第一栅极的下金属层源自表现出与第二栅极的下金属层源自的沉积材料所表现的功函数相同的功函数的沉积材料。然而，第一栅极的下部金属层表现出与第二栅极的下部金属层所表现的功函数不同的修正功函数。与第二栅极的下金属层相比，第一栅极的下金属层可以含有较少的氧和/或碳。与第二栅极的下金属层相比，第一栅极的下金属层可以含有更多的氮。第一栅极可以是n沟道栅极，第二栅极可以是p沟道栅极。

8. 发明授权

US07112542B2 Methods of forming materials between conductive electrical components, and insulating materials 有权
标题翻译：在导电电气部件和绝缘材料之间形成材料的方法
公开(公告)号：US07112542B2
公开(公告)日：2006-09-26
申请号：US10330719
申请日：2002-12-27
申请人： Werner Juengling , Kirk D. Prall , Ravi Iyer , Gurtej S. Sandhu , Guy Blalock
发明人： Werner Juengling , Kirk D. Prall , Ravi Iyer , Gurtej S. Sandhu , Guy Blalock
IPC分类号： H01L21/31 , H01L21/469 , H01L21/76
CPC分类号： H01L21/7682 , H01L21/02115 , H01L21/02118 , H01L21/02167 , H01L21/02203 , H01L21/02274 , H01L21/02282 , H01L21/02362 , H01L21/31695 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76834 , H01L23/5222 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , Y10T428/12014 , Y10T428/24149 , Y10T428/249921 , Y10T428/25 , Y10T428/259 , H01L2924/00
摘要： Methods of forming insulating materials between conductive elements include forming a material adjacent a conductive electrical component comprising: partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. Other methods include forming a material between a pair of conductive electrical components comprising: forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components. Some embodiments include an insulating material adjacent a conductive electrical component, such material comprising a matrix and at least one void within the matrix.
摘要翻译：在导电元件之间形成绝缘材料的方法包括形成邻近导电电气部件的材料，该材料包括：部分蒸发物质以形成邻近导电电气部件的基体，所述基体在其内具有至少一个空隙。其他方法包括在一对导电电气部件之间形成材料，包括：在一个质量块内形成一对导电的电气部件，并由该质量块的一大片分隔; 在所述物体的宽度内形成至少一个支撑构件，所述支撑构件不包括导电互连; 以及使所述质量块的膨胀程度有效地在所述支撑构件和所述一对导电电气部件中的每一个之间形成至少一个空隙。一些实施例包括邻近导电电气部件的绝缘材料，这种材料包括基质和基质内的至少一个空隙。

9. 发明授权

US07037829B2 Compound structure for reduced contact resistance 有权
公开(公告)号：US07037829B2
公开(公告)日：2006-05-02
申请号：US10355667
申请日：2003-01-31
申请人： Ravi Iyer , Yongjun Jeff Hu , Luan Tran , Brent Gilgen
发明人： Ravi Iyer , Yongjun Jeff Hu , Luan Tran , Brent Gilgen
IPC分类号： H01L21/44
CPC分类号： H01L21/76846 , H01L21/2855 , H01L21/28556 , H01L21/76849 , H01L21/76855 , H01L21/7687 , H01L21/76889 , H01L23/485 , H01L27/10855 , H01L28/84 , H01L28/90 , H01L29/456 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first refractory metal material. Each refractory metal material is a conductive material containing a refractory metal and an impurity. The first refractory metal material is a metal-rich material, containing a level of its impurity at less than a stoichiometric level. The second refractory metal material has a lower affinity for the impurities than does the first refractory metal material. The second refractory metal material can thus serve as an impurity donor during an anneal or other exposure to heat. This net migration of the impurities to the first refractory metal material limits growth of a metal silicide interface between the first refractory metal material and the underlying silicon-containing material, thereby providing ohmic contact with attendant thermal tolerance.

10. 发明授权

US06977225B2 Chemical vapor deposition of titanium from titanium tetrachloride and hydrocarbon reactants 失效
标题翻译：来自四氯化钛和烃反应物的钛的化学气相沉积
公开(公告)号：US06977225B2
公开(公告)日：2005-12-20
申请号：US10706244
申请日：2003-11-12
申请人： Ravi Iyer , Sujit Sharan
发明人： Ravi Iyer , Sujit Sharan
IPC分类号： H01L21/285 , H01L21/44
CPC分类号： C23C16/08 , H01L21/28556 , H01L21/28568 , Y10S438/909
摘要： A new process for depositing titanium metal layers via chemical vapor deposition is disclosed. The process provides deposited titanium layers having a high degree of conformality, even in trenches and contact openings having aspect ratios greater than 1:5.
摘要翻译：公开了一种通过化学气相沉积沉积钛金属层的新工艺。该方法即使在具有大于1:5的纵横比的沟槽和接触开口中也提供具有高度保形性的沉积钛层。

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