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1. 发明授权

US06335531B1 Modification of resist and/or resist processing with fluorescence detection 失效
标题翻译：用荧光检测改性抗蚀剂和/或抗蚀剂加工
公开(公告)号：US06335531B1
公开(公告)日：2002-01-01
申请号：US09291652
申请日：1999-04-06
申请人： Linda K. Somerville , Richard D. Holscher , Kenneth H. Somerville
发明人： Linda K. Somerville , Richard D. Holscher , Kenneth H. Somerville
IPC分类号： G01J158
CPC分类号： G03F7/40
摘要： The detectability of photoresist is enhanced through the addition of materials to enhance the fluorescence of photoresist such that residual photoresist that either does not fluoresce or fluoresces at an emission wavelength shorter that that which can be detected using existing automatic resist inspection tools. In one embodiment of the invention, a benign tag that does not interfere with the photochemistry of the photoresist is added to the photoresist before it is processed. In a second embodiment of the invention, a tag is introduced onto a surface on which residual photoresist may be present such that the tag is absorbed or adsorbed by the residual photoresist, thereby rendering the residual photoresist easily detectable. The tag may be introduced onto the surface in a solution.
摘要翻译：通过添加材料以增强光致抗蚀剂的荧光，增强了光致抗蚀剂的可检测性，使得残留光致抗蚀剂在发射波长上不发荧光或发荧光短于使用现有的自动抗蚀剂检查工具可以检测到的光致抗蚀剂。在本发明的一个实施方案中，在光致抗蚀剂被处理之前，将不影响光致抗蚀剂的光化学的良性标签加入到光致抗蚀剂中。在本发明的第二实施例中，将标签引入到可以存在残留光致抗蚀剂的表面上，使得标签被残留的光致抗蚀剂吸收或吸收，从而使残留的光致抗蚀剂容易检测。标签可以在溶液中引入到表面上。

2. 发明授权

US07576400B1 Circuitry and gate stacks 失效
标题翻译：电路和门堆叠
公开(公告)号：US07576400B1
公开(公告)日：2009-08-18
申请号：US09559903
申请日：2000-04-26
申请人： Zhiping Yin , Ravi Iyer , Thomas R. Glass , Richard Holscher , Ardavan Niroomand , Linda K. Somerville , Gurtej S. Sandhu
发明人： Zhiping Yin , Ravi Iyer , Thomas R. Glass , Richard Holscher , Ardavan Niroomand , Linda K. Somerville , Gurtej S. Sandhu
IPC分类号： H01L29/78
CPC分类号： H01L21/31144 , H01L21/0276 , H01L21/28123 , H01L21/32139
摘要： The present invention includes semiconductor circuitry. Such circuitry encompasses a metal silicide layer over a substrate and a layer comprising silicon, nitrogen and oxygen in physical contact with the metal silicide layer. The present invention also includes a gate stack which encompasses a polysilicon layer over a substrate, a metal silicide layer over the polysilicon layer, an antireflective material layer over the metal silicide layer, a silicon nitride layer over the antireflective material layer, and a layer of photoresist over the silicon nitride layer, for photolithographically patterning the layer of photoresist to form a patterned masking layer from the layer of photoresist and transferring a pattern from the patterned masking layer to the silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer. The patterned silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer encompass a gate stack.
摘要翻译：本发明包括半导体电路。这种电路包括衬底上的金属硅化物层和与金属硅化物层物理接触的包含硅，氮和氧的层。本发明还包括一个栅极堆叠，其包围衬底上的多晶硅层，多晶硅层上的金属硅化物层，金属硅化物层上的抗反射材料层，抗反射材料层上的氮化硅层，以及一层在氮化硅层上的光致抗蚀剂，用于光刻地图案化该光致抗蚀剂层以从光致抗蚀剂层形成图案化掩模层，并将图案从图案化掩模层转移到氮化硅层，抗反射材料层，金属硅化物层和多晶硅层。图案化氮化硅层，抗反射材料层，金属硅化物层和多晶硅层包围栅极堆叠。

3. 发明授权

US06580493B2 Method and apparatus for exposing semiconductor wafers in a manner that promotes radial processing uniformity 有权
公开(公告)号：US06580493B2
公开(公告)日：2003-06-17
申请号：US10008108
申请日：2001-11-13
申请人： Richard D. Holscher , Linda K. Somerville
发明人： Richard D. Holscher , Linda K. Somerville
IPC分类号： G03B2742
CPC分类号： G03F7/70091 , G03F7/701 , G03F7/70466
摘要： A stepper device and method of using the stepper device in which a light source in the stepper generates an annular or multipole pattern of light having a relatively large coherency value that is used to expose inner fields of a photoresist-coated wafer. The light source generates an annular or multipole pattern of light having a relatively small coherency that is used to expose outer fields of the wafer adjacent its edge. The use of light having a relatively small coherence value to expose the outer fields of the wafer causes the exposure width of isolated features to be relatively large compared to the exposure width of dense features. As a result, after etching, the isolated features and the dense features can have the same width since etching is more effective for dense features.

4. 发明授权

US06461950B2 Semiconductor processing methods, semiconductor circuitry, and gate stacks 有权
标题翻译：半导体处理方法，半导体电路和栅极堆叠
公开(公告)号：US06461950B2
公开(公告)日：2002-10-08
申请号：US09870850
申请日：2001-05-30
申请人： Zhiping Yin , Ravi Iyer , Thomas R. Glass , Richard Holscher , Ardavan Niroomand , Linda K. Somerville , Gurtej S. Sandhu
发明人： Zhiping Yin , Ravi Iyer , Thomas R. Glass , Richard Holscher , Ardavan Niroomand , Linda K. Somerville , Gurtej S. Sandhu
IPC分类号： H01L213205
CPC分类号： H01L21/31144 , H01L21/0276 , H01L21/28123 , H01L21/32139
摘要： In one aspect, the invention includes a semiconductor processing method comprising a) forming a metal silicide layer over a substrate; b) depositing a layer comprising silicon, nitrogen and oxygen over the metal silicide layer; and c) while the layer comprising silicon, nitrogen and oxygen is over the metal silicide layer, annealing the metal silicide layer. In another aspect, the invention includes a gate stack forming method, comprising a) forming a polysilicon layer over a substrate; b) forming a metal silicide layer over the polysilicon layer; c) depositing an antireflective material layer over the metal silicide layer; d) forming a silicon nitride layer over the antireflective material layer; e) forming a layer of photoresist over the silicon nitride layer; f) photolithographically patterning the layer of photoresist to form a patterned masking layer from the layer of photoresist; and g) transferring a pattern from the patterned masking layer to the silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer to pattern the silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer into a gate stack. In yet other aspects, the invention encompasses circuitry and gate stacks.
摘要翻译：一方面，本发明包括一种半导体处理方法，包括：a）在衬底上形成金属硅化物层; b）在所述金属硅化物层上沉积包含硅，氮和氧的层; 和c）当包含硅，氮和氧的层在金属硅化物层之上时，退火金属硅化物层。在另一方面，本发明包括一种栅堆叠形成方法，包括：a）在衬底上形成多晶硅层; b）在所述多晶硅层上形成金属硅化物层; c）在所述金属硅化物层上沉积抗反射材料层; d）在抗反射材料层上形成氮化硅层; e）在氮化硅层上形成光致抗蚀剂层; f）光刻地图案化所述光致抗蚀剂层以从所述光致抗蚀剂层形成图案化掩模层; 并且g）将图案从图案化掩模层转移到氮化硅层，抗反射材料层，金属硅化物层和多晶硅层，以将氮化硅层，抗反射材料层，金属硅化物层和多晶硅层图案化成栅叠层。在另一方面，本发明包括电路和栅极堆叠。

5. 发明授权

US06281100B1 Semiconductor processing methods 有权
标题翻译：半导体加工方法
公开(公告)号：US06281100B1
公开(公告)日：2001-08-28
申请号：US09146842
申请日：1998-09-03
申请人： Zhiping Yin , Ravi Iyer , Thomas R. Glass , Richard Holscher , Ardavan Niroomand , Linda K. Somerville , Gurtej S. Sandhu
发明人： Zhiping Yin , Ravi Iyer , Thomas R. Glass , Richard Holscher , Ardavan Niroomand , Linda K. Somerville , Gurtej S. Sandhu
IPC分类号： H01L213205
CPC分类号： H01L21/31144 , H01L21/0276 , H01L21/28123 , H01L21/32139
摘要： In one aspect, the invention includes a semiconductor processing method comprising a) forming a metal silicide layer over a substrate; b) depositing a layer comprising silicon, nitrogen and oxygen over the metal silicide layer; and c) while the layer comprising silicon, nitrogen and oxygen is over the metal silicide layer, annealing the metal silicide layer. In another aspect, the invention includes a gate stack forming method, comprising a) forming a polysilicon layer over a substrate; b) forming a metal silicide layer over the polysilicon layer; c) depositing an antireflective material layer over the metal silicide layer; d) forming a silicon nitride layer over the antireflective material layer; e) forming a layer of photoresist over the silicon nitride layer; f) photolithographically patterning the layer of photoresist to form a patterned masking layer from the layer of photoresist; and g) transferring a pattern from the patterned masking layer to the silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer to pattern the silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer into a gate stack. In yet other aspects, the invention encompasses circuitry and gate stacks.
摘要翻译：一方面，本发明包括一种半导体处理方法，包括：a）在衬底上形成金属硅化物层; b）在所述金属硅化物层上沉积包含硅，氮和氧的层; 和c）当包含硅，氮和氧的层在金属硅化物层之上时，退火金属硅化物层。在另一方面，本发明包括一种栅堆叠形成方法，包括：a）在衬底上形成多晶硅层; b）在所述多晶硅层上形成金属硅化物层; c）在所述金属硅化物层上沉积抗反射材料层; d）在抗反射材料层上形成氮化硅层; e）在氮化硅层上形成光致抗蚀剂层; f）光刻地图案化所述光致抗蚀剂层以从所述光致抗蚀剂层形成图案化掩模层; 并且g）将图案从图案化掩模层转移到氮化硅层，抗反射材料层，金属硅化物层和多晶硅层，以将氮化硅层，抗反射材料层，金属硅化物层和多晶硅层图案化成栅叠层。在另一方面，本发明包括电路和栅极堆叠。

6. 发明申请

US20090294878A1 CIRCUITRY AND GATE STACKS 审中-公开
标题翻译：电路和门架
公开(公告)号：US20090294878A1
公开(公告)日：2009-12-03
申请号：US12537577
申请日：2009-08-07
申请人： Zhiping Yin , Ravi Iyer , Thomas R. Glass , Richard Holscher , Ardavan Niroomand , Linda K. Somerville , Gurtej S. Sandhu
发明人： Zhiping Yin , Ravi Iyer , Thomas R. Glass , Richard Holscher , Ardavan Niroomand , Linda K. Somerville , Gurtej S. Sandhu
IPC分类号： H01L29/78
CPC分类号： H01L21/31144 , H01L21/0276 , H01L21/28123 , H01L21/32139
摘要： The present invention includes semiconductor circuitry. Such circuitry encompasses a metal silicide layer over a substrate and a layer comprising silicon, nitrogen and oxygen in physical contact with the metal silicide layer. The present invention also includes a gate stack which encompasses a polysilicon layer over a substrate, a metal silicide layer over the polysilicon layer, an antireflective material layer over the metal silicide layer, a silicon nitride layer over the antireflective material layer, and a layer of photoresist over the silicon nitride layer, for photolithographically patterning the layer of photoresist to form a patterned masking layer from the layer of photoresist and transferring a pattern from the patterned masking layer to the silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer. The patterned silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer encompass a gate stack.
摘要翻译：本发明包括半导体电路。这种电路包括衬底上的金属硅化物层和与金属硅化物层物理接触的包含硅，氮和氧的层。本发明还包括一个栅极堆叠，其包围衬底上的多晶硅层，多晶硅层上的金属硅化物层，金属硅化物层上的抗反射材料层，抗反射材料层上的氮化硅层，以及一层在氮化硅层上的光致抗蚀剂，用于光刻地图案化该光致抗蚀剂层以从光致抗蚀剂层形成图案化掩模层，并将图案从图案化掩模层转移到氮化硅层，抗反射材料层，金属硅化物层和多晶硅层。图案化氮化硅层，抗反射材料层，金属硅化物层和多晶硅层包围栅极堆叠。

7. 发明授权

US5312717A Residue free vertical pattern transfer with top surface imaging resists 失效
标题翻译：残留自由垂直图案转印与顶部表面成像抗蚀剂
公开(公告)号：US5312717A
公开(公告)日：1994-05-17
申请号：US949963
申请日：1992-09-24
申请人： Harbans S. Sachdev , John C. Forster , Leo L. Linehan , Scott A. MacDonald , K. Paul L. Muller , Walter E. Mlynko , Linda K. Somerville
发明人： Harbans S. Sachdev , John C. Forster , Leo L. Linehan , Scott A. MacDonald , K. Paul L. Muller , Walter E. Mlynko , Linda K. Somerville
IPC分类号： G03F7/26 , G03F7/36 , G03C5/00
CPC分类号： G03F7/36 , G03F7/265
摘要： A method for transferring a pattern through a photoresist layer in the fabrication of submicron semiconductor devices structures is disclosed. A photoresist is provided on a substrate and the same is imagewise exposed with a desired pattern to form exposed and unexposed patterned areas in the top surface of the photoresist. The photoresist is then baked to form cross-linked regions in the exposed pattern areas of the photoresist. Silylation is then performed to incorporate silicon into the unexposed patterned areas of the photoresist, wherein some incorporation of silicon occurs in the exposed patterned crosslinked areas of the photoresist. The patterned photoresist is subsequently etched using a high density, low pressure, anisotropic O.sub.2 plasma alone to produce residue-free images with vertical wall profiles in the photoresist. This method is particularly advantageous with RFI reactive ion etch systems.
摘要翻译：公开了在制造亚微米半导体器件结构中通过光致抗蚀剂层转印图案的方法。在基板上提供光致抗蚀剂，并将其以所需图案成像曝光，以在光致抗蚀剂的顶表面中形成曝光和未曝光的图案区域。然后将光致抗蚀剂烘烤以在光致抗蚀剂的暴露图案区域中形成交联区域。然后进行硅烷化以将硅结合到光致抗蚀剂的未曝光图案区域中，其中硅的一些掺入发生在光致抗蚀剂的暴露的图案化交联区域中。随后使用高密度，低压，各向异性O 2等离子体蚀刻图案化的光致抗蚀剂，以在光致抗蚀剂中产生具有垂直壁分布的无残留图像。该方法对于RFI反应离子蚀刻系统是特别有利的。

8. 发明授权

US06403285B1 Method for exposing semiconductor wafers in a manner that promotes radial processing uniformity 有权
标题翻译：以促进径向加工均匀性的方式露出半导体晶片的方法
公开(公告)号：US06403285B1
公开(公告)日：2002-06-11
申请号：US09466364
申请日：1999-12-17
申请人： Richard D. Holscher , Linda K. Somerville
发明人： Richard D. Holscher , Linda K. Somerville
IPC分类号： G03F720
CPC分类号： G03F7/70091 , G03F7/701 , G03F7/70466
摘要： A stepper device and method of using the stepper device in which a light source in the stepper generates an annular or multipole pattern of light having a relatively large coherency value that is used to expose inner fields of a photoresist-coated wafer. The light source generates an annular or multipole pattern of light having a relatively small coherency that is used to expose outer fields of the wafer adjacent its edge. The use of light having a relatively small coherence value to expose the outer fields of the wafer causes the exposure width of isolated features to be relatively large compared to the exposure width of dense features. As a result, after etching, the isolated features and the dense features can have the same width since etching is more effective for dense features.
摘要翻译：步进装置和使用步进装置的方法，其中步进器中的光源产生具有相对较大一致性值的环形或多极图案，其用于曝光光致抗蚀剂涂覆的晶片的内部场。光源产生具有相对小的相干性的环形或多极图案，其用于暴露邻近其边缘的晶片的外场。相对于致密特征的曝光宽度，使用具有相对较小相干值的光来露出晶片的外部场域使得隔离特征的曝光宽度相对较大。结果，在蚀刻之后，隔离特征和致密特征可以具有相同的宽度，因为蚀刻对于密集特征更有效。

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